From: Ming Huang <ming.huang@linaro.org>
To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org,
edk2-devel@lists.01.org, graeme.gregory@linaro.org
Cc: ard.biesheuvel@linaro.org, michael.d.kinney@intel.com,
lersek@redhat.com, guoheyi@huawei.com, wanghuiqiang@huawei.com,
huangming23@huawei.com, zhangjinsong2@huawei.com,
huangdaode@hisilicon.com, john.garry@huawei.com,
xinliang.liu@linaro.org, Ming Huang <ming.huang@linaro.org>
Subject: [PATCH edk2-platforms v4 13/31] Hisilicon/D06: Add ACPI Tables for D06
Date: Fri, 24 Aug 2018 00:07:25 +0800 [thread overview]
Message-ID: <20180823160743.45638-14-ming.huang@linaro.org> (raw)
In-Reply-To: <20180823160743.45638-1-ming.huang@linaro.org>
ACPI tables for D06 2P, especially,Hi1620Iort.asl is include smmu
and Hi1620IortNoSmmu.asl is without smmu.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <ming.huang@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
Platform/Hisilicon/D06/D06.dsc | 1 +
Platform/Hisilicon/D06/D06.fdf | 1 +
Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620.inf | 60 +
Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Platform.h | 27 +
Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/CPU.asl | 409 ++++
Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Com.asl | 30 +
Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/DsdtHi1620.asl | 35 +
Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Apei.asl | 93 +
Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Ged.asl | 58 +
Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mbig.asl | 1459 ++++++++++++++
Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mctp.asl | 41 +
Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl | 1216 ++++++++++++
Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Power.asl | 28 +
Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Rde.asl | 47 +
Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Sec.asl | 57 +
Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Socip4_i2c100k.asl | 249 +++
Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Socip4_i2c400k.asl | 249 +++
Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/LpcUart_clk.asl | 49 +
Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Pv680UncorePmu.asl | 1658 ++++++++++++++++
Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/ipmi.asl | 49 +
Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Facs.aslc | 67 +
Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Fadt.aslc | 91 +
Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Gtdt.aslc | 86 +
Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Dbg2.aslc | 86 +
Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Iort.asl | 1989 ++++++++++++++++++++
Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620IortNoSmmu.asl | 1736 +++++++++++++++++
Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Mcfg.aslc | 64 +
Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Slit.aslc | 64 +
Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Spcr.aslc | 81 +
Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Srat.aslc | 166 ++
Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/MadtHi1620.aslc | 375 ++++
31 files changed, 10621 insertions(+)
diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc
index 20d2d2a1b4..9d4a86a4f4 100644
--- a/Platform/Hisilicon/D06/D06.dsc
+++ b/Platform/Hisilicon/D06/D06.dsc
@@ -332,6 +332,7 @@
MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620.inf
Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
#
diff --git a/Platform/Hisilicon/D06/D06.fdf b/Platform/Hisilicon/D06/D06.fdf
index 8cac126ccf..06203dc079 100644
--- a/Platform/Hisilicon/D06/D06.fdf
+++ b/Platform/Hisilicon/D06/D06.fdf
@@ -249,6 +249,7 @@ READ_LOCK_STATUS = TRUE
INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
INF Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
+ INF RuleOverride=ACPITABLE Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620.inf
INF Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
#
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620.inf b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620.inf
new file mode 100644
index 0000000000..8df53a8378
--- /dev/null
+++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620.inf
@@ -0,0 +1,60 @@
+## @file
+#
+# ACPI table data and ASL sources required to boot the platform.
+#
+# Copyright (c) 2014, ARM Ltd. All rights reserved.
+# Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+# Copyright (c) 2018, Linaro Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+# Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = Hi1620AcpiTables
+ FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ Dsdt/DsdtHi1620.asl
+ Facs.aslc
+ Fadt.aslc
+ Gtdt.aslc
+ Hi1620Dbg2.aslc
+ Hi1620Iort.asl
+ Hi1620IortNoSmmu.asl
+ Hi1620Mcfg.aslc
+ Hi1620Slit.aslc
+ Hi1620Spcr.aslc
+ Hi1620Srat.aslc
+ MadtHi1620.aslc
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Hisilicon/Hi1620/Hi1620.dec
+ Silicon/Hisilicon/HisiPkg.dec
+
+[FixedPcd]
+ gArmPlatformTokenSpaceGuid.PcdCoreCount
+ gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Platform.h b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Platform.h
new file mode 100644
index 0000000000..faaeb83781
--- /dev/null
+++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Platform.h
@@ -0,0 +1,27 @@
+/** @file
+*
+* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+* Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015-2018, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+
+#ifndef _HI1620_PLATFORM_H_
+#define _HI1620_PLATFORM_H_
+
+#include <PlatformArch.h>
+
+#define HI1620_WATCHDOG_COUNT 2
+
+#endif
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/CPU.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/CPU.asl
new file mode 100644
index 0000000000..ef8dae4d01
--- /dev/null
+++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/CPU.asl
@@ -0,0 +1,409 @@
+/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+Scope(_SB)
+{
+ //
+ // A57x16 Processor declaration
+ //
+ Device(CPU0) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0)
+ }
+ Device(CPU1) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 1)
+ }
+ Device(CPU2) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 2)
+ }
+ Device(CPU3) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 3)
+ }
+ Device(CPU4) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 4)
+ }
+ Device(CPU5) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 5)
+ }
+ Device(CPU6) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 6)
+ }
+ Device(CPU7) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 7)
+ }
+ Device(CPU8) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 8)
+ }
+ Device(CPU9) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 9)
+ }
+ Device(CP10) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 10)
+ }
+ Device(CP11) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 11)
+ }
+ Device(CP12) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 12)
+ }
+ Device(CP13) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 13)
+ }
+ Device(CP14) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 14)
+ }
+ Device(CP15) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 15)
+ }
+ Device(CP16) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 16)
+ }
+ Device(CP17) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 17)
+ }
+ Device(CP18) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 18)
+ }
+ Device(CP19) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 19)
+ }
+ Device(CP20) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 20)
+ }
+ Device(CP21) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 21)
+ }
+ Device(CP22) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 22)
+ }
+ Device(CP23) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 23)
+ }
+ Device(CP24) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 24)
+ }
+ Device(CP25) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 25)
+ }
+ Device(CP26) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 26)
+ }
+ Device(CP27) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 27)
+ }
+ Device(CP28) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 28)
+ }
+ Device(CP29) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 29)
+ }
+ Device(CP30) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 30)
+ }
+ Device(CP31) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 31)
+ }
+ Device(CP32) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 32)
+ }
+ Device(CP33) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 33)
+ }
+ Device(CP34) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 34)
+ }
+ Device(CP35) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 35)
+ }
+ Device(CP36) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 36)
+ }
+ Device(CP37) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 37)
+ }
+ Device(CP38) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 38)
+ }
+ Device(CP39) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 39)
+ }
+ Device(CP40) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 40)
+ }
+ Device(CP41) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 41)
+ }
+ Device(CP42) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 42)
+ }
+ Device(CP43) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 43)
+ }
+ Device(CP44) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 44)
+ }
+ Device(CP45) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 45)
+ }
+ Device(CP46) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 46)
+ }
+ Device(CP47) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 47)
+ }
+
+ Device(CP48) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 48)
+ }
+ Device(CP49) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 49)
+ }
+ Device(CP50) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 50)
+ }
+ Device(CP51) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 51)
+ }
+ Device(CP52) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 52)
+ }
+ Device(CP53) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 53)
+ }
+ Device(CP54) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 54)
+ }
+ Device(CP55) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 55)
+ }
+ Device(CP56) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 56)
+ }
+ Device(CP57) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 57)
+ }
+ Device(CP58) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 58)
+ }
+ Device(CP59) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 59)
+ }
+ Device(CP60) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 60)
+ }
+ Device(CP61) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 61)
+ }
+ Device(CP62) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 62)
+ }
+ Device(CP63) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 63)
+ }
+ Device(CP64) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 64)
+ }
+ Device(CP65) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 65)
+ }
+ Device(CP66) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 66)
+ }
+ Device(CP67) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 67)
+ }
+ Device(CP68) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 68)
+ }
+ Device(CP69) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 69)
+ }
+ Device(CP70) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 70)
+ }
+ Device(CP71) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 71)
+ }
+ Device(CP72) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 72)
+ }
+ Device(CP73) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 73)
+ }
+ Device(CP74) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 74)
+ }
+ Device(CP75) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 75)
+ }
+ Device(CP76) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 76)
+ }
+ Device(CP77) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 77)
+ }
+ Device(CP78) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 78)
+ }
+ Device(CP79) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 79)
+ }
+ Device(CP80) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 80)
+ }
+ Device(CP81) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 81)
+ }
+ Device(CP82) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 82)
+ }
+ Device(CP83) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 83)
+ }
+ Device(CP84) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 84)
+ }
+ Device(CP85) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 85)
+ }
+ Device(CP86) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 86)
+ }
+ Device(CP87) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 87)
+ }
+ Device(CP88) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 88)
+ }
+ Device(CP89) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 89)
+ }
+ Device(CP90) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 90)
+ }
+ Device(CP91) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 91)
+ }
+ Device(CP92) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 92)
+ }
+ Device(CP93) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 93)
+ }
+ Device(CP94) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 94)
+ }
+ Device(CP95) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 95)
+ }
+}
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Com.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Com.asl
new file mode 100644
index 0000000000..377d171abb
--- /dev/null
+++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Com.asl
@@ -0,0 +1,30 @@
+/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+Scope(_SB)
+{
+ Device(COM0) {
+ Name(_HID, "ARMH0011")
+ Name(_CID, "PL011")
+ Name(_UID, Zero)
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x94080000, 0x1000)
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 141 }
+ })
+ }
+}
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/DsdtHi1620.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/DsdtHi1620.asl
new file mode 100644
index 0000000000..7e26ba22b7
--- /dev/null
+++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/DsdtHi1620.asl
@@ -0,0 +1,35 @@
+/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+#include "Hi1620Platform.h"
+
+DefinitionBlock("DsdtTable.aml", "DSDT", 2, "HISI ", "HIP08 ", EFI_ACPI_ARM_OEM_REVISION) {
+ include ("Com.asl")
+ include ("CPU.asl")
+ include ("Hi1620Pci.asl")
+ include ("Hi1620Mbig.asl")
+ include ("Hi1620Rde.asl")
+ include ("Hi1620Sec.asl")
+ include ("ipmi.asl")
+ include ("LpcUart_clk.asl")
+ include ("Hi1620Ged.asl")
+ include ("Hi1620Power.asl")
+ include ("Hi1620Apei.asl")
+ include ("Hi1620Mctp.asl")
+ include ("Pv680UncorePmu.asl")
+}
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Apei.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Apei.asl
new file mode 100644
index 0000000000..0970ed9b99
--- /dev/null
+++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Apei.asl
@@ -0,0 +1,93 @@
+/** @file
+*
+* Copyright (c) 2018 Hisilicon Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+//Define a control method APEI
+Scope(_SB)
+{
+ Device(GED2) {
+ Name(_HID, "ACPI0013")
+ Name(_UID, 2)
+
+ Name (_CRS, ResourceTemplate () {
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive) {
+ 122
+ }
+ })
+
+ Method (_EVT, 0x1) {
+ Switch(ToInteger(Arg0)) {
+ Case(122) {
+ Notify (\_SB.ERRD, 0x80)
+ }
+ }
+ }
+
+ Method (_STA, 0x0, NotSerialized) {
+ return (0xF);
+ }
+ }
+}
+
+Device (\_SB.ERRD)
+{
+ Name (_HID, EISAID("PNP0C33"))
+ Name (_UID, 0)
+ Method (_STA, 0x0, NotSerialized) {
+ Return(0xF)
+ }
+}
+
+Name(PWCP, Zero) // Platform-Wide Capability value.
+
+Scope (\_SB) {
+ Method (_OSC,4) {
+ // Create DWord-adressable for Arg3 First DWORD.
+ CreateDWordField(Arg3,0,CDW1)
+
+ // Check for proper UUID
+ If (LEqual(Arg0,ToUUID("0811B06E-4A27-44F9-8D60-3CBBC22E7B48"))) {
+ // Create DWord-adressable fields from the Capabilities Buffer
+ CreateDWordField (Arg3,4,TPD2)
+
+ // Save Capabilities DWord2
+ Store (TPD2, PWCP)
+
+ // Set Bit[4]: APEI Support
+ Or (PWCP,0x10,PWCP)
+
+ If (LNotEqual(Arg1,One)) {// Unknown revision
+ Or (CDW1,0x08,CDW1)
+ }
+
+ // Update DWORD2 in the buffer
+ Store (PWCP,TPD2)
+
+ Return (Arg3)
+ }
+ ElseIf (LEqual(Arg0, ToUUID("ed855e0c-6c90-47bf-a62a-26de0fc5ad5c"))) { // Check for WHEA GUID
+ CreateDWordField (Arg3,4,TPD3)
+
+ Or (TPD3, 0x10, TPD3) //Set Bit[4]: APEI support.
+
+ If (LNotEqual(Arg1,One)) {// Unknown revision
+ Or (CDW1,0x08,CDW1)
+ }
+
+ return (Arg3)
+ }
+ Else {
+ Or (CDW1,4,CDW1) // Unrecognized UUID
+ Return (Arg3)
+ }
+ } // End _OSC
+}
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Ged.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Ged.asl
new file mode 100644
index 0000000000..6664c0c681
--- /dev/null
+++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Ged.asl
@@ -0,0 +1,58 @@
+/** @file
+*
+* Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+* Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
+* Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+//
+// Ged
+//
+
+//Define a control method power button
+Scope(_SB)
+{
+ OperationRegion(IOM1, SystemMemory, 0x941900C8, 0x4)
+ Field(IOM1, DWordAcc, NoLock, Preserve) {
+ IMX0, 32,
+ }
+
+ Method (_INI) {
+ Store(IMX0, Local0)
+ And(Local0, 0xFFFFFFFC, Local0)
+ Or(Local0, 0x4, Local0)
+ Store(Local0, IMX0)
+ }
+
+ Device(GED1) {
+ Name(_HID, "ACPI0013")
+ Name(_UID, 0)
+
+ Name (_CRS, ResourceTemplate () {
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive) {
+ 121
+ }
+ })
+
+ Method (_STA, 0x0, NotSerialized) {
+ return (0xF);
+ }
+
+ Method (_EVT, 0x1) {
+ Switch(ToInteger(Arg0)) {
+ Case(121) {
+ Notify (\_SB.PWRB, 0x80)
+ }
+ }
+ }
+ }
+}
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mbig.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mbig.asl
new file mode 100644
index 0000000000..6adf5973a6
--- /dev/null
+++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mbig.asl
@@ -0,0 +1,1459 @@
+/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope(_SB)
+{
+ //This is for S0-TB-L3T0 PMU implementation
+ Device(MB30) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x30)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0xA8080000,
+ 0xA808ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S0-TB-L3T1 PMU implementation
+ Device(MB31) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x31)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0xA8080000,
+ 0xA808ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S0-TB-L3T2 PMU implementation
+ Device(MB32) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x32)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0xA8080000,
+ 0xA808ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S0-TB-L3T3 PMU implementation
+ Device(MB33) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x33)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0xA8080000,
+ 0xA808ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S0-TB-L3T4 PMU implementation
+ Device(MB34) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x34)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0xA8080000,
+ 0xA808ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S0-TB-L3T5 PMU implementation
+ Device(MB35) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x35)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0xA8080000,
+ 0xA808ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S0-TB-DDRC0 PMU implementation
+ Device(MB38) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x38)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0xA8080000,
+ 0xA808ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S0-TB-DDRC1 PMU implementation
+ Device(MB39) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x39)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0xA8080000,
+ 0xA808ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S0-TB-DDRC2 PMU implementation
+ Device(MB3A) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x3A)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0xA8080000,
+ 0xA808ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S0-TB-DDRC3 PMU implementation
+ Device(MB3B) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x3B)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0xA8080000,
+ 0xA808ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S0-TB-HHA0 PMU implementation
+ Device(MB3C) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x3C)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0xA8080000,
+ 0xA808ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S0-TB-HHA1 PMU implementation
+ Device(MB3D) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x3D)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0xA8080000,
+ 0xA808ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S0-TA-L3T0 PMU implementation
+ Device(MB10) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x10)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0xAC080000,
+ 0xAC08ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S0-TA-L3T1 PMU implementation
+ Device(MB11) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x11)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0xAC080000,
+ 0xAC08ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S0-TA-L3T2 PMU implementation
+ Device(MB12) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x12)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0xAC080000,
+ 0xAC08ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S0-TA-L3T3 PMU implementation
+ Device(MB13) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x13)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0xAC080000,
+ 0xAC08ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+
+ //This is for S0-TA-L3T4 PMU implementation
+ Device(MB14) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x14)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0xAC080000,
+ 0xAC08ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S0-TA-L3T5 PMU implementation
+ Device(MB15) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x15)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0xAC080000,
+ 0xAC08ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S0-TA-DDRC0 PMU implementation
+ Device(MB18) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x18)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0xAC080000,
+ 0xAC08ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S0-TA-DDRC1 PMU implementation
+ Device(MB19) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x19)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0xAC080000,
+ 0xAC08ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S0-TA-DDRC2 PMU implementation
+ Device(MB1A) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x1A)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0xAC080000,
+ 0xAC08ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S0-TA-DDRC3 PMU implementation
+ Device(MB1B) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x1B)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0xAC080000,
+ 0xAC08ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S0-TA-HHA0 PMU implementation
+ Device(MB1C) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x1C)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0xAC080000,
+ 0xAC08ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S0-TA-HHA1 PMU implementation
+ Device(MB1D) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x1D)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0xAC080000,
+ 0xAC08ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S1-TB-L3T0 PMU implementation
+ Device(MB70) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x70)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x4000A8080000,
+ 0x4000A808ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S1-TB-L3T1 PMU implementation
+ Device(MB71) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x71)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x4000A8080000,
+ 0x4000A808ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S1-TB-L3T2 PMU implementation
+ Device(MB72) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x72)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x4000A8080000,
+ 0x4000A808ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S1-TB-L3T3 PMU implementation
+ Device(MB73) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x73)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x4000A8080000,
+ 0x4000A808ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+
+ //This is for S1-TB-L3T4 PMU implementation
+ Device(MB74) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x74)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x4000A8080000,
+ 0x4000A808ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S1-TB-L3T5 PMU implementation
+ Device(MB75) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x75)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x4000A8080000,
+ 0x4000A808ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S1-TB-DDRC0 PMU implementation
+ Device(MB78) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x78)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x4000A8080000,
+ 0x4000A808ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S1-TB-DDRC1 PMU implementation
+ Device(MB79) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x79)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x4000A8080000,
+ 0x4000A808ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S1-TB-DDRC2 PMU implementation
+ Device(MB7A) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x7A)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x4000A8080000,
+ 0x4000A808ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S1-TB-DDRC3 PMU implementation
+ Device(MB7B) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x7B)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x4000A8080000,
+ 0x4000A808ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S1-TB-HHA0 PMU implementation
+ Device(MB7C) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x7C)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x4000A8080000,
+ 0x4000A808ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S1-TB-HHA1 PMU implementation
+ Device(MB7D) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x7D)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x4000A8080000,
+ 0x4000A808ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S1-TA-L3T0 PMU implementation
+ Device(MB50) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x50)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x4000AC080000,
+ 0x4000AC08ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S1-TA-L3T1 PMU implementation
+ Device(MB51) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x51)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x4000AC080000,
+ 0x4000AC08ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S1-TA-L3T2 PMU implementation
+ Device(MB52) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x52)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x4000AC080000,
+ 0x4000AC08ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S1-TA-L3T3 PMU implementation
+ Device(MB53) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x53)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x4000AC080000,
+ 0x4000AC08ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+
+ //This is for S1-TA-L3T4 PMU implementation
+ Device(MB54) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x54)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x4000AC080000,
+ 0x4000AC08ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S1-TA-L3T5 PMU implementation
+ Device(MB55) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x55)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x4000AC080000,
+ 0x4000AC08ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S1-TA-DDRC0 PMU implementation
+ Device(MB58) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x58)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x4000AC080000,
+ 0x4000AC08ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S1-TA-DDRC1 PMU implementation
+ Device(MB59) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x59)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x4000AC080000,
+ 0x4000AC08ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S1-TA-DDRC2 PMU implementation
+ Device(MB5A) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x5A)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x4000AC080000,
+ 0x4000AC08ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S1-TA-DDRC3 PMU implementation
+ Device(MB5B) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x5B)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x4000AC080000,
+ 0x4000AC08ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S1-TA-HHA0 PMU implementation
+ Device(MB5C) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x5C)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x4000AC080000,
+ 0x4000AC08ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+
+ //This is for S1-TA-HHA1 PMU implementation
+ Device(MB5D) {
+ Name(_HID, "HISI0152")
+ Name(_UID, 0x5D)
+ Name(_CID, "MBIGen")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x4000AC080000,
+ 0x4000AC08ffff,
+ 0x0,
+ 0x10000
+ )
+ })
+
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 1}
+ }
+ })
+ }
+}
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mctp.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mctp.asl
new file mode 100644
index 0000000000..d039e8a110
--- /dev/null
+++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mctp.asl
@@ -0,0 +1,41 @@
+/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+Scope(_SB)
+{
+ Device(LOC0) {
+ Name(_HID, "HISI02F1")
+ Name(_UID, 0)
+ Name (_CRS, ResourceTemplate () {
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive)
+ {
+ 488,489
+ }
+ })
+ }
+
+ Device(MCT0) {
+ Name(_HID, "HISI0301")
+ Name(_UID, 0)
+ Name (_CRS, ResourceTemplate () {
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI4")
+ {
+ 656
+ }
+ })
+ }
+}
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl
new file mode 100644
index 0000000000..8e3547926a
--- /dev/null
+++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl
@@ -0,0 +1,1216 @@
+/** @file
+*
+* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+* Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+//#include "ArmPlatform.h"
+Scope(_SB)
+{
+ Device (PCI0)
+ { // PCI0 indicate host bridge 0
+ Name (_HID, "PNP0A08") // PCI Express Root Bridge
+ Name (_UID, 0)
+ Name (_CID, "PNP0A03") // Compatible PCI Root Bridge, Compatible ID
+ Name(_SEG, 0) // Segment of this Root complex
+ Name (_BBN, 0x0) // Base Bus Number
+ Name (_CCA, 1) // cache coherence attribute
+
+ Name (_PRT, Package (){
+ // INTx configure for RP0, whoes device number is 0
+ // For ESL/FPGA debug, we should modify this according to
+ // specific hardware configuration.
+ Package () {0xFFFF,0,0,640}, // INT_A
+ Package () {0xFFFF,1,0,641}, // INT_B
+ Package () {0xFFFF,2,0,642}, // INT_C
+ Package () {0xFFFF,3,0,643}, // INT_D
+
+ // This is an example of RP1 INTx configure. Adding or not
+ // adding RPx INTx configure deponds on hardware board topology,
+ // if UEFI enables RPx, RPy, RPz... related INTx configure
+ // should be added
+ Package () {0x4FFFF,0,0,640}, // INT_A
+ Package () {0x4FFFF,1,0,641}, // INT_B
+ Package () {0x4FFFF,2,0,642}, // INT_C
+ Package () {0x4FFFF,3,0,643}, // INT_D
+
+ Package () {0x8FFFF,0,0,640}, // INT_A
+ Package () {0x8FFFF,1,0,641}, // INT_B
+ Package () {0x8FFFF,2,0,642}, // INT_C
+ Package () {0x8FFFF,3,0,643}, // INT_D
+
+ Package () {0xCFFFF,0,0,640}, // INT_A
+ Package () {0xCFFFF,1,0,641}, // INT_B
+ Package () {0xCFFFF,2,0,642}, // INT_C
+ Package () {0xCFFFF,3,0,643}, // INT_D
+
+ Package () {0x10FFFF,0,0,640}, // INT_A
+ Package () {0x10FFFF,1,0,641}, // INT_B
+ Package () {0x10FFFF,2,0,642}, // INT_C
+ Package () {0x10FFFF,3,0,643}, // INT_D
+
+ Package () {0x12FFFF,0,0,640}, // INT_A
+ Package () {0x12FFFF,1,0,641}, // INT_B
+ Package () {0x12FFFF,2,0,642}, // INT_C
+ Package () {0x12FFFF,3,0,643}, // INT_D
+ })
+
+ Method (_CRS, 0, Serialized) {
+ // Method is defined in 19.6.82 in ACPI 6.0 spec
+ Name (RBUF, ResourceTemplate () {
+ // 19.3.3 in ACPI 6.0 spec
+ WordBusNumber (
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ 0, // AddressGranularity
+ 0x00, // AddressMinimum - Minimum Bus Number
+ 0x3f, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 0x40 // RangeLength - Number of Busses
+ )
+ QWordMemory ( // 64-bit prefetch BAR windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Prefetchable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x80000000000, // Min Base Address pci address
+ 0x83fffffffff, // Max Base Address
+ 0x0, // Translate
+ 0x4000000000 // Length, 256G
+ )
+ QWordMemory ( // 32-bit non-prefetch BAR windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0xe0000000, // Min Base Address pci address
+ 0xeffeffff, // Max Base Address
+ 0x0, // Translate
+ 0xfff0000 // Length, 256M - 64K
+ )
+ QWordIO (
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ EntireRange,
+ 0x0, // Granularity
+ 0x0, // Min Base Address
+ 0xffff, // Max Base Address
+ 0xefff0000, // Translate
+ 0x10000 // Length, 64K
+ )}
+ ) // Name(RBUF)
+ Return (RBUF)
+ } // Method(_CRS), this method return RBUF!
+
+ //
+ // OS Control Handoff
+ //
+ Name(SUPP, Zero) // PCI _OSC Support Field value
+ Name(CTRL, Zero) // PCI _OSC Control Field value
+
+ Method(_OSC,4) {
+ // Check for proper UUID
+ If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+ // Create DWord-adressable fields from the Capabilities Buffer
+ CreateDWordField(Arg3,0,CDW1)
+ CreateDWordField(Arg3,4,CDW2)
+ CreateDWordField(Arg3,8,CDW3)
+
+ // Save Capabilities DWord2 & 3
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ // Only allow native hot plug control if OS supports:
+ // ASPM
+ // Clock PM
+ // MSI/MSI-X
+ If(LNotEqual(And(SUPP, 0x16), 0x16)) {
+ And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)
+ }
+
+ // Always allow native PME, AER (no dependencies)
+
+ // Never allow SHPC (no SHPC controller in this system)
+ And(CTRL,0x1D,CTRL)
+
+ If(LNotEqual(Arg1,One)) { // Unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+
+ // Update DWORD3 in the buffer
+ Store(CTRL,CDW3)
+ Return(Arg3)
+ } Else {
+ Or(CDW1,4,CDW1) // Unrecognized UUID
+ Return(Arg3)
+ }
+ } // End _OSC
+
+ Method (_HPX, 0) {
+ Return (Package(2) {
+ Package(6) { // PCI Setting Record
+ 0x00, // Type 0
+ 0x01, // Revision 1
+ 0x08, // CacheLineSize in DWORDS
+ 0x40, // LatencyTimer in PCI clocks
+ 0x01, // Enable SERR (Boolean)
+ 0x01 // Enable PERR (Boolean)
+ },
+
+ Package(18){ // PCI-X Setting Record
+ 0x02, // Type 2
+ 0x01, // Revision 1
+ 0xFFFFFFFF, // Uncorrectable Error Mask Register AND Mask, Keep ->1
+ 0x00000000, // Uncorrectable Error Mask Register OR Mask, keep ->0
+ 0xFFFFFFFF, // Uncorrectable Error Severity Register AND Mask
+ 0x00000000, // Uncorrectable Error Severity Register OR Mask
+ 0xFFFFFFFF, // Correctable Error Mask Register AND Mask
+ 0x00000000, // Correctable Error Mask Register OR Mask
+ 0xFFFFFFFF, // Advanced Error Capabilities and Control Register AND Mask
+ 0x00000000, // Advanced Error Capabilities and Control Register OR Mask
+ 0xFFF7, // Device Control Register AND Mask
+ 0x0007, // Device Control Register OR Mask
+ 0xFFFF, // Link Control Register AND Mask
+ 0x0000, // Link Control Register OR Mask
+ 0xFFFFFFFF, // Secondary Uncorrectable Error Severity Register AND Mask
+ 0x00000000, // Secondary Uncorrectable Error Severity Register OR Mask
+ 0xFFFFFFFF, // Secondary Uncorrectable Error Mask Register AND Mask
+ 0x00000000 // Secondary Uncorrectable Error Mask Register OR Mask
+ }
+ })
+ }
+
+ Method (_STA, 0x0, NotSerialized) {
+ Return (0xf)
+ }
+
+ Method (_PXM, 0, NotSerialized)
+ {
+ Return(0x01)
+ }
+} // Device(PCI0)
+
+
+Device (PCI1)
+{ // PCI1 indicate host bridge 1
+ Name (_HID, "PNP0A08") // PCI Express Root Bridge
+ Name (_UID, 1)
+ Name (_CID, "PNP0A03") // Compatible PCI Root Bridge, Compatible ID
+ Name(_SEG, 0) // Segment of this Root complex
+ Name(_BBN, 0x7b) // Base Bus Number ??
+ Name(_CCA, 1) // cache coherence attribute ??
+ Method (_CRS, 0, Serialized) { // Root complex resources, _CRS: current resource setting
+ Name (RBUF, ResourceTemplate () { // Name: 19.6.87, ResourceTemplate: 19.6.111,
+ WordBusNumber ( // Bus numbers assigned to this root,
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ 0, // AddressGranularity
+ 0x7b, // AddressMinimum - Minimum Bus Number
+ 0x7b, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 0x1 // RangeLength - Number of Busses
+ )
+ QWordMemory ( // 64-bit BAR Windows, where to show this ??
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Prefetchable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x148800000, // Min Base Address pci address ??
+ 0x148ffffff, // Max Base Address
+ 0x0, // Translate
+ 0x800000 // Length, 8M
+ )
+ }) // Name(RBUF)
+ Return (RBUF)
+ } // Method(_CRS), this method return RBUF!
+
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0xf)
+ }
+
+ Method (_PXM, 0, NotSerialized)
+ {
+ Return(0x01)
+ }
+} // Device(PCI1)
+
+Device (PCI2)
+{
+ Name (_HID, "PNP0A08") // PCI Express Root Bridge
+ Name (_UID, 2)
+ Name (_CID, "PNP0A03") // Compatible PCI Root Bridge, Compatible ID
+ Name(_SEG, 0) // Segment of this Root complex
+ Name(_BBN, 0x7a) // Base Bus Number
+ Name(_CCA, 1) // cache coherence attribute ??
+ Name (_PRT, Package (){
+ Package () {0xFFFF,0,0,640}, // INT_A
+ Package () {0xFFFF,1,0,641}, // INT_B
+ Package () {0xFFFF,2,0,642}, // INT_C
+ Package () {0xFFFF,3,0,643}, // INT_D
+ Package () {0x1FFFF,0,0,640}, // INT_A
+ Package () {0x1FFFF,1,0,641}, // INT_B
+ Package () {0x1FFFF,2,0,642}, // INT_C
+ Package () {0x1FFFF,3,0,643}, // INT_D
+ Package () {0x2FFFF,0,0,640}, // INT_A
+ Package () {0x2FFFF,1,0,641}, // INT_B
+ Package () {0x2FFFF,2,0,642}, // INT_C
+ Package () {0x2FFFF,3,0,643}, // INT_D
+ })
+ Method (_CRS, 0, Serialized) { // Root complex resources, _CRS: current resource // setting
+ Name (RBUF, ResourceTemplate () { // Name: 19.6.87, ResourceTemplate: 19.6.111,
+ WordBusNumber ( // Bus numbers assigned to this root,
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ 0, // AddressGranularity
+ 0x7a, // AddressMinimum - Minimum Bus Number
+ 0x7a, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 0x1 // RangeLength - Number of Busses
+ )
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Prefetchable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x20c000000, // Min Base Address pci address
+ 0x20c1fffff, // Max Base Address
+ 0x0, // Translate
+ 0x200000 // Length, 2M
+ )
+ }) // Name(RBUF)
+ Return (RBUF)
+ } // Method(_CRS), this method return RBUF!
+
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0xf)
+ }
+
+ Method (_PXM, 0, NotSerialized)
+ {
+ Return(0x01)
+ }
+}
+
+Device (PCI3)
+{
+ Name (_HID, "PNP0A08") // PCI Express Root Bridge
+ Name (_UID, 3)
+ Name (_CID, "PNP0A03") // Compatible PCI Root Bridge, Compatible ID
+ Name(_SEG, 0) // Segment of this Root complex
+ Name(_BBN, 0x78) // Base Bus Number ??
+ Name(_CCA, 1) // cache coherence attribute ??
+ Method (_CRS, 0, Serialized) { // Root complex resources, _CRS: current resource
+ Name (RBUF, ResourceTemplate () { // Name: 19.6.87, ResourceTemplate: 19.6.111,
+ WordBusNumber ( // Bus numbers assigned to this root,
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ 0, // AddressGranularity
+ 0x78, // AddressMinimum - Minimum Bus Number
+ 0x79, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 0x2 // RangeLength - Number of Busses
+ )
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Prefetchable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x208000000, // Min Base Address pci address
+ 0x208ffffff, // Max Base Address
+ 0x0, // Translate
+ 0x1000000 // Length, 16M
+ )
+ }) // Name(RBUF)
+ Return (RBUF)
+ } // Method(_CRS), this method return RBUF!
+
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0xf)
+ }
+
+ Method (_PXM, 0, NotSerialized)
+ {
+ Return(0x01)
+ }
+}
+
+Device (PCI4)
+{
+ Name (_HID, "PNP0A08") // PCI Express Root Bridge
+ Name (_UID, 4)
+ Name (_CID, "PNP0A03") // Compatible PCI Root Bridge, Compatible ID
+ Name(_SEG, 0) // Segment of this Root complex
+ Name(_BBN, 0x7c) // Base Bus Number ??
+ Name(_CCA, 1) // cache coherence attribute ??
+ Method (_CRS, 0, Serialized) { // Root complex resources, _CRS: current resource
+ Name (RBUF, ResourceTemplate () { // Name: 19.6.87, ResourceTemplate: 19.6.111,
+ WordBusNumber ( // Bus numbers assigned to this root,
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ 0, // AddressGranularity
+ 0x7c, // AddressMinimum - Minimum Bus Number
+ 0x7d, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 0x2 // RangeLength - Number of Busses
+ )
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Prefetchable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x120000000, // Min Base Address pci address
+ 0x13fffffff, // Max Base Address
+ 0x0, // Translate
+ 0x20000000 // Length, 512M
+ )
+ }) // Name(RBUF)
+ Return (RBUF)
+ } // Method(_CRS), this method return RBUF!
+
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+
+ Method (_PXM, 0, NotSerialized)
+ {
+ Return(0x01)
+ }
+}
+
+Device (PCI5)
+{
+ Name (_HID, "PNP0A08") // PCI Express Root Bridge
+ Name (_UID, 5)
+ Name (_CID, "PNP0A03") // Compatible PCI Root Bridge, Compatible ID
+ Name(_SEG, 0) // Segment of this Root complex
+ Name(_BBN, 0x74) // Base Bus Number ??
+ Name(_CCA, 1) // cache coherence attribute ??
+
+ Name (_PRT, Package (){
+ Package () {0x2FFFF,0,0,640}, // INT_A
+ Package () {0x2FFFF,1,0,641}, // INT_B
+ Package () {0x2FFFF,2,0,642}, // INT_C
+ Package () {0x2FFFF,3,0,643}, // INT_D
+ Package () {0x3FFFF,0,0,640}, // INT_A
+ Package () {0x3FFFF,1,0,641}, // INT_B
+ Package () {0x3FFFF,2,0,642}, // INT_C
+ Package () {0x3FFFF,3,0,643}, // INT_D
+ })
+
+ Method (_CRS, 0, Serialized) { // Root complex resources, _CRS: current resource setting
+ Name (RBUF, ResourceTemplate () { // Name: 19.6.87, ResourceTemplate: 19.6.111,
+ WordBusNumber ( // Bus numbers assigned to this root,
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ 0, // AddressGranularity
+ 0x74, // AddressMinimum - Minimum Bus Number
+ 0x76, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 0x3 // RangeLength - Number of Busses
+ )
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Prefetchable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x144000000, // Min Base Address pci address
+ 0x147ffffff, // Max Base Address
+ 0x0, // Translate
+ 0x4000000 // Length, 32M
+ )
+ QWordMemory ( // 32-bit non-prefetch BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0xa2000000, // Min Base Address pci address
+ 0xa2ffffff, // Max Base Address
+ 0x0, // Translate
+ 0x1000000 // Length, 16M
+ )
+ }) // Name(RBUF)
+ Return (RBUF)
+ } // Method(_CRS), this method return RBUF!
+
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0xf)
+ }
+
+ Device (SAS0)
+ {
+ Name (_ADR, 0x00020000)
+ Name (_DSD, Package ()
+ {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package (2) {"sas-addr", Package() {0x50, 0x01, 0x88, 0x20, 0x16, 0x00, 0x00, 0x00}},
+ Package () {"queue-count", 16},
+ Package () {"phy-count", 8},
+ }
+ })
+
+ OperationRegion (CTL, SystemMemory, 0x140070000, 0x1000)
+ Field (CTL, DWordAcc, NoLock, Preserve)
+ {
+ Offset (0xa18),
+ RST, 32,
+ DRST, 32,
+ }
+
+ OperationRegion (TXD, SystemMemory, 0xA2000000, 0x4000)
+ Field (TXD, DwordAcc, NoLock, Preserve)
+ {
+ Offset (0x2350), //port0
+ ST00, 32, //0x2350
+ ST01, 32, //0x2354
+ ST02, 32, //0x2358
+ ST03, 32, //0x235c
+ ST04, 32, //0x2360
+ ST05, 32, //0x2364
+ ST06, 32, //0x2368
+ ST07, 32, //0x236c
+ Offset (0x2750), //port1
+ ST10, 32, //0x2750
+ ST11, 32, //0x2754
+ ST12, 32, //0x2758
+ ST13, 32, //0x275c
+ ST14, 32, //0x2760
+ ST15, 32, //0x2764
+ ST16, 32, //0x2768
+ ST17, 32, //0x276c
+ Offset (0x2b50), //port2
+ ST20, 32, //0x2b50
+ ST21, 32, //0x2b54
+ ST22, 32, //0x2b58
+ ST23, 32, //0x2b5c
+ ST24, 32, //0x2b60
+ ST25, 32, //0x2b64
+ ST26, 32, //0x2b68
+ ST27, 32, //0x2b6c
+ Offset (0x2f50), //port3
+ ST30, 32, //0x2f50
+ ST31, 32, //0x2f54
+ ST32, 32, //0x2f58
+ ST33, 32, //0x2f5c
+ ST34, 32, //0x2f60
+ ST35, 32, //0x2f64
+ ST36, 32, //0x2f68
+ ST37, 32, //0x2f6c
+ Offset (0x3350), //port4
+ ST40, 32, //0x3350
+ ST41, 32, //0x3354
+ ST42, 32, //0x3358
+ ST43, 32, //0x335c
+ ST44, 32, //0x3360
+ ST45, 32, //0x3364
+ ST46, 32, //0x3368
+ ST47, 32, //0x336c
+ Offset (0x3750),//port5
+ ST50, 32, //0x3750
+ ST51, 32, //0x3754
+ ST52, 32, //0x3758
+ ST53, 32, //0x375c
+ ST54, 32, //0x3760
+ ST55, 32, //0x3764
+ ST56, 32, //0x3768
+ ST57, 32, //0x376c
+ Offset (0x3b50), //port6
+ ST60, 32, //0x3b50
+ ST61, 32, //0x3b54
+ ST62, 32, //0x3b58
+ ST63, 32, //0x3b5c
+ ST64, 32, //0x3b60
+ ST65, 32, //0x3b64
+ ST66, 32, //0x3b68
+ ST67, 32, //0x3b6c
+ Offset (0x3f50), //port7
+ ST70, 32, //0x3f50
+ ST71, 32, //0x3f54
+ ST72, 32, //0x3f58
+ ST73, 32, //0x3f5c
+ ST74, 32, //0x3f60
+ ST75, 32, //0x3f64
+ ST76, 32, //0x3f68
+ ST77, 32 //0x3f6c
+ }
+
+ Method (_RST, 0x0, Serialized)
+ {
+ Store(0x7FFFFFF, RST)
+ Sleep(1)
+ Store(0x7FFFFFF, DRST)
+ Sleep(1)
+
+ //port0
+ Store (0x8D04, ST00)
+ Sleep(1)
+ Store (0x8D04, ST01)
+ Sleep(1)
+ Store (0x8D04, ST02)
+ Sleep(1)
+ Store (0x8D04, ST03)
+ Sleep(1)
+ Store (0x8D04, ST05)
+ Sleep(1)
+ Store (0x8D04, ST06)
+ Sleep(1)
+ Store (0x8D04, ST07)
+ Sleep(1)
+
+ //port1
+ Store (0x8D04, ST10)
+ Sleep(1)
+ Store (0x8D04, ST11)
+ Sleep(1)
+ Store (0x8D04, ST12)
+ Sleep(1)
+ Store (0x8D04, ST13)
+ Sleep(1)
+ Store (0x8D04, ST15)
+ Sleep(1)
+ Store (0x8D04, ST16)
+ Sleep(1)
+ Store (0x8D04, ST17)
+ Sleep(1)
+
+ //port2
+ Store (0x8D04, ST20)
+ Sleep(1)
+ Store (0x8D04, ST21)
+ Sleep(1)
+ Store (0x8D04, ST22)
+ Sleep(1)
+ Store (0x8D04, ST23)
+ Sleep(1)
+ Store (0x8D04, ST25)
+ Sleep(1)
+ Store (0x8D04, ST26)
+ Sleep(1)
+ Store (0x8D04, ST27)
+ Sleep(1)
+
+ //port3
+ Store (0x8D04, ST30)
+ Sleep(1)
+ Store (0x8D04, ST31)
+ Sleep(1)
+ Store (0x8D04, ST32)
+ Sleep(1)
+ Store (0x8D04, ST33)
+ Sleep(1)
+ Store (0x8D04, ST35)
+ Sleep(1)
+ Store (0x8D04, ST36)
+ Sleep(1)
+ Store (0x8D04, ST37)
+ Sleep(1)
+
+ //port4
+ Store (0x8D04, ST40)
+ Sleep(1)
+ Store (0x8D04, ST41)
+ Sleep(1)
+ Store (0x8D04, ST42)
+ Sleep(1)
+ Store (0x8D04, ST43)
+ Sleep(1)
+ Store (0x8D04, ST45)
+ Sleep(1)
+ Store (0x8D04, ST46)
+ Sleep(1)
+ Store (0x8D04, ST47)
+ Sleep(1)
+
+ //port5
+ Store (0x8D04, ST50)
+ Sleep(1)
+ Store (0x8D04, ST51)
+ Sleep(1)
+ Store (0x8D04, ST52)
+ Sleep(1)
+ Store (0x8D04, ST53)
+ Sleep(1)
+ Store (0x8D04, ST55)
+ Sleep(1)
+ Store (0x8D04, ST56)
+ Sleep(1)
+ Store (0x8D04, ST57)
+ Sleep(1)
+
+ //port6
+ Store (0x8D04, ST60)
+ Sleep(1)
+ Store (0x8D04, ST61)
+ Sleep(1)
+ Store (0x8D04, ST62)
+ Sleep(1)
+ Store (0x8D04, ST63)
+ Sleep(1)
+ Store (0x8D04, ST65)
+ Sleep(1)
+ Store (0x8D04, ST66)
+ Sleep(1)
+ Store (0x8D04, ST67)
+ Sleep(1)
+
+ //port7
+ Store (0x8D04, ST70)
+ Sleep(1)
+ Store (0x8D04, ST71)
+ Sleep(1)
+ Store (0x8D04, ST72)
+ Sleep(1)
+ Store (0x8D04, ST73)
+ Sleep(1)
+ Store (0x8D04, ST75)
+ Sleep(1)
+ Store (0x8D04, ST76)
+ Sleep(1)
+ Store (0x8D04, ST77)
+ Sleep(1)
+ }
+ }
+
+ Method (_PXM, 0, NotSerialized)
+ {
+ Return(0x01)
+ }
+}
+
+Device (PCI6)
+{ // PCI0 indicate host bridge 0
+ Name (_HID, "PNP0A08") // PCI Express Root Bridge
+ Name (_UID, 6)
+ Name (_CID, "PNP0A03") // Compatible PCI Root Bridge, Compatible ID
+ Name(_SEG, 0) // Segment of this Root complex
+ Name(_BBN, 0x80) // Base Bus Number ??
+ Name(_CCA, 1) // cache coherence attribute ??
+
+ Name (_PRT, Package (){
+ // INTx configure for RP0, whoes device number is 0
+ // For ESL/FPGA debug, we should modify this according to
+ // specific hardware configuration.
+ Package () {0xFFFF,0,0,640}, // INT_A
+ Package () {0xFFFF,1,0,641}, // INT_B
+ Package () {0xFFFF,2,0,642}, // INT_C
+ Package () {0xFFFF,3,0,643}, // INT_D
+
+ // This is an example of RP1 INTx configure. Adding or not
+ // adding RPx INTx configure deponds on hardware board topology,
+ // if UEFI enables RPx, RPy, RPz... related INTx configure
+ // should be added
+ Package () {0x04FFFF,0,0,640}, // INT_A
+ Package () {0x04FFFF,1,0,641}, // INT_B
+ Package () {0x04FFFF,2,0,642}, // INT_C
+ Package () {0x04FFFF,3,0,643}, // INT_D
+
+ Package () {0x08FFFF,0,0,640}, // INT_A
+ Package () {0x08FFFF,1,0,641}, // INT_B
+ Package () {0x08FFFF,2,0,642}, // INT_C
+ Package () {0x08FFFF,3,0,643}, // INT_D
+
+ Package () {0x0CFFFF,0,0,640}, // INT_A
+ Package () {0x0CFFFF,1,0,641}, // INT_B
+ Package () {0x0CFFFF,2,0,642}, // INT_C
+ Package () {0x0CFFFF,3,0,643}, // INT_D
+
+ Package () {0x10FFFF,0,0,640}, // INT_A
+ Package () {0x10FFFF,1,0,641}, // INT_B
+ Package () {0x10FFFF,2,0,642}, // INT_C
+ Package () {0x10FFFF,3,0,643}, // INT_D
+ })
+
+ Method (_CRS, 0, Serialized) { // Root complex resources, _CRS: current resource setting
+ Name (RBUF, ResourceTemplate () { // Name: 19.6.87, ResourceTemplate: 19.6.111,
+ WordBusNumber ( // Bus numbers assigned to this root,
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ 0, // AddressGranularity
+ 0x80, // AddressMinimum - Minimum Bus Number
+ 0x9f, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 0x20 // RangeLength - Number of Busses
+ )
+ QWordMemory ( // 64-bit prefetch BAR windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Prefetchable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x480000000000, // Min Base Address pci address
+ 0x483fffffffff, // Max Base Address
+ 0x0, // Translate
+ 0x4000000000 // Length, 256G
+ )
+ QWordMemory ( // 32-bit non-prefetch BAR windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0xf0000000, // Min Base Address pci address
+ 0xfffeffff, // Max Base Address
+ 0x0, // Translate
+ 0xfff0000 // Length, 256M - 64K
+ )
+ QWordIO (
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ EntireRange,
+ 0x0, // Granularity
+ 0x0, // Min Base Address
+ 0xffff, // Max Base Address
+ 0xffff0000, // Translate
+ 0x10000 // Length, 64K
+ )
+ }) // Name(RBUF)
+ Return (RBUF)
+ } // Method(_CRS), this method return RBUF!
+
+ //
+ // OS Control Handoff
+ //
+ Name(SUPP, Zero) // PCI _OSC Support Field value
+ Name(CTRL, Zero) // PCI _OSC Control Field value
+
+ Method(_OSC,4) {
+ // Check for proper UUID
+ If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+ // Create DWord-adressable fields from the Capabilities Buffer
+ CreateDWordField(Arg3,0,CDW1)
+ CreateDWordField(Arg3,4,CDW2)
+ CreateDWordField(Arg3,8,CDW3)
+
+ // Save Capabilities DWord2 & 3
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ // Only allow native hot plug control if OS supports:
+ // ASPM
+ // Clock PM
+ // MSI/MSI-X
+ If(LNotEqual(And(SUPP, 0x16), 0x16)) {
+ And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)
+ }
+
+ // Always allow native PME, AER (no dependencies)
+
+ // Never allow SHPC (no SHPC controller in this system)
+ And(CTRL,0x1D,CTRL)
+
+ If(LNotEqual(Arg1,One)) { // Unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+
+ // Update DWORD3 in the buffer
+ Store(CTRL,CDW3)
+ Return(Arg3)
+ } Else {
+ Or(CDW1,4,CDW1) // Unrecognized UUID
+ Return(Arg3)
+ }
+ } // End _OSC
+
+ Method (_HPX, 0) {
+ Return (Package(2) {
+ Package(6) { // PCI Setting Record
+ 0x00, // Type 0
+ 0x01, // Revision 1
+ 0x08, // CacheLineSize in DWORDS
+ 0x40, // LatencyTimer in PCI clocks
+ 0x01, // Enable SERR (Boolean)
+ 0x01 // Enable PERR (Boolean)
+ },
+
+ Package(18){ // PCI-X Setting Record
+ 0x02, // Type 2
+ 0x01, // Revision 1
+ 0xFFFFFFFF, // Uncorrectable Error Mask Register AND Mask, Keep ->1
+ 0x00000000, // Uncorrectable Error Mask Register OR Mask, keep ->0
+ 0xFFFFFFFF, // Uncorrectable Error Severity Register AND Mask
+ 0x00000000, // Uncorrectable Error Severity Register OR Mask
+ 0xFFFFFFFF, // Correctable Error Mask Register AND Mask
+ 0x00000000, // Correctable Error Mask Register OR Mask
+ 0xFFFFFFFF, // Advanced Error Capabilities and Control Register AND Mask
+ 0x00000000, // Advanced Error Capabilities and Control Register OR Mask
+ 0xFFF7, // Device Control Register AND Mask
+ 0x0007, // Device Control Register OR Mask
+ 0xFFFF, // Link Control Register AND Mask
+ 0x0000, // Link Control Register OR Mask
+ 0xFFFFFFFF, // Secondary Uncorrectable Error Severity Register AND Mask
+ 0x00000000, // Secondary Uncorrectable Error Severity Register OR Mask
+ 0xFFFFFFFF, // Secondary Uncorrectable Error Mask Register AND Mask
+ 0x00000000 // Secondary Uncorrectable Error Mask Register OR Mask
+ }
+ })
+ }
+
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0xf)
+ }
+
+ Method (_PXM, 0, NotSerialized)
+ {
+ Return(0x03)
+ }
+} // Device(PCI6)
+
+
+Device (PCI7)
+{ // PCI1 indicate host bridge 1
+ Name (_HID, "PNP0A08") // PCI Express Root Bridge
+ Name (_UID, 7)
+ Name (_CID, "PNP0A03") // Compatible PCI Root Bridge, Compatible ID
+ Name(_SEG, 0) // Segment of this Root complex
+ Name(_BBN, 0xbb) // Base Bus Number ??
+ Name(_CCA, 1) // cache coherence attribute ??
+ Method (_CRS, 0, Serialized) { // Root complex resources, _CRS: current resource setting
+ Name (RBUF, ResourceTemplate () { // Name: 19.6.87, ResourceTemplate: 19.6.111,
+ WordBusNumber ( // Bus numbers assigned to this root,
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ 0, // AddressGranularity
+ 0xbb, // AddressMinimum - Minimum Bus Number
+ 0xbb, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 0x1 // RangeLength - Number of Busses
+ )
+ QWordMemory ( // 64-bit BAR Windows, where to show this ??
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Prefetchable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x400148800000, // Min Base Address pci address ??
+ 0x400148ffffff, // Max Base Address
+ 0x0, // Translate
+ 0x800000 // Length, 8M
+ )
+ }) // Name(RBUF)
+ Return (RBUF)
+ } // Method(_CRS), this method return RBUF!
+
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0xf)
+ }
+
+ Method (_PXM, 0, NotSerialized)
+ {
+ Return(0x03)
+ }
+} // Device(PCI7)
+
+Device (PCI8)
+{
+ Name (_HID, "PNP0A08") // PCI Express Root Bridge
+ Name (_UID, 8)
+ Name (_CID, "PNP0A03") // Compatible PCI Root Bridge, Compatible ID
+ Name(_SEG, 0) // Segment of this Root complex
+ Name(_BBN, 0xba) // Base Bus Number
+ Name(_CCA, 1) // cache coherence attribute ??
+ Name (_PRT, Package (){
+ Package () {0xFFFF,0,0,640}, // INT_A
+ Package () {0xFFFF,1,0,641}, // INT_B
+ Package () {0xFFFF,2,0,642}, // INT_C
+ Package () {0xFFFF,3,0,643}, // INT_D
+ Package () {0x1FFFF,0,0,640}, // INT_A
+ Package () {0x1FFFF,1,0,641}, // INT_B
+ Package () {0x1FFFF,2,0,642}, // INT_C
+ Package () {0x1FFFF,3,0,643}, // INT_D
+ Package () {0x2FFFF,0,0,640}, // INT_A
+ Package () {0x2FFFF,1,0,641}, // INT_B
+ Package () {0x2FFFF,2,0,642}, // INT_C
+ Package () {0x2FFFF,3,0,643}, // INT_D
+ })
+
+ Method (_CRS, 0, Serialized) { // Root complex resources, _CRS: current resource // setting
+ Name (RBUF, ResourceTemplate () { // Name: 19.6.87, ResourceTemplate: 19.6.111,
+ WordBusNumber ( // Bus numbers assigned to this root,
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ 0, // AddressGranularity
+ 0xba, // AddressMinimum - Minimum Bus Number
+ 0xba, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 0x1 // RangeLength - Number of Busses
+ )
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Prefetchable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x40020c000000, // Min Base Address pci address
+ 0x40020c1fffff, // Max Base Address
+ 0x0, // Translate
+ 0x200000 // Length, 2M
+ )
+ }) // Name(RBUF)
+ Return (RBUF)
+ } // Method(_CRS), this method return RBUF!
+
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0xf)
+ }
+
+ Method (_PXM, 0, NotSerialized)
+ {
+ Return(0x03)
+ }
+}// Device(PCI8)
+
+Device (PCI9)
+{
+ Name (_HID, "PNP0A08") // PCI Express Root Bridge
+ Name (_UID, 9)
+ Name (_CID, "PNP0A03") // Compatible PCI Root Bridge, Compatible ID
+ Name(_SEG, 0) // Segment of this Root complex
+ Name(_BBN, 0xb8) // Base Bus Number ??
+ Name(_CCA, 1) // cache coherence attribute ??
+ Method (_CRS, 0, Serialized) { // Root complex resources, _CRS: current resource // setting
+ Name (RBUF, ResourceTemplate () { // Name: 19.6.87, ResourceTemplate: 19.6.111,
+ WordBusNumber ( // Bus numbers assigned to this root,
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ 0, // AddressGranularity
+ 0xb8, // AddressMinimum - Minimum Bus Number
+ 0xb9, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 0x2 // RangeLength - Number of Busses
+ )
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Prefetchable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x400208000000, // Min Base Address pci address
+ 0x400208ffffff, // Max Base Address
+ 0x0, // Translate
+ 0x1000000 // Length, 16M
+ )
+ }) // Name(RBUF)
+ Return (RBUF)
+ } // Method(_CRS), this method return RBUF!
+
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0xf)
+ }
+
+ Method (_PXM, 0, NotSerialized)
+ {
+ Return(0x03)
+ }
+}// Device(PCI9)
+
+Device (PCIA)
+{
+ Name (_HID, "PNP0A08") // PCI Express Root Bridge
+ Name (_UID, 0xA)
+ Name (_CID, "PNP0A03") // Compatible PCI Root Bridge, Compatible ID
+ Name(_SEG, 0) // Segment of this Root complex
+ Name(_BBN, 0xbc) // Base Bus Number ??
+ Name(_CCA, 1) // cache coherence attribute ??
+ Method (_CRS, 0, Serialized) { // Root complex resources, _CRS: current resource
+ Name (RBUF, ResourceTemplate () { // Name: 19.6.87, ResourceTemplate: 19.6.111,
+ WordBusNumber ( // Bus numbers assigned to this root,
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ 0, // AddressGranularity
+ 0xbc, // AddressMinimum - Minimum Bus Number
+ 0xbd, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 0x2 // RangeLength - Number of Busses
+ )
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Prefetchable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x400120000000, // Min Base Address pci address
+ 0x40013fffffff, // Max Base Address
+ 0x0, // Translate
+ 0x20000000 // Length, 512M
+ )
+ }) // Name(RBUF)
+ Return (RBUF)
+ } // Method(_CRS), this method return RBUF!
+
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+
+ Method (_PXM, 0, NotSerialized)
+ {
+ Return(0x03)
+ }
+}// Device(PCIA)
+
+Device (PCIB)
+{
+ Name (_HID, "PNP0A08") // PCI Express Root Bridge
+ Name (_UID, 0xB)
+ Name (_CID, "PNP0A03") // Compatible PCI Root Bridge, Compatible ID
+ Name(_SEG, 0) // Segment of this Root complex
+ Name(_BBN, 0xb4) // Base Bus Number ??
+ Name(_CCA, 1) // cache coherence attribute ??
+
+ Name (_PRT, Package (){
+ Package () {0x2FFFF,0,0,640}, // INT_A
+ Package () {0x2FFFF,1,0,641}, // INT_B
+ Package () {0x2FFFF,2,0,642}, // INT_C
+ Package () {0x2FFFF,3,0,643}, // INT_D
+ Package () {0x3FFFF,0,0,640}, // INT_A
+ Package () {0x3FFFF,1,0,641}, // INT_B
+ Package () {0x3FFFF,2,0,642}, // INT_C
+ Package () {0x3FFFF,3,0,643}, // INT_D
+ })
+
+ Method (_CRS, 0, Serialized) { // Root complex resources, _CRS: current resource setting
+ Name (RBUF, ResourceTemplate () { // Name: 19.6.87, ResourceTemplate: 19.6.111,
+ WordBusNumber ( // Bus numbers assigned to this root,
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ 0, // AddressGranularity
+ 0xb4, // AddressMinimum - Minimum Bus Number
+ 0xb6, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 0x3 // RangeLength - Number of Busses
+ )
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Prefetchable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x400144000000, // Min Base Address pci address
+ 0x400147ffffff, // Max Base Address
+ 0x0, // Translate
+ 0x4000000 // Length, 32M
+ )
+ QWordMemory ( // 32-bit non-prefetch BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0xa3000000, // Min Base Address pci address
+ 0xa3ffffff, // Max Base Address
+ 0x0, // Translate
+ 0x1000000 // Length, 16M
+ )
+ }) // Name(RBUF)
+ Return (RBUF)
+ } // Method(_CRS), this method return RBUF!
+
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0xf)
+ }
+
+ Method (_PXM, 0, NotSerialized)
+ {
+ Return(0x03)
+ }
+}
+}
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Power.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Power.asl
new file mode 100644
index 0000000000..39553e01af
--- /dev/null
+++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Power.asl
@@ -0,0 +1,28 @@
+/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+Scope(_SB)
+{
+ Device(PWRB) {
+ Name(_HID, "PNP0C0C")
+ Name(_UID, Zero)
+ Method(_STA, 0x0, NotSerialized) {
+ Return(0xF)
+ }
+ }
+}
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Rde.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Rde.asl
new file mode 100644
index 0000000000..1dcf1bba7e
--- /dev/null
+++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Rde.asl
@@ -0,0 +1,47 @@
+/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+Scope(_SB)
+{
+ Device(RDE0) {
+ Name(_HID, "HISI0201")
+ Name(_UID, 0)
+ Name(_CCA, 1)
+ Name (_CRS, ResourceTemplate () {
+ //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000)
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x209000000,
+ 0x209ffffff,
+ 0x0,
+ 0x01000000
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI2")
+ { 586,587,588,589,590,591,592,593,594,595,596,597,598,599,600,601,
+ 602,603,604,605,606,607,608,609,610,611,612,613,614,615,616,617
+ }
+ })
+ }
+}
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Sec.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Sec.asl
new file mode 100644
index 0000000000..bba455468e
--- /dev/null
+++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Sec.asl
@@ -0,0 +1,57 @@
+/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2018, Linaro Limited. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+Scope(_SB)
+{
+ Device(SEC0) {
+ Name (_HID, "HISI0200")
+ Name(_UID, 0)
+ Name(_CCA, 1)
+ Name (_CRS, ResourceTemplate () {
+ //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000)
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x141000000,
+ 0x141ffffff,
+ 0x0,
+ 0x01000000
+ )
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI3")
+ {
+ 624,625,626,627,628,629,630,631,632,633,634,635,636,637,638,639,
+ 640,641,642,643,644,645,646,647,648,649,650,651,652,653,654,655
+ }
+ })
+ }
+
+ Device(SEC1) {
+ Name(_HID, "HISI0200")
+ Name(_UID, 1)
+ Name (_CRS, ResourceTemplate () {
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive)
+ { 466,467
+ }
+ })
+ }
+}
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Socip4_i2c100k.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Socip4_i2c100k.asl
new file mode 100644
index 0000000000..622355ade0
--- /dev/null
+++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Socip4_i2c100k.asl
@@ -0,0 +1,249 @@
+/** @file
+*
+* Copyright (c) 2018 Hisilicon Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+//
+// GPIO
+//
+
+//#include "ArmPlatform.h"
+Scope(_SB)
+{
+Device(GPO0) {
+ Name(_HID, "HISI0181")
+ Name(_ADR, 0)
+ Name(_UID, 0)
+
+ Name (_CRS, ResourceTemplate () {
+ //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000)
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x201120000,
+ 0x20112ffff,
+ 0x0,
+ 0x10000
+ )
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,)
+ {
+ 476,
+ }
+ })
+
+ Device(PRTa) {
+ Name(_ADR, 0)
+ Name(_UID, 0)
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"reg", 0},
+ Package () {"snps,nr-gpios", 32},
+ }
+ })
+ }
+}
+
+/**
+*I2C for 100k release
+**/
+Device(I2C0) {
+ Name(_HID, "HISI02A2")
+ Name(_ADR, 0)
+ Name(_UID, 0)
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"i2c-sda-falling-time-ns", 913},
+ Package () {"i2c-scl-falling-time-ns", 303},
+ Package () {"i2c-sda-hold-time-ns", 1000},
+ Package () {"clock-frequency", 100000},
+ }
+ })
+
+ Name (_CRS, ResourceTemplate () {
+ //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000)
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x201160000,
+ 0x20116ffff,
+ 0x0,
+ 0x10000
+ )
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,)
+ {
+ 480,
+ }
+ })
+}
+
+
+/**
+*I2C for 100k vtof
+**/
+Device(I2C2) {
+ Name(_HID, "HISI0182")
+ Name(_ADR, 0)
+ Name(_UID, 0)
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"i2c-sda-falling-time-ns", 913},
+ Package () {"i2c-scl-falling-time-ns", 303},
+ Package () {"i2c-sda-hold-time-ns", 1000},
+ Package () {"clock-frequency", 100000},
+ }
+ })
+
+ Name (_CRS, ResourceTemplate () {
+ //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000)
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x201160000,
+ 0x20116ffff,
+ 0x0,
+ 0x10000
+ )
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,)
+ {
+ 480,
+ }
+ })
+}
+
+/**
+*I2C for 400k fpga
+**/
+Device(I2C3) {
+ Name(_HID, "HISI0183")
+ Name(_ADR, 0)
+ Name(_UID, 0)
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"i2c-sda-falling-time-ns", 300},
+ Package () {"i2c-scl-falling-time-ns", 100},
+ Package () {"i2c-sda-hold-time-ns", 250},
+ Package () {"clock-frequency", 400000},
+ }
+ })
+
+ Name (_CRS, ResourceTemplate () {
+ //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000)
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x201160000,
+ 0x20116ffff,
+ 0x0,
+ 0x10000
+ )
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,)
+ {
+ 480,
+ }
+ })
+}
+
+Device(LPC) {
+ Name(_HID, "HISI0191")
+ Name(_ADR, 0)
+ Name(_UID, 0)
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ }
+ })
+
+ Name (_CRS, ResourceTemplate () {
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,)
+ {
+ 484,
+ 490
+ }
+ })
+}
+
+Device(NAD) {
+ Name(_HID, "HISI0192")
+ Name(_ADR, 0)
+ Name(_UID, 0)
+ Name(_CCA, 1)
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"nand-bus-width", 8},
+ Package () {"nand-ecc-mode", "hw"},
+ Package () {"nand-ecc-strength", 24},
+ Package () {"nand-ecc-step-size", 1024},
+ }
+ })
+
+ Name (_CRS, ResourceTemplate () {
+ //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000)
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x206220000,
+ 0x20622ffff,
+ 0x0,
+ 0x10000
+ )
+
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x206210000,
+ 0x20621ffff,
+ 0x0,
+ 0x10000
+ )
+
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,)
+ {
+ 483,
+ }
+ })
+}
+}
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Socip4_i2c400k.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Socip4_i2c400k.asl
new file mode 100644
index 0000000000..5db4284467
--- /dev/null
+++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Socip4_i2c400k.asl
@@ -0,0 +1,249 @@
+/** @file
+*
+* Copyright (c) 2018 Hisilicon Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+//
+// GPIO
+//
+
+//#include "ArmPlatform.h"
+Scope(_SB)
+{
+ Device(GPO0) {
+ Name(_HID, "HISI0181")
+ Name(_ADR, 0)
+ Name(_UID, 0)
+
+ Name (_CRS, ResourceTemplate () {
+ //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000)
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x201120000,
+ 0x20112ffff,
+ 0x0,
+ 0x10000
+ )
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,)
+ {
+ 476,
+ }
+ })
+
+ Device(PRTa) {
+ Name(_ADR, 0)
+ Name(_UID, 0)
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"reg", 0},
+ Package () {"snps,nr-gpios", 32},
+ }
+ })
+ }
+
+ }
+
+/**
+*I2C for 400k release
+**/
+Device(I2C1) {
+ Name(_HID, "HISI02A2")
+ Name(_ADR, 0)
+ Name(_UID, 0)
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"i2c-sda-falling-time-ns", 500},
+ Package () {"i2c-scl-falling-time-ns", 100},
+ Package () {"i2c-sda-hold-time-ns", 250},
+ Package () {"clock-frequency", 400000},
+ }
+ })
+
+ Name (_CRS, ResourceTemplate () {
+ //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000)
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x201160000,
+ 0x20116ffff,
+ 0x0,
+ 0x10000
+ )
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,)
+ {
+ 480,
+ }
+ })
+}
+
+/**
+*I2C for 100k vtof
+**/
+Device(I2C2) {
+ Name(_HID, "HISI0182")
+ Name(_ADR, 0)
+ Name(_UID, 0)
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"i2c-sda-falling-time-ns", 913},
+ Package () {"i2c-scl-falling-time-ns", 303},
+ Package () {"i2c-sda-hold-time-ns", 1000},
+ Package () {"clock-frequency", 100000},
+ }
+ })
+
+ Name (_CRS, ResourceTemplate () {
+ //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000)
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x201160000,
+ 0x20116ffff,
+ 0x0,
+ 0x10000
+ )
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,)
+ {
+ 480,
+ }
+ })
+}
+
+/**
+*I2C for 400k fpga
+**/
+Device(I2C3) {
+ Name(_HID, "HISI0183")
+ Name(_ADR, 0)
+ Name(_UID, 0)
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"i2c-sda-falling-time-ns", 300},
+ Package () {"i2c-scl-falling-time-ns", 100},
+ Package () {"i2c-sda-hold-time-ns", 250},
+ Package () {"clock-frequency", 400000},
+ }
+ })
+
+ Name (_CRS, ResourceTemplate () {
+ //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000)
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x201160000,
+ 0x20116ffff,
+ 0x0,
+ 0x10000
+ )
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,)
+ {
+ 480,
+ }
+ })
+}
+
+Device(LPC) {
+ Name(_HID, "HISI0191")
+ Name(_ADR, 0)
+ Name(_UID, 0)
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ }
+ })
+
+ Name (_CRS, ResourceTemplate () {
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,)
+ {
+ 484,
+ 490
+ }
+ })
+}
+
+Device(NAD) {
+ Name(_HID, "HISI0192")
+ Name(_ADR, 0)
+ Name(_UID, 0)
+ Name(_CCA, 1)
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"nand-bus-width", 8},
+ Package () {"nand-ecc-mode", "hw"},
+ Package () {"nand-ecc-strength", 24},
+ Package () {"nand-ecc-step-size", 1024},
+ }
+ })
+
+ Name (_CRS, ResourceTemplate () {
+ //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000)
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x206220000,
+ 0x20622ffff,
+ 0x0,
+ 0x10000
+ )
+
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x206210000,
+ 0x20621ffff,
+ 0x0,
+ 0x10000
+ )
+
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,)
+ {
+ 483,
+ }
+ })
+}
+}
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/LpcUart_clk.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/LpcUart_clk.asl
new file mode 100644
index 0000000000..14e36353ad
--- /dev/null
+++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/LpcUart_clk.asl
@@ -0,0 +1,49 @@
+/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+Scope(_SB)
+{
+ Device(UART) {
+ Name(_HID, "PNP0501")
+ Name(_UID, 0)
+ Name(_CCA, 1)
+ Name(_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"clock-frequency", 1843200},
+ }
+ })
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x3f00003f8,
+ 0x3f00003ff,
+ 0x0,
+ 0x8
+ )
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 484 }
+ })
+ }
+}
+
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Pv680UncorePmu.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Pv680UncorePmu.asl
new file mode 100644
index 0000000000..65c3eccf0a
--- /dev/null
+++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Pv680UncorePmu.asl
@@ -0,0 +1,1658 @@
+/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2017, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2017, Linaro Limited. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+Scope(_SB)
+{
+ // L3T0 for S0_TB(DieID:3)
+ Device (L300) {
+ Name (_HID, "HISI0213") // _HID: Hardware ID
+ Name (_UID, 0) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // L3T address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x90180000, // Min Base Address
+ 0x9018FFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB30")
+ {
+ 832,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x03},
+ Package () {"hisilicon,ccl-id", 0x00},
+ }
+ })
+
+ }
+ // L3T1 for S0_TB(DieID:3)
+ Device (L301) {
+ Name (_HID, "HISI0213") // _HID: Hardware ID
+ Name (_UID, 1) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // L3T address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x90190000, // Min Base Address
+ 0x9019FFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB31")
+ {
+ 833,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x03},
+ Package () {"hisilicon,ccl-id", 0x01},
+ }
+ })
+
+ }
+
+ // L3T2 for S0_TB(DieID:3)
+ Device (L302) {
+ Name (_HID, "HISI0213") // _HID: Hardware ID
+ Name (_UID, 2) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // L3T address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x901A0000, // Min Base Address
+ 0x901AFFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB32")
+ {
+ 834,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x03},
+ Package () {"hisilicon,ccl-id", 0x02},
+ }
+ })
+
+ }
+
+ // L3T3 for S0_TB(DieID:3)
+ Device (L303) {
+ Name (_HID, "HISI0213") // _HID: Hardware ID
+ Name (_UID, 3) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // L3T address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x901B0000, // Min Base Address
+ 0x901BFFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB33")
+ {
+ 835,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x03},
+ Package () {"hisilicon,ccl-id", 0x03},
+ }
+ })
+
+ }
+ // L3T4 for S0_TB(DieID:3)
+ Device (L304) {
+ Name (_HID, "HISI0213") // _HID: Hardware ID
+ Name (_UID, 4) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // L3T address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x901C0000, // Min Base Address
+ 0x901CFFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB34")
+ {
+ 836,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x03},
+ Package () {"hisilicon,ccl-id", 0x04},
+ }
+ })
+
+ }
+ // L3T5 for S0_TB(DieID:3)
+ Device (L305) {
+ Name (_HID, "HISI0213") // _HID: Hardware ID
+ Name (_UID, 5) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // L3T address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x901D0000, // Min Base Address
+ 0x901DFFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB35")
+ {
+ 837,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x03},
+ Package () {"hisilicon,ccl-id", 0x05},
+ }
+ })
+
+ }
+
+ // DDRC0 for S0_TB(DieID:3)
+ Device (DDR0) {
+ Name (_HID, "HISI0233") // _HID: Hardware ID
+ Name (_UID, 0) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // DDRC address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x94D20000, // Min Base Address
+ 0x94D2FFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB38")
+ {
+ 844,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x03},
+ Package () {"hisilicon,ch-id", 0x0},
+ }
+ })
+
+ }
+ // DDRC1 for S0_TB(DieID:3)
+ Device (DDR1) {
+ Name (_HID, "HISI0233") // _HID: Hardware ID
+ Name (_UID, 1) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // DDRC address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x94D30000, // Min Base Address
+ 0x94D3FFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB39")
+ {
+ 845,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x03},
+ Package () {"hisilicon,ch-id", 0x1},
+ }
+ })
+
+ }
+ // DDRC2 for S0_TB(DieID:3)
+ Device (DDR2) {
+ Name (_HID, "HISI0233") // _HID: Hardware ID
+ Name (_UID, 2) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // DDRC address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x94D40000, // Min Base Address
+ 0x94D4FFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB3A")
+ {
+ 846,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x03},
+ Package () {"hisilicon,ch-id", 0x2},
+ }
+ })
+
+ }
+ // DDRC3 for S0_TB(DieID:3)
+ Device (DDR3) {
+ Name (_HID, "HISI0233") // _HID: Hardware ID
+ Name (_UID, 3) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // DDRC address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x94D50000, // Min Base Address
+ 0x94D5FFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB3B")
+ {
+ 847,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x03},
+ Package () {"hisilicon,ch-id", 0x3},
+ }
+ })
+
+ }
+
+ // HHA0 for S0_TB(DieID:3)
+ Device (HHA0) {
+ Name (_HID, "HISI0243") // _HID: Hardware ID
+ Name (_UID, 0) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // HHA address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x90120000, // Min Base Address
+ 0x9012FFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB3C")
+ {
+ 848,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x03}
+ }
+ })
+ }
+
+ // HHA1 for S0_TB(DieID:3)
+ Device (HHA1) {
+ Name (_HID, "HISI0243") // _HID: Hardware ID
+ Name (_UID, 1) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // HHA address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x90130000, // Min Base Address
+ 0x9013FFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB3D")
+ {
+ 849,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x03}
+ }
+ })
+ }
+
+ // L3T0 for S0_TA(DieID:1)
+ Device (L308) {
+ Name (_HID, "HISI0213") // _HID: Hardware ID
+ Name (_UID, 0x08) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // L3T address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x98180000, // Min Base Address
+ 0x9818FFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB10")
+ {
+ 832,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x01},
+ Package () {"hisilicon,ccl-id", 0x00},
+ }
+ })
+
+ }
+ // L3T1 for S0_TA(DieID:1)
+ Device (L309) {
+ Name (_HID, "HISI0213") // _HID: Hardware ID
+ Name (_UID, 0x09) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // L3T address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x98190000, // Min Base Address
+ 0x9819FFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB11")
+ {
+ 833,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x01},
+ Package () {"hisilicon,ccl-id", 0x01},
+ }
+ })
+
+ }
+
+ // L3T2 for S0_TA(DieID:1)
+ Device (L30A) {
+ Name (_HID, "HISI0213") // _HID: Hardware ID
+ Name (_UID, 0x0A) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // L3T address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x981A0000, // Min Base Address
+ 0x981AFFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB12")
+ {
+ 834,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x01},
+ Package () {"hisilicon,ccl-id", 0x02},
+ }
+ })
+
+ }
+
+ // L3T3 for S0_TA(DieID:1)
+ Device (L30B) {
+ Name (_HID, "HISI0213") // _HID: Hardware ID
+ Name (_UID, 0x0B) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // L3T address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x981B0000, // Min Base Address
+ 0x981BFFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB13")
+ {
+ 835,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x01},
+ Package () {"hisilicon,ccl-id", 0x03},
+ }
+ })
+
+ }
+ // L3T4 for S0_TA(DieID:1)
+ Device (L30C) {
+ Name (_HID, "HISI0213") // _HID: Hardware ID
+ Name (_UID, 0x0C) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // L3T address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x981C0000, // Min Base Address
+ 0x981CFFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB14")
+ {
+ 836,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x01},
+ Package () {"hisilicon,ccl-id", 0x04},
+ }
+ })
+
+ }
+ // L3T5 for S0_TA(DieID:1)
+ Device (L30D) {
+ Name (_HID, "HISI0213") // _HID: Hardware ID
+ Name (_UID, 0x0D) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // L3T address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x981D0000, // Min Base Address
+ 0x981DFFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB15")
+ {
+ 837,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x01},
+ Package () {"hisilicon,ccl-id", 0x05},
+ }
+ })
+
+ }
+
+ // DDRC0 for S0_TA(DieID:1)
+ Device (DDR4) {
+ Name (_HID, "HISI0233") // _HID: Hardware ID
+ Name (_UID, 4) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // L3T address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x9CD20000, // Min Base Address
+ 0x9CD2FFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB18")
+ {
+ 844,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x01},
+ Package () {"hisilicon,ch-id", 0x0},
+ }
+ })
+
+ }
+ // DDRC1 for S0_TA(DieID:1)
+ Device (DDR5) {
+ Name (_HID, "HISI0233") // _HID: Hardware ID
+ Name (_UID, 5) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // L3T address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x9CD30000, // Min Base Address
+ 0x9CD3FFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB19")
+ {
+ 845,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x01},
+ Package () {"hisilicon,ch-id", 0x1},
+ }
+ })
+
+ }
+ // DDRC2 for S0_TA(DieID:1)
+ Device (DDR6) {
+ Name (_HID, "HISI0233") // _HID: Hardware ID
+ Name (_UID, 6) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // L3T address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x9CD40000, // Min Base Address
+ 0x9CD4FFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB1A")
+ {
+ 846,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x01},
+ Package () {"hisilicon,ch-id", 0x2},
+ }
+ })
+
+ }
+ // DDRC3 for S0_TA(DieID:1)
+ Device (DDR7) {
+ Name (_HID, "HISI0233") // _HID: Hardware ID
+ Name (_UID, 7) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // L3T address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x9CD50000, // Min Base Address
+ 0x9CD5FFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB1B")
+ {
+ 847,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x01},
+ Package () {"hisilicon,ch-id", 0x3},
+ }
+ })
+ }
+
+ // HHA0 for S0_TA(DieID:1)
+ Device (HHA2) {
+ Name (_HID, "HISI0243") // _HID: Hardware ID
+ Name (_UID, 2) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // HHA address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x98120000, // Min Base Address
+ 0x9812FFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB1C")
+ {
+ 848,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x01}
+ }
+ })
+ }
+
+ // HHA1 for S0_TA(DieID:1)
+ Device (HHA3) {
+ Name (_HID, "HISI0243") // _HID: Hardware ID
+ Name (_UID, 3) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // HHA address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x98130000, // Min Base Address
+ 0x9813FFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB1D")
+ {
+ 849,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x01}
+ }
+ })
+ }
+
+ // It is the list PMU node of Socket1
+ // L3T0 for S1_TB(DieID:7)
+ Device (L310) {
+ Name (_HID, "HISI0213") // _HID: Hardware ID
+ Name (_UID, 0x10) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // L3T address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x400090180000, // Min Base Address
+ 0x40009018FFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB70")
+ {
+ 832,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x07},
+ Package () {"hisilicon,ccl-id", 0x00},
+ }
+ })
+
+ }
+ // L3T1 for S1_TB(DieID:7)
+ Device (L311) {
+ Name (_HID, "HISI0213") // _HID: Hardware ID
+ Name (_UID, 0x11) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // L3T address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x400090190000, // Min Base Address
+ 0x40009019FFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB71")
+ {
+ 833,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x07},
+ Package () {"hisilicon,ccl-id", 0x01},
+ }
+ })
+
+ }
+
+ // L3T2 for S1_TB(DieID:7)
+ Device (L312) {
+ Name (_HID, "HISI0213") // _HID: Hardware ID
+ Name (_UID, 0x12) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // L3T address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x4000901A0000, // Min Base Address
+ 0x4000901AFFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB72")
+ {
+ 834,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x07},
+ Package () {"hisilicon,ccl-id", 0x02},
+ }
+ })
+
+ }
+
+ // L3T3 for S1_TB(DieID:7)
+ Device (L313) {
+ Name (_HID, "HISI0213") // _HID: Hardware ID
+ Name (_UID, 0x13) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // L3T address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x4000901B0000, // Min Base Address
+ 0x4000901BFFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB73")
+ {
+ 835,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x07},
+ Package () {"hisilicon,ccl-id", 0x03},
+ }
+ })
+
+ }
+ // L3T4 for S1_TB(DieID:7)
+ Device (L314) {
+ Name (_HID, "HISI0213") // _HID: Hardware ID
+ Name (_UID, 0x14) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // L3T address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x4000901C0000, // Min Base Address
+ 0x4000901CFFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB74")
+ {
+ 836,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x07},
+ Package () {"hisilicon,ccl-id", 0x04},
+ }
+ })
+
+ }
+ // L3T5 for S1_TB(DieID:7)
+ Device (L315) {
+ Name (_HID, "HISI0213") // _HID: Hardware ID
+ Name (_UID, 0x15) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // L3T address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x4000901D0000, // Min Base Address
+ 0x4000901DFFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB75")
+ {
+ 837,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x07},
+ Package () {"hisilicon,ccl-id", 0x05},
+ }
+ })
+
+ }
+
+ // DDRC0 for S1_TB(DieID:7)
+ Device (DDR8) {
+ Name (_HID, "HISI0233") // _HID: Hardware ID
+ Name (_UID, 8) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // DDRC address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x400094D20000, // Min Base Address
+ 0x400094D2FFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB78")
+ {
+ 844,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x07},
+ Package () {"hisilicon,ch-id", 0x0},
+ }
+ })
+
+ }
+ // DDRC1 for S1_TB(DieID:7)
+ Device (DDR9) {
+ Name (_HID, "HISI0233") // _HID: Hardware ID
+ Name (_UID, 9) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // DDRC address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x400094D30000, // Min Base Address
+ 0x400094D3FFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB79")
+ {
+ 845,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x07},
+ Package () {"hisilicon,ch-id", 0x1},
+ }
+ })
+
+ }
+ // DDRC2 for S1_TB(DieID:7)
+ Device (DDRA) {
+ Name (_HID, "HISI0233") // _HID: Hardware ID
+ Name (_UID, 0xA) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // DDRC address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x400094D40000, // Min Base Address
+ 0x400094D4FFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB7A")
+ {
+ 846,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x07},
+ Package () {"hisilicon,ch-id", 0x2},
+ }
+ })
+
+ }
+ // DDRC3 for S1_TB(DieID:7)
+ Device (DDRB) {
+ Name (_HID, "HISI0233") // _HID: Hardware ID
+ Name (_UID, 0xB) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // DDRC address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x400094D50000, // Min Base Address
+ 0x400094D5FFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB7B")
+ {
+ 847,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x07},
+ Package () {"hisilicon,ch-id", 0x3},
+ }
+ })
+
+ }
+
+ // HHA0 for S1_TB(DieID:7)
+ Device (HHA4) {
+ Name (_HID, "HISI0243") // _HID: Hardware ID
+ Name (_UID, 4) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // HHA address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x400090120000, // Min Base Address
+ 0x40009012FFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB7C")
+ {
+ 848,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x07}
+ }
+ })
+ }
+
+ // HHA1 for S1_TB(DieID:7)
+ Device (HHA5) {
+ Name (_HID, "HISI0243") // _HID: Hardware ID
+ Name (_UID, 5) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // HHA address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x400090130000, // Min Base Address
+ 0x40009013FFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB7D")
+ {
+ 849,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x07}
+ }
+ })
+ }
+
+ // L3T0 for S1_TA(DieID:5)
+ Device (L318) {
+ Name (_HID, "HISI0213") // _HID: Hardware ID
+ Name (_UID, 0x18) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // L3T address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x400098180000, // Min Base Address
+ 0x40009818FFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB50")
+ {
+ 832,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x05},
+ Package () {"hisilicon,ccl-id", 0x00},
+ }
+ })
+
+ }
+ // L3T1 for S1_TA(DieID:5)
+ Device (L319) {
+ Name (_HID, "HISI0213") // _HID: Hardware ID
+ Name (_UID, 0x19) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // L3T address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x400098190000, // Min Base Address
+ 0x40009819FFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB51")
+ {
+ 833,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x05},
+ Package () {"hisilicon,ccl-id", 0x01},
+ }
+ })
+
+ }
+
+ // L3T2 for S1_TA(DieID:5)
+ Device (L31A) {
+ Name (_HID, "HISI0213") // _HID: Hardware ID
+ Name (_UID, 0x1A) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // L3T address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x4000981A0000, // Min Base Address
+ 0x4000981AFFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB52")
+ {
+ 834,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x05},
+ Package () {"hisilicon,ccl-id", 0x02},
+ }
+ })
+
+ }
+
+ // L3T3 for S1_TA(DieID:5)
+ Device (L31B) {
+ Name (_HID, "HISI0213") // _HID: Hardware ID
+ Name (_UID, 0x1B) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // L3T address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x4000981B0000, // Min Base Address
+ 0x4000981BFFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB53")
+ {
+ 835,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x05},
+ Package () {"hisilicon,ccl-id", 0x03},
+ }
+ })
+
+ }
+ // L3T4 for S1_TA(DieID:5)
+ Device (L31C) {
+ Name (_HID, "HISI0213") // _HID: Hardware ID
+ Name (_UID, 0x1C) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // L3T address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x4000981C0000, // Min Base Address
+ 0x4000981CFFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB54")
+ {
+ 836,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x05},
+ Package () {"hisilicon,ccl-id", 0x04},
+ }
+ })
+
+ }
+ // L3T5 for S1_TA(DieID:5)
+ Device (L31D) {
+ Name (_HID, "HISI0213") // _HID: Hardware ID
+ Name (_UID, 0x1D) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // L3T address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x4000981D0000, // Min Base Address
+ 0x4000981DFFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB55")
+ {
+ 837,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x05},
+ Package () {"hisilicon,ccl-id", 0x05},
+ }
+ })
+
+ }
+
+ // DDRC0 for S1_TA(DieID:5)
+ Device (DDRC) {
+ Name (_HID, "HISI0233") // _HID: Hardware ID
+ Name (_UID, 0xC) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // L3T address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x40009CD20000, // Min Base Address
+ 0x40009CD2FFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB58")
+ {
+ 844,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x05},
+ Package () {"hisilicon,ch-id", 0x0},
+ }
+ })
+
+ }
+ // DDRC1 for S1_TA(DieID:5)
+ Device (DDRD) {
+ Name (_HID, "HISI0233") // _HID: Hardware ID
+ Name (_UID, 0xD) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // L3T address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x40009CD30000, // Min Base Address
+ 0x40009CD3FFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB59")
+ {
+ 845,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x05},
+ Package () {"hisilicon,ch-id", 0x1},
+ }
+ })
+
+ }
+ // DDRC2 for S1_TA(DieID:5)
+ Device (DDRE) {
+ Name (_HID, "HISI0233") // _HID: Hardware ID
+ Name (_UID, 0xE) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // L3T address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x40009CD40000, // Min Base Address
+ 0x40009CD4FFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB5A")
+ {
+ 846,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x05},
+ Package () {"hisilicon,ch-id", 0x2},
+ }
+ })
+
+ }
+ // DDRC3 for S1_TA(DieID:5)
+ Device (DDRF) {
+ Name (_HID, "HISI0233") // _HID: Hardware ID
+ Name (_UID, 0xF) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // L3T address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x40009CD50000, // Min Base Address
+ 0x40009CD5FFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB5B")
+ {
+ 847,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x05},
+ Package () {"hisilicon,ch-id", 0x3},
+ }
+ })
+ }
+
+ // HHA0 for S1_TA(DieID:5)
+ Device (HHA6) {
+ Name (_HID, "HISI0243") // _HID: Hardware ID
+ Name (_UID, 6) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // HHA address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x400098120000, // Min Base Address
+ 0x40009812FFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB5C")
+ {
+ 848,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x05}
+ }
+ })
+ }
+ // HHA1 for S0_TA(DieID:5)
+ Device (HHA7) {
+ Name (_HID, "HISI0243") // _HID: Hardware ID
+ Name (_UID, 7) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // HHA address base
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x400098130000, // Min Base Address
+ 0x40009813FFFF, // Max Base Address
+ 0x0, // Translate
+ 0x10000 // Length
+ )
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB5D")
+ {
+ 849,
+ }
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"hisilicon,scl-id", 0x05}
+ }
+ })
+ }
+}
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/ipmi.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/ipmi.asl
new file mode 100644
index 0000000000..555fe39936
--- /dev/null
+++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/ipmi.asl
@@ -0,0 +1,49 @@
+/** @file
+*
+* Copyright (c) 2018 Hisilicon Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+//
+// LPC
+//
+
+Scope(_SB) {
+ Device (IPI0) {
+ Name (_HID, "IPI0001")
+ Name (_UID, 0)
+ Name (_STR, Unicode("IPMI_BT"))
+ Name(_CCA, 1)
+ //Name (_CID, "IPI0001")
+ Method (_IFT) {
+ Return (0x03)
+ }
+ Method (_SRV) {
+ Return (0x0200) // IPMI Spec Revision 2.0
+ }
+ Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+ QWordMemory ( // BMC memory region
+ ResourceConsumer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x0, // Granularity
+ 0x3f00000e4, // Min Base Address
+ 0x3f00000e7, // Max Base Address
+ 0x0, // Translate
+ 0x4 // Length
+ )
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 484 }
+ })
+ }
+}
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Facs.aslc b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Facs.aslc
new file mode 100644
index 0000000000..9e57936b85
--- /dev/null
+++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Facs.aslc
@@ -0,0 +1,67 @@
+/** @file
+* Firmware ACPI Control Structure (FACS)
+*
+* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
+* Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+#include <IndustryStandard/Acpi.h>
+
+EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = {
+ EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, // UINT32 Signature
+ sizeof (EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE), // UINT32 Length
+ 0xA152, // UINT32 HardwareSignature
+ 0, // UINT32 FirmwareWakingVector
+ 0, // UINT32 GlobalLock
+ 0, // UINT32 Flags
+ 0, // UINT64 XFirmwareWakingVector
+ EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION, // UINT8 Version;
+ { EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[0]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[1]
+ EFI_ACPI_RESERVED_BYTE }, // UINT8 Reserved0[2]
+ 0, // UINT32 OspmFlags "Platform firmware must
+ // initialize this field to zero."
+ { EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[0]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[1]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[2]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[3]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[4]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[5]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[6]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[7]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[8]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[9]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[10]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[11]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[12]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[13]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[14]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[15]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[16]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[17]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[18]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[19]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[20]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[21]
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1[22]
+ EFI_ACPI_RESERVED_BYTE }, // UINT8 Reserved1[23]
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Facs;
+
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Fadt.aslc b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Fadt.aslc
new file mode 100644
index 0000000000..e7ee6981ec
--- /dev/null
+++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Fadt.aslc
@@ -0,0 +1,91 @@
+/** @file
+* Fixed ACPI Description Table (FADT)
+*
+* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
+* Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+#include "Hi1620Platform.h"
+
+#include <Library/AcpiLib.h>
+#include <IndustryStandard/Acpi.h>
+
+EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE,
+ EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
+ ),
+ 0, // UINT32 FirmwareCtrl
+ 0, // UINT32 Dsdt
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0
+ EFI_ACPI_6_2_PM_PROFILE_UNSPECIFIED, // UINT8 PreferredPmProfile
+ 0, // UINT16 SciInt
+ 0, // UINT32 SmiCmd
+ 0, // UINT8 AcpiEnable
+ 0, // UINT8 AcpiDisable
+ 0, // UINT8 S4BiosReq
+ 0, // UINT8 PstateCnt
+ 0, // UINT32 Pm1aEvtBlk
+ 0, // UINT32 Pm1bEvtBlk
+ 0, // UINT32 Pm1aCntBlk
+ 0, // UINT32 Pm1bCntBlk
+ 0, // UINT32 Pm2CntBlk
+ 0, // UINT32 PmTmrBlk
+ 0, // UINT32 Gpe0Blk
+ 0, // UINT32 Gpe1Blk
+ 0, // UINT8 Pm1EvtLen
+ 0, // UINT8 Pm1CntLen
+ 0, // UINT8 Pm2CntLen
+ 0, // UINT8 PmTmrLen
+ 0, // UINT8 Gpe0BlkLen
+ 0, // UINT8 Gpe1BlkLen
+ 0, // UINT8 Gpe1Base
+ 0, // UINT8 CstCnt
+ 0, // UINT16 PLvl2Lat
+ 0, // UINT16 PLvl3Lat
+ 0, // UINT16 FlushSize
+ 0, // UINT16 FlushStride
+ 0, // UINT8 DutyOffset
+ 0, // UINT8 DutyWidth
+ 0, // UINT8 DayAlrm
+ 0, // UINT8 MonAlrm
+ 0, // UINT8 Century
+ 0, // UINT16 IaPcBootArch
+ 0, // UINT8 Reserved1
+ EFI_ACPI_6_2_HW_REDUCED_ACPI | EFI_ACPI_6_2_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags
+ NULL_GAS, // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ResetReg
+ 0, // UINT8 ResetValue
+ EFI_ACPI_6_2_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags
+ EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision
+ 0, // UINT64 XFirmwareCtrl
+ 0, // UINT64 XDsdt
+ NULL_GAS, // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk
+ NULL_GAS, // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk
+ NULL_GAS, // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk
+ NULL_GAS, // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk
+ NULL_GAS, // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk
+ NULL_GAS, // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk
+ NULL_GAS, // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XGpe0Blk
+ NULL_GAS, // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XGpe1Blk
+ NULL_GAS, // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE SleepControlReg
+ NULL_GAS // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE SleepStatusReg
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Fadt;
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Gtdt.aslc b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Gtdt.aslc
new file mode 100644
index 0000000000..45f5d20704
--- /dev/null
+++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Gtdt.aslc
@@ -0,0 +1,86 @@
+/** @file
+* Generic Timer Description Table (GTDT)
+*
+* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
+* Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+#include "Hi1620Platform.h"
+
+#include <Library/AcpiLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+
+#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_6_2_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
+#define GTDT_TIMER_LEVEL_TRIGGERED 0
+#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_6_2_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
+#define GTDT_TIMER_ACTIVE_HIGH 0
+#define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF
+
+#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED)
+
+#pragma pack (1)
+
+typedef struct {
+ EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt;
+ EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[HI1620_WATCHDOG_COUNT];
+} EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLES;
+
+#pragma pack ()
+
+EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = {
+ {
+ ARM_ACPI_HEADER(
+ EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE,
+ EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION
+ ),
+ SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress
+ 0, // UINT32 Reserved
+ FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags
+ FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags
+ FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags
+ FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags
+ 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress
+#ifdef notyet
+ PV660_WATCHDOG_COUNT, // UINT32 PlatformTimerCount
+ sizeof (EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset
+ },
+ {
+ {
+ EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG, sizeof(EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE),
+ EFI_ACPI_RESERVED_BYTE, 0, 0, 0, 0
+ },
+ {
+ EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG, sizeof(EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE),
+ EFI_ACPI_RESERVED_BYTE, 0, 0, 0, 0
+ }
+ }
+#else /* !notyet */
+ 0, 0
+ }
+#endif
+ };
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Gtdt;
+
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Dbg2.aslc b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Dbg2.aslc
new file mode 100644
index 0000000000..342ec33629
--- /dev/null
+++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Dbg2.aslc
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ * Copyright (c) 2018 Hisilicon Limited
+ *
+ * All rights reserved. This program and the accompanying materials
+ * are made available under the terms of the BSD License which accompanies
+ * this distribution, and is available at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+*/
+
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/DebugPort2Table.h>
+#include <Library/AcpiLib.h>
+#include <Library/PcdLib.h>
+#include "Hi1620Platform.h"
+
+#define NUMBER_DEBUG_DEVICE_INFO 1
+#define NUMBER_OF_GENERIC_ADDRESS 1
+#define NAMESPACE_STRING_SIZE 8
+#define UART_LENGTH 0x1000
+
+#pragma pack(1)
+
+typedef struct {
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT DdiHeader;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE Address[NUMBER_OF_GENERIC_ADDRESS];
+ UINT32 AddressSize[NUMBER_OF_GENERIC_ADDRESS];
+ CHAR8 NamespaceString[NAMESPACE_STRING_SIZE];
+} EFI_ACPI_DBG2_DDI_STRUCT;
+
+typedef struct {
+ EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Desc;
+ EFI_ACPI_DBG2_DDI_STRUCT Ddi[NUMBER_DEBUG_DEVICE_INFO];
+} EFI_ACPI_DEBUG_PORT_2_TABLE;
+
+#pragma pack()
+
+EFI_ACPI_DEBUG_PORT_2_TABLE Dbg2 = {
+ {
+ ARM_ACPI_HEADER(
+ EFI_ACPI_6_1_DEBUG_PORT_2_TABLE_SIGNATURE,
+ EFI_ACPI_DEBUG_PORT_2_TABLE,
+ EFI_ACPI_DEBUG_PORT_2_TABLE_REVISION
+ ),
+ OFFSET_OF(EFI_ACPI_DEBUG_PORT_2_TABLE, Ddi),
+ NUMBER_DEBUG_DEVICE_INFO
+ },
+ {
+ {
+ {
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION,
+ sizeof(EFI_ACPI_DBG2_DDI_STRUCT),
+ NUMBER_OF_GENERIC_ADDRESS,
+ NAMESPACE_STRING_SIZE,
+ OFFSET_OF(EFI_ACPI_DBG2_DDI_STRUCT, NamespaceString),
+ 0, //OemDataLength
+ 0, //OemDataOffset
+ EFI_ACPI_DBG2_PORT_TYPE_SERIAL,
+ EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_PL011_UART,
+ {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE},
+ OFFSET_OF(EFI_ACPI_DBG2_DDI_STRUCT, Address),
+ OFFSET_OF(EFI_ACPI_DBG2_DDI_STRUCT, AddressSize),
+ },
+ {
+ {
+ EFI_ACPI_6_1_SYSTEM_MEMORY,
+ 32,
+ 0,
+ EFI_ACPI_6_1_BYTE,
+ FixedPcdGet64 (PcdSerialDbgRegisterBase)
+ }
+ },
+ {
+ UART_LENGTH
+ },
+ "COM1"
+ }
+ }
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Dbg2;
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Iort.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Iort.asl
new file mode 100644
index 0000000000..33b5d5250b
--- /dev/null
+++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Iort.asl
@@ -0,0 +1,1989 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20151124-64
+ * Copyright (c) 2000 - 2015 Intel Corporation
+ *
+ * Template for [IORT] ACPI Table (static data table)
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+[0004] Signature : "IORT" [IO Remapping Table]
+[0004] Table Length : 01c8
+[0001] Revision : 00
+[0001] Checksum : BC
+[0006] Oem ID : "HISI " // ?
+[0008] Oem Table ID : "HIP08 " // ?
+[0004] Oem Revision : 00000000 // ?
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20150410
+
+[0004] Node Count : 00000005 // ITS, SMMU and RC
+[0004] Node Offset : 00000034 // ?
+[0004] Reserved : 00000000
+[0004] Optional Padding : 00 00 00 00
+
+/* 0x34 ITS, for PCIe */
+/* Here we use the P680/Hi1620 ACPI table which includes MADT table to help to debuge */
+[0001] Type : 00
+[0002] Length : 0018
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000000 // ?
+[0004] Mapping Offset : 00000000 // ?
+
+[0004] ItsCount : 00000001 // ?
+[0004] Identifiers : 00000000 // how to refer to MADT ?
+
+/* 0x4c SMMU for PCIe host bridge 0 and 1 */
+[0001] Type : 04
+[0002] Length : 0080
+[0001] Revision : 01
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000003
+[0004] Mapping Offset : 00000044
+
+[0008] Base Address : 148000000
+[0004] Flags (decoded below) : 00000009
+ COHACC Override : 1
+ HTTU Override : 0
+ Proximity Domain Valid : 1
+[0004] Reserved : 00000000
+[0008] VATOS Address : 0
+[0004] Model : 00000000
+[0004] Event Interrupt : 00000000
+[0004] PRI Interrupt : 00000000
+[0004] GERR Interrupt : 00000000
+[0004] Sync Interrupt : 00000000
+[0001] Proximity Domain : 01
+[0001] Reserved : 00
+[0002] Reserved : 0000
+[0004] DeviceID mapping index : 00000002
+
+[0004] Input base : 00000000
+[0004] ID Count : 00004000
+[0004] Output Base : 00000000
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 1
+
+[0004] Input base : 00007b00
+[0004] ID Count : 00000100
+[0004] Output Base : 00007b00
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 1
+
+[0004] Input base : 00000000 //single mapping will ignore input base
+[0004] ID Count : 00000001
+[0004] Output Base : 00007F01
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* 0xCC SMMU for PCIe host bridge 4 */
+[0001] Type : 04
+[0002] Length : 006C
+[0001] Revision : 01
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000044
+
+[0008] Base Address : 100000000
+[0004] Flags (decoded below) : 00000009
+ COHACC Override : 1
+ HTTU Override : 0
+ Proximity Domain Valid : 1
+[0004] Reserved : 00000000
+[0008] VATOS Address : 0
+[0004] Model : 00000000
+[0004] Event Interrupt : 00000000
+[0004] PRI Interrupt : 00000000
+[0004] GERR Interrupt : 00000000
+[0004] Sync Interrupt : 00000000
+[0001] Proximity Domain : 01
+[0001] Reserved : 00
+[0002] Reserved : 0000
+[0004] DeviceID mapping index : 0001
+
+[0004] Input base : 00007c00
+[0004] ID Count : 00000200
+[0004] Output Base : 00007c00
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 1
+
+[0004] Input base : 00000000 //single mapping will ignore input base
+[0004] ID Count : 00000001
+[0004] Output Base : 00007F03
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* 0x138 */
+/* SMMU for PCIe host bridge 5 */
+[0001] Type : 04
+[0002] Length : 006C
+[0001] Revision : 01
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000044
+
+[0008] Base Address : 140000000
+[0004] Flags (decoded below) : 00000009
+ COHACC Override : 1
+ HTTU Override : 0
+ Proximity Domain Valid : 1
+[0004] Reserved : 00000000
+[0008] VATOS Address : 0
+[0004] Model : 00000000
+[0004] Event Interrupt : 00000000
+[0004] PRI Interrupt : 00000000
+[0004] GERR Interrupt : 00000000
+[0004] Sync Interrupt : 00000000
+[0001] Proximity Domain : 01
+[0001] Reserved : 00
+[0002] Reserved : 0000
+[0004] DeviceID mapping index : 00000001
+
+[0004] Input base : 00007400
+[0004] ID Count : 00000300
+[0004] Output Base : 00007400
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 1
+
+[0004] Input base : 00000000 //single mapping will ignore input base
+[0004] ID Count : 00000001
+[0004] Output Base : 00007F04
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+// Here for Chip1 SMMU settings
+/* 0x1A4 SMMU for PCIe host bridge 6 and 7 */
+[0001] Type : 04
+[0002] Length : 0080
+[0001] Revision : 01
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000003
+[0004] Mapping Offset : 00000044
+
+[0008] Base Address : 400148000000
+[0004] Flags (decoded below) : 00000009
+ COHACC Override : 1
+ HTTU Override : 0
+ Proximity Domain Valid : 1
+[0004] Reserved : 00000000
+[0008] VATOS Address : 0
+[0004] Model : 00000000
+[0004] Event Interrupt : 00000000
+[0004] PRI Interrupt : 00000000
+[0004] GERR Interrupt : 00000000
+[0004] Sync Interrupt : 00000000
+[0001] Proximity Domain : 03
+[0001] Reserved : 00
+[0002] Reserved : 0000
+[0004] DeviceID mapping index : 00000002
+
+[0004] Input base : 00008000
+[0004] ID Count : 00002000
+[0004] Output Base : 00008000
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 1
+
+[0004] Input base : 0000bb00
+[0004] ID Count : 00000100
+[0004] Output Base : 0000bb00
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 1
+
+[0004] Input base : 00000000 //single mapping will ignore input base
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BF01
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* 0x224 SMMU for PCIe host bridge 10 */
+[0001] Type : 04
+[0002] Length : 006C
+[0001] Revision : 01
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000044
+
+[0008] Base Address : 400100000000
+[0004] Flags (decoded below) : 00000009
+ COHACC Override : 1
+ HTTU Override : 0
+ Proximity Domain Valid : 1
+[0004] Reserved : 00000000
+[0008] VATOS Address : 0
+[0004] Model : 00000000
+[0004] Event Interrupt : 00000000
+[0004] PRI Interrupt : 00000000
+[0004] GERR Interrupt : 00000000
+[0004] Sync Interrupt : 00000000
+[0001] Proximity Domain : 03
+[0001] Reserved : 00
+[0002] Reserved : 0000
+[0004] DeviceID mapping index : 0001
+
+[0004] Input base : 0000BC00
+[0004] ID Count : 00000200
+[0004] Output Base : 0000BC00
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 1
+
+[0004] Input base : 00000000 //single mapping will ignore input base
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BF03
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* 0x290*/
+/* SMMU for PCIe host bridge 11 */
+[0001] Type : 04
+[0002] Length : 006C
+[0001] Revision : 01
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000044
+
+[0008] Base Address : 400140000000
+[0004] Flags (decoded below) : 00000009
+ COHACC Override : 1
+ HTTU Override : 0
+ Proximity Domain Valid : 1
+[0004] Reserved : 00000000
+[0008] VATOS Address : 0
+[0004] Model : 00000000
+[0004] Event Interrupt : 00000000
+[0004] PRI Interrupt : 00000000
+[0004] GERR Interrupt : 00000000
+[0004] Sync Interrupt : 00000000
+[0001] Proximity Domain : 03
+[0001] Reserved : 00
+[0002] Reserved : 0000
+[0004] DeviceID mapping index : 00000001
+
+[0004] Input base : 0000B400
+[0004] ID Count : 00000300
+[0004] Output Base : 0000B400
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 1
+
+[0004] Input base : 00000000 //single mapping will ignore input base
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BF04
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/*0x2FC RC 0 */
+[0001] Type : 02
+[0002] Length : 00A0
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 0000000C
+[0004] Mapping Offset : 00000028
+
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000001
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0004] ATS Attribute : 00000000
+[0004] PCI Segment Number : 00000000 // should match with above MCFG
+
+/* BDF of pcie host 0 -> stream ID of pcie 0/1 SMMU */
+[0004] Input base : 00000000
+[0004] ID Count : 00004000 // the number of IDs in range
+[0004] Output Base : 00000000
+[0004] Output Reference : 0000004c
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 1
+
+/* BDF of pcie host 1 -> stream ID of pcie 0/1 SMMU */
+[0004] Input base : 00007b00
+[0004] ID Count : 00000100 // the number of IDs in range
+[0004] Output Base : 00007b00
+[0004] Output Reference : 0000004c
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 1
+
+/* host2 and host3 should no open smmu for chips smmu bug *
+/* BDF of pcie host 2 -> stream ID of pcie 0/1 ITS */
+[0004] Input base : 00007a00
+[0004] ID Count : 00000100 // the number of IDs in range
+[0004] Output Base : 00007a00
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 1
+
+/* BDF of pcie host 3 -> stream ID of pcie 0/1 ITS */
+[0004] Input base : 00007800
+[0004] ID Count : 00000200 // the number of IDs in range
+[0004] Output Base : 00007800
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 1
+
+/* BDF of pcie host 4 -> stream ID of pcie 4 SMMU */
+[0004] Input base : 00007c00
+[0004] ID Count : 00000200 // the number of IDs in range
+[0004] Output Base : 00007c00
+[0004] Output Reference : 000000cc
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 1
+
+/* BDF of pcie host 5 -> stream ID of pcie 5 SMMU */
+[0004] Input base : 00007400
+[0004] ID Count : 00000300 // the number of IDs in range
+[0004] Output Base : 00007400
+[0004] Output Reference : 00000138
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 1
+
+/* BDF of pcie host 6 -> stream ID of pcie 6/7 SMMU */
+[0004] Input base : 00008000
+[0004] ID Count : 00002000 // the number of IDs in range
+[0004] Output Base : 00008000
+[0004] Output Reference : 000001A4
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 1
+
+/* BDF of pcie host 7 -> stream ID of pcie 6/7 SMMU */
+[0004] Input base : 0000BB00
+[0004] ID Count : 00000100 // the number of IDs in range
+[0004] Output Base : 0000BB00
+[0004] Output Reference : 000001A4
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 1
+
+/* host8 and host9 should no open smmu for chips smmu bug *
+/* BDF of pcie host 8 -> stream ID of pcie ITS */
+[0004] Input base : 0000BA00
+[0004] ID Count : 00000100 // the number of IDs in range
+[0004] Output Base : 0000BA00
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 1
+
+/* BDF of pcie host 9 -> stream ID of pcie 0/1 ITS */
+[0004] Input base : 0000B800
+[0004] ID Count : 00000200 // the number of IDs in range
+[0004] Output Base : 0000B800
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 1
+
+/* BDF of pcie host 10 -> stream ID of pcie 10 SMMU */
+[0004] Input base : 0000BC00
+[0004] ID Count : 00000200 // the number of IDs in range
+[0004] Output Base : 0000BC00
+[0004] Output Reference : 00000224
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 1
+
+/* BDF of pcie host 11 -> stream ID of pcie 11 SMMU */
+[0004] Input base : 0000B400
+[0004] ID Count : 00000300 // the number of IDs in range
+[0004] Output Base : 0000B400
+[0004] Output Reference : 00000290
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 1
+
+/* mbi-gen for S0-TB-L3T0, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB30"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007FD1 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TB-L3T1, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB31"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007FD2 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TB-L3T2, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB32"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007FD3 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TB-L3T3, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB33"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007FD4 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TB-L3T4, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB34"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007FD5 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TB-L3T5, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB35"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007FD6 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TB-DDRC0, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB38"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007FDD // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TB-DDRC1, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB39"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007FDE // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TB-DDRC2, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB3A"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007FDF // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TB-DDRC3, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB3B"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007FC7 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TB-HHA0, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB3C"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007FC8 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TB-HHA1, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB3D"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007FC9 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TA-L3T0, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB10"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007F51 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TA-L3T1, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB11"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007F52 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TA-L3T2, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB12"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007F53 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TA-L3T3, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB13"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007F54 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TA-L3T4, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB14"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007F55 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TA-L3T5, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB15"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007F56 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TA-DDRC0, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB18"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007F5D // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TA-DDRC1, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB19"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007F5E // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TA-DDRC2, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB1A"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007F5F // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TA-DDRC3, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB1B"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007F47 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TA-HHA0, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB1C"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007F48 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TA-HHA1, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB1D"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007F49 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TB-L3T0, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB70"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BFD1 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TB-L3T1, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB71"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BFD2 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TB-L3T2, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB72"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BFD3 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TB-L3T3, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB73"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BFD4 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TB-L3T4, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB74"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BFD5 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TB-L3T5, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB75"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BFD6 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TB-DDRC0, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB78"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BFDD // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TB-DDRC1, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB79"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BFDE // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TB-DDRC2, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB7A"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BFDF // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TB-DDRC3, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB7B"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BFC7 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TB-HHA0, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB7C"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BFC8 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TB-HHA1, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB7D"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BFC9 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TA-L3T0, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB50"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BF51 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TA-L3T1, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB51"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BF52 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TA-L3T2, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB52"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BF53 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TA-L3T3, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB53"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BF54 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TA-L3T4, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB54"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BF55 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TA-L3T5, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB55"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BF56 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TA-DDRC0, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB58"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BF5D // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TA-DDRC1, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB59"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BF5E // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TA-DDRC2, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB5A"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BF5F // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TA-DDRC3, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB5B"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BF47 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TA-HHA0, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB5C"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BF48 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TA-HHA1, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB5D"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BF49 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+
+[320h 0800 1] Type : 01
+[321h 0801 2] Length : 0054
+[323h 0803 1] Revision : 00
+[324h 0804 4] Reserved : 00000000
+[328h 0808 4] Mapping Count : 00000001
+[32Ch 0812 4] Mapping Offset : 00000040
+
+[330h 0816 4] Node Flags : 00000000
+[334h 0820 8] Memory Properties : [IORT Memory Access Properties]
+[334h 0820 4] Cache Coherency : 00000000
+[338h 0824 1] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[339h 0825 2] Reserved : 0000
+[33Bh 0827 1] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[33Ch 0828 1] Memory Size Limit : 00
+[33Dh 0829 11] Device Name : "\_SB_.SEC0"
+[348h 0840 24] Padding : \
+ 00 00 00 00 00 00 00 00 01 00 00 00 80 00 04 00 \
+ 4C 00 00 00 01 00 00 00
+
+[34Ch 0844 4] Input base : 00000000
+[350h 0848 4] ID Count : 00000001
+[354h 0852 4] Output Base : 00000100
+[358h 0856 4] Output Reference : 00000100
+[35Ch 0860 4] Flags (decoded below) : 00000001
+ Single Mapping : 1
+/* RDE device report++.*/
+[320h 0800 1] Type : 01
+[321h 0801 2] Length : 0054
+[323h 0803 1] Revision : 00
+[324h 0804 4] Reserved : 00000000
+[328h 0808 4] Mapping Count : 00000001
+[32Ch 0812 4] Mapping Offset : 00000040
+
+[330h 0816 4] Node Flags : 00000000
+[334h 0820 8] Memory Properties : [IORT Memory Access Properties]
+[334h 0820 4] Cache Coherency : 00000000
+[338h 0824 1] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[339h 0825 2] Reserved : 0000
+[33Bh 0827 1] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[33Ch 0828 1] Memory Size Limit : 00
+[33Dh 0829 11] Device Name : "\_SB_.RDE0"
+[348h 0840 24] Padding : \
+ 00 00 00 00 00 00 00 00 01 00 00 00 80 00 04 00 \
+ 4C 00 00 00 01 00 00 00
+
+[34Ch 0844 4] Input base : 00000000
+[350h 0848 4] ID Count : 00000001
+[354h 0852 4] Output Base : 00007f13
+[358h 0856 4] Output Reference : 00000034
+[35Ch 0860 4] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for MCTP, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MBI4"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007F18 // MCTP device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620IortNoSmmu.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620IortNoSmmu.asl
new file mode 100644
index 0000000000..63d11b83eb
--- /dev/null
+++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620IortNoSmmu.asl
@@ -0,0 +1,1736 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20151124-64
+ * Copyright (c) 2000 - 2015 Intel Corporation
+ *
+ * Template for [IORT] ACPI Table (static data table)
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+[0004] Signature : "IORT" [IO Remapping Table]
+[0004] Table Length : 01c8
+[0001] Revision : 00
+[0001] Checksum : BC
+[0006] Oem ID : "HISI " // ?
+[0008] Oem Table ID : "HIP08 " // ?
+[0004] Oem Revision : 00000000 // ?
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20150410
+
+[0004] Node Count : 00000005 // ITS, SMMU and RC
+[0004] Node Offset : 00000034 // ?
+[0004] Reserved : 00000000
+[0004] Optional Padding : 00 00 00 00
+
+/* 0x34 ITS, for PCIe */
+/* Here we use the P680/Hi1620 ACPI table which includes MADT table to help to debuge */
+[0001] Type : 00
+[0002] Length : 0018
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000000 // ?
+[0004] Mapping Offset : 00000000 // ?
+
+[0004] ItsCount : 00000001 // ?
+[0004] Identifiers : 00000000 // how to refer to MADT ?
+
+/*0x4c RC 0 */
+[0001] Type : 02
+[0002] Length : 00A0
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 0000000C
+[0004] Mapping Offset : 00000028
+
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000001
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0004] ATS Attribute : 00000000
+[0004] PCI Segment Number : 00000000 // should match with above MCFG
+
+/* BDF of pcie host 0 -> stream ID of pcie 0/1 SMMU */
+[0004] Input base : 00000000
+[0004] ID Count : 00004000 // the number of IDs in range
+[0004] Output Base : 00000000
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 0
+
+/* BDF of pcie host 1 -> stream ID of pcie 0/1 SMMU */
+[0004] Input base : 00007b00
+[0004] ID Count : 00000100 // the number of IDs in range
+[0004] Output Base : 00007b00
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 0
+
+/* BDF of pcie host 2 -> stream ID of pcie 0/1 ITS */
+[0004] Input base : 00007a00
+[0004] ID Count : 00000100 // the number of IDs in range
+[0004] Output Base : 00007a00
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 0
+
+/* BDF of pcie host 3 -> stream ID of pcie 0/1 ITS */
+[0004] Input base : 00007800
+[0004] ID Count : 00000200 // the number of IDs in range
+[0004] Output Base : 00007800
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 0
+
+/* BDF of pcie host 4 -> stream ID of pcie 4 SMMU */
+[0004] Input base : 00007c00
+[0004] ID Count : 00000200 // the number of IDs in range
+[0004] Output Base : 00007c00
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 0
+
+/* BDF of pcie host 5 -> stream ID of pcie 5 SMMU */
+[0004] Input base : 00007400
+[0004] ID Count : 00000300 // the number of IDs in range
+[0004] Output Base : 00007400
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 0
+
+/* BDF of pcie host 6 -> stream ID of pcie 6/7 SMMU */
+[0004] Input base : 00008000
+[0004] ID Count : 00002000 // the number of IDs in range
+[0004] Output Base : 00008000
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 0
+
+/* BDF of pcie host 7 -> stream ID of pcie 6/7 SMMU */
+[0004] Input base : 0000BB00
+[0004] ID Count : 00000100 // the number of IDs in range
+[0004] Output Base : 0000BB00
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 0
+
+/* BDF of pcie host 8 -> stream ID of pcie ITS */
+[0004] Input base : 0000BA00
+[0004] ID Count : 00000100 // the number of IDs in range
+[0004] Output Base : 0000BA00
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 0
+
+/* BDF of pcie host 9 -> stream ID of pcie 0/1 ITS */
+[0004] Input base : 0000B800
+[0004] ID Count : 00000200 // the number of IDs in range
+[0004] Output Base : 0000B800
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 0
+
+/* BDF of pcie host 10 -> stream ID of pcie 10 SMMU */
+[0004] Input base : 0000BC00
+[0004] ID Count : 00000200 // the number of IDs in range
+[0004] Output Base : 0000BC00
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 0
+
+/* BDF of pcie host 11 -> stream ID of pcie 11 SMMU */
+[0004] Input base : 0000B400
+[0004] ID Count : 00000300 // the number of IDs in range
+[0004] Output Base : 0000B400
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 0
+
+/* mbi-gen for S0-TB-L3T0, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB30"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007FD1 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TB-L3T1, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB31"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007FD2 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TB-L3T2, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB32"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007FD3 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TB-L3T3, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB33"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007FD4 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TB-L3T4, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB34"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007FD5 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TB-L3T5, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB35"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007FD6 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TB-DDRC0, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB38"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007FDD // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TB-DDRC1, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB39"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007FDE // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TB-DDRC2, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB3A"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007FDF // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TB-DDRC3, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB3B"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007FC7 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TB-HHA0, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB3C"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007FC8 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TB-HHA1, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB3D"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007FC9 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TA-L3T0, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB10"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007F51 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TA-L3T1, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB11"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007F52 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TA-L3T2, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB12"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007F53 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TA-L3T3, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB13"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007F54 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TA-L3T4, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB14"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007F55 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TA-L3T5, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB15"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007F56 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TA-DDRC0, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB18"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007F5D // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TA-DDRC1, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB19"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007F5E // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TA-DDRC2, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB1A"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007F5F // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TA-DDRC3, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB1B"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007F47 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TA-HHA0, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB1C"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007F48 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S0-TA-HHA1, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB1D"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007F49 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TB-L3T0, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB70"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BFD1 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TB-L3T1, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB71"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BFD2 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TB-L3T2, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB72"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BFD3 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TB-L3T3, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB73"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BFD4 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TB-L3T4, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB74"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BFD5 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TB-L3T5, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB75"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BFD6 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TB-DDRC0, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB78"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BFDD // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TB-DDRC1, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB79"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BFDE // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TB-DDRC2, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB7A"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BFDF // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TB-DDRC3, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB7B"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BFC7 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TB-HHA0, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB7C"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BFC8 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TB-HHA1, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB7D"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BFC9 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TA-L3T0, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB50"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BF51 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TA-L3T1, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB51"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BF52 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TA-L3T2, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB52"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BF53 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TA-L3T3, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB53"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BF54 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TA-L3T4, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB54"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BF55 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TA-L3T5, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB55"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BF56 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TA-DDRC0, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB58"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BF5D // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TA-DDRC1, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB59"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BF5E // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TA-DDRC2, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB5A"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BF5F // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TA-DDRC3, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB5B"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BF47 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TA-HHA0, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB5C"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BF48 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for S1-TA-HHA1, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MB5D"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 0000BF49 // PMU device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+
+[320h 0800 1] Type : 01
+[321h 0801 2] Length : 0054
+[323h 0803 1] Revision : 00
+[324h 0804 4] Reserved : 00000000
+[328h 0808 4] Mapping Count : 00000001
+[32Ch 0812 4] Mapping Offset : 00000040
+
+[330h 0816 4] Node Flags : 00000000
+[334h 0820 8] Memory Properties : [IORT Memory Access Properties]
+[334h 0820 4] Cache Coherency : 00000000
+[338h 0824 1] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[339h 0825 2] Reserved : 0000
+[33Bh 0827 1] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[33Ch 0828 1] Memory Size Limit : 00
+[33Dh 0829 11] Device Name : "\_SB_.SEC0"
+[348h 0840 24] Padding : \
+ 00 00 00 00 00 00 00 00 01 00 00 00 80 00 04 00 \
+ 4C 00 00 00 01 00 00 00
+
+[34Ch 0844 4] Input base : 00000000
+[350h 0848 4] ID Count : 00000001
+[354h 0852 4] Output Base : 00000100
+[358h 0856 4] Output Reference : 00000034
+[35Ch 0860 4] Flags (decoded below) : 00000001
+ Single Mapping : 1
+/* RDE device report++.*/
+[320h 0800 1] Type : 01
+[321h 0801 2] Length : 0054
+[323h 0803 1] Revision : 00
+[324h 0804 4] Reserved : 00000000
+[328h 0808 4] Mapping Count : 00000001
+[32Ch 0812 4] Mapping Offset : 00000040
+
+[330h 0816 4] Node Flags : 00000000
+[334h 0820 8] Memory Properties : [IORT Memory Access Properties]
+[334h 0820 4] Cache Coherency : 00000000
+[338h 0824 1] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[339h 0825 2] Reserved : 0000
+[33Bh 0827 1] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[33Ch 0828 1] Memory Size Limit : 00
+[33Dh 0829 11] Device Name : "\_SB_.RDE0"
+[348h 0840 24] Padding : \
+ 00 00 00 00 00 00 00 00 01 00 00 00 80 00 04 00 \
+ 4C 00 00 00 01 00 00 00
+
+[34Ch 0844 4] Input base : 00000000
+[350h 0848 4] ID Count : 00000001
+[354h 0852 4] Output Base : 00007f13
+[358h 0856 4] Output Reference : 00000034
+[35Ch 0860 4] Flags (decoded below) : 00000001
+ Single Mapping : 1
+
+/* mbi-gen for MCTP, named component */
+[0001] Type : 01
+[0002] Length : 0046
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000032
+
+[0004] Node Flags : 00000000
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000000
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0001] Memory Size Limit : 00
+[0016] Device Name : "\_SB_.MBI4"
+[0004] Padding : 00 00 00 00
+
+[0004] Input base : 00000000
+[0004] ID Count : 00000001
+[0004] Output Base : 00007F18 // MCTP device id
+[0004] Output Reference : 00000034
+[0004] Flags (decoded below) : 00000001
+ Single Mapping : 1
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Mcfg.aslc b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Mcfg.aslc
new file mode 100644
index 0000000000..2d719ef562
--- /dev/null
+++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Mcfg.aslc
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2018 Hisilicon Limited
+ *
+ * All rights reserved. This program and the accompanying materials
+ * are made available under the terms of the BSD License which accompanies
+ * this distribution, and is available at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ */
+
+#include <IndustryStandard/Acpi.h>
+#include "Hi1620Platform.h"
+
+#define MCFG_VERSION 0x1
+
+#pragma pack(1)
+typedef struct
+{
+ UINT64 ullBaseAddress;
+ UINT16 usSegGroupNum;
+ UINT8 ucStartBusNum;
+ UINT8 ucEndBusNum;
+ UINT32 Reserved2;
+}EFI_MCFG_CONFIG_STRUCTURE;
+
+typedef struct
+{
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 Reserved1;
+}EFI_MCFG_TABLE_CONFIG;
+
+typedef struct
+{
+ EFI_MCFG_TABLE_CONFIG Acpi_Table_Mcfg;
+ EFI_MCFG_CONFIG_STRUCTURE Config_Structure;
+}EFI_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE;
+#pragma pack()
+
+EFI_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg=
+{
+ {
+ {
+ EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
+ sizeof (EFI_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE),
+ MCFG_VERSION,
+ 0x00, // Checksum will be updated at runtime
+ {EFI_ACPI_ARM_OEM_ID},
+ EFI_ACPI_ARM_OEM_TABLE_ID,
+ EFI_ACPI_ARM_OEM_REVISION,
+ EFI_ACPI_ARM_CREATOR_ID,
+ EFI_ACPI_ARM_CREATOR_REVISION
+ },
+ 0x0000000000000000, //Reserved
+ },
+ {
+ 0xd0000000, //Base Address
+ 0x0, //Segment Group Number
+ 0x0, //Start Bus Number
+ 0xff, //End Bus Number
+ 0x00000000, //Reserved
+ }
+};
+
+VOID* CONST ReferenceAcpiTable = &Mcfg;
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Slit.aslc b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Slit.aslc
new file mode 100644
index 0000000000..53ae9a9235
--- /dev/null
+++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Slit.aslc
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2013 Linaro Limited
+ *
+ * All rights reserved. This program and the accompanying materials
+ * are made available under the terms of the BSD License which accompanies
+ * this distribution, and is available at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * Yi Li - yi.li@linaro.org
+*/
+
+#include <IndustryStandard/Acpi.h>
+#include "Hi1620Platform.h"
+
+#define EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT 0x0000000000000004
+
+#pragma pack(1)
+typedef struct {
+ UINT8 Entry[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT];
+} EFI_ACPI_6_2_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE;
+
+typedef struct {
+ EFI_ACPI_6_2_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER Header;
+ EFI_ACPI_6_2_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE NumSlit[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT];
+
+} EFI_ACPI_6_2_SYSTEM_LOCALITY_INFORMATION_TABLE;
+#pragma pack()
+
+//
+// System Locality Information Table
+// Please modify all values in Slit.h only.
+//
+EFI_ACPI_6_2_SYSTEM_LOCALITY_INFORMATION_TABLE Slit = {
+ {
+ {
+ EFI_ACPI_6_2_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE,
+ sizeof (EFI_ACPI_6_2_SYSTEM_LOCALITY_INFORMATION_TABLE),
+ EFI_ACPI_6_2_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION,
+ 0x00, // Checksum will be updated at runtime
+ {EFI_ACPI_ARM_OEM_ID},
+ EFI_ACPI_ARM_OEM_TABLE_ID,
+ EFI_ACPI_ARM_OEM_REVISION,
+ EFI_ACPI_ARM_CREATOR_ID,
+ EFI_ACPI_ARM_CREATOR_REVISION,
+ },
+ //
+ // Beginning of SLIT specific fields
+ //
+ EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT,
+ },
+ {
+ {{0x0A, 0x10, 0x20, 0x21}}, //Locality 0
+ {{0x10, 0x0A, 0x19, 0x20}}, //Locality 1
+ {{0x20, 0x19, 0x0A, 0x10}}, //Locality 2
+ {{0x21, 0x20, 0x10, 0x0A}}, //Locality 3
+ },
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Slit;
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Spcr.aslc b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Spcr.aslc
new file mode 100644
index 0000000000..a9768d4ba2
--- /dev/null
+++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Spcr.aslc
@@ -0,0 +1,81 @@
+/** @file
+* Serial Port Console Redirection Table (SPCR)
+*
+* Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016 Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+#include <Library/AcpiLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
+#include "Hi1620Platform.h"
+
+#define SPCR_FLOW_CONTROL_NONE 0
+
+STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = {
+ ARM_ACPI_HEADER (EFI_ACPI_6_2_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE,
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION),
+ // UINT8 InterfaceType;
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART,
+ // UINT8 Reserved1[3];
+ {
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE
+ },
+ // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE BaseAddress;
+ ARM_GAS32 (FixedPcdGet64 (PcdSerialRegisterBase)),
+ // UINT8 InterruptType;
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC,
+ // UINT8 Irq;
+ 0, // Not used on ARM
+ // UINT32 GlobalSystemInterrupt;
+ 141,
+ // UINT8 BaudRate;
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200,
+ // UINT8 Parity;
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY,
+ // UINT8 StopBits;
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1,
+ // UINT8 FlowControl;
+ SPCR_FLOW_CONTROL_NONE,
+ // UINT8 TerminalType;
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI,
+ // UINT8 Reserved2;
+ EFI_ACPI_RESERVED_BYTE,
+ // UINT16 PciDeviceId;
+ 0xFFFF,
+ // UINT16 PciVendorId;
+ 0xFFFF,
+ // UINT8 PciBusNumber;
+ 0x00,
+ // UINT8 PciDeviceNumber;
+ 0x00,
+ // UINT8 PciFunctionNumber;
+ 0x00,
+ // UINT32 PciFlags;
+ 0x00000000,
+ // UINT8 PciSegment;
+ 0x00,
+ // UINT32 Reserved3;
+ EFI_ACPI_RESERVED_DWORD
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Spcr;
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Srat.aslc b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Srat.aslc
new file mode 100644
index 0000000000..aea4c21858
--- /dev/null
+++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Srat.aslc
@@ -0,0 +1,166 @@
+/*
+ * Copyright (c) 2013 Linaro Limited
+ *
+ * All rights reserved. This program and the accompanying materials
+ * are made available under the terms of the BSD License which accompanies
+ * this distribution, and is available at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * Yi Li - yi.li@linaro.org
+ *
+ * Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*/
+
+#include <IndustryStandard/Acpi.h>
+#include "Hi1620Platform.h"
+#include <Library/AcpiLib.h>
+#include <Library/AcpiNextLib.h>
+
+
+//
+// Static Resource Affinity Table definition
+//
+EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE Srat = {
+ {
+ {EFI_ACPI_6_2_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE,
+ sizeof (EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE),
+ EFI_ACPI_6_2_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION,
+ 0x00, // Checksum will be updated at runtime
+ {EFI_ACPI_ARM_OEM_ID},
+ EFI_ACPI_ARM_OEM_TABLE_ID,
+ EFI_ACPI_ARM_OEM_REVISION,
+ EFI_ACPI_ARM_CREATOR_ID,
+ EFI_ACPI_ARM_CREATOR_REVISION},
+ /*Reserved*/
+ 0x00000001, // Reserved to be 1 for backward compatibility
+ EFI_ACPI_RESERVED_QWORD
+ },
+
+ //
+ //
+ // Memory Affinity
+ //
+ {
+ EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
+ EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
+ EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
+ EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
+ EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
+ EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
+ EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
+ EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
+ EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
+ EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
+ },
+
+ {
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000000,0x00000001,0x00000000), //GICC Affinity Processor 0
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000001,0x00000001,0x00000000), //GICC Affinity Processor 1
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000002,0x00000001,0x00000000), //GICC Affinity Processor 2
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000003,0x00000001,0x00000000), //GICC Affinity Processor 3
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000004,0x00000001,0x00000000), //GICC Affinity Processor 4
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000005,0x00000001,0x00000000), //GICC Affinity Processor 5
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000006,0x00000001,0x00000000), //GICC Affinity Processor 6
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000007,0x00000001,0x00000000), //GICC Affinity Processor 7
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000008,0x00000001,0x00000000), //GICC Affinity Processor 8
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000009,0x00000001,0x00000000), //GICC Affinity Processor 9
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000000A,0x00000001,0x00000000), //GICC Affinity Processor 10
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000000B,0x00000001,0x00000000), //GICC Affinity Processor 11
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000000C,0x00000001,0x00000000), //GICC Affinity Processor 12
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000000D,0x00000001,0x00000000), //GICC Affinity Processor 13
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000000E,0x00000001,0x00000000), //GICC Affinity Processor 14
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000000F,0x00000001,0x00000000), //GICC Affinity Processor 15
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000010,0x00000001,0x00000000), //GICC Affinity Processor 16
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000011,0x00000001,0x00000000), //GICC Affinity Processor 17
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000012,0x00000001,0x00000000), //GICC Affinity Processor 18
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000013,0x00000001,0x00000000), //GICC Affinity Processor 19
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000014,0x00000001,0x00000000), //GICC Affinity Processor 20
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000015,0x00000001,0x00000000), //GICC Affinity Processor 21
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000016,0x00000001,0x00000000), //GICC Affinity Processor 22
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000017,0x00000001,0x00000000), //GICC Affinity Processor 23
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000018,0x00000001,0x00000000), //GICC Affinity Processor 24
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000019,0x00000001,0x00000000), //GICC Affinity Processor 25
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000001A,0x00000001,0x00000000), //GICC Affinity Processor 26
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000001B,0x00000001,0x00000000), //GICC Affinity Processor 27
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000001C,0x00000001,0x00000000), //GICC Affinity Processor 28
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000001D,0x00000001,0x00000000), //GICC Affinity Processor 29
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000001E,0x00000001,0x00000000), //GICC Affinity Processor 30
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000001F,0x00000001,0x00000000), //GICC Affinity Processor 31
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000020,0x00000001,0x00000000), //GICC Affinity Processor 32
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000021,0x00000001,0x00000000), //GICC Affinity Processor 33
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000022,0x00000001,0x00000000), //GICC Affinity Processor 34
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000023,0x00000001,0x00000000), //GICC Affinity Processor 35
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000024,0x00000001,0x00000000), //GICC Affinity Processor 36
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000025,0x00000001,0x00000000), //GICC Affinity Processor 37
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000026,0x00000001,0x00000000), //GICC Affinity Processor 38
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000027,0x00000001,0x00000000), //GICC Affinity Processor 39
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000028,0x00000001,0x00000000), //GICC Affinity Processor 40
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000029,0x00000001,0x00000000), //GICC Affinity Processor 41
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000002A,0x00000001,0x00000000), //GICC Affinity Processor 42
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000002B,0x00000001,0x00000000), //GICC Affinity Processor 43
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000002C,0x00000001,0x00000000), //GICC Affinity Processor 44
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000002D,0x00000001,0x00000000), //GICC Affinity Processor 45
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000002E,0x00000001,0x00000000), //GICC Affinity Processor 46
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000002F,0x00000001,0x00000000), //GICC Affinity Processor 47
+
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000030,0x00000001,0x00000000), //GICC Affinity Processor 48
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000031,0x00000001,0x00000000), //GICC Affinity Processor 49
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000032,0x00000001,0x00000000), //GICC Affinity Processor 50
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000033,0x00000001,0x00000000), //GICC Affinity Processor 51
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000034,0x00000001,0x00000000), //GICC Affinity Processor 52
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000035,0x00000001,0x00000000), //GICC Affinity Processor 53
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000036,0x00000001,0x00000000), //GICC Affinity Processor 54
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000037,0x00000001,0x00000000), //GICC Affinity Processor 55
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000038,0x00000001,0x00000000), //GICC Affinity Processor 56
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000039,0x00000001,0x00000000), //GICC Affinity Processor 57
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003A,0x00000001,0x00000000), //GICC Affinity Processor 58
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003B,0x00000001,0x00000000), //GICC Affinity Processor 59
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003C,0x00000001,0x00000000), //GICC Affinity Processor 60
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003D,0x00000001,0x00000000), //GICC Affinity Processor 61
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003E,0x00000001,0x00000000), //GICC Affinity Processor 62
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003F,0x00000001,0x00000000), //GICC Affinity Processor 63
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000040,0x00000001,0x00000000), //GICC Affinity Processor 64
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000041,0x00000001,0x00000000), //GICC Affinity Processor 65
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000042,0x00000001,0x00000000), //GICC Affinity Processor 66
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000043,0x00000001,0x00000000), //GICC Affinity Processor 67
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000044,0x00000001,0x00000000), //GICC Affinity Processor 68
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000045,0x00000001,0x00000000), //GICC Affinity Processor 69
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000046,0x00000001,0x00000000), //GICC Affinity Processor 70
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000047,0x00000001,0x00000000), //GICC Affinity Processor 71
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000048,0x00000001,0x00000000), //GICC Affinity Processor 72
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000049,0x00000001,0x00000000), //GICC Affinity Processor 73
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000004A,0x00000001,0x00000000), //GICC Affinity Processor 74
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000004B,0x00000001,0x00000000), //GICC Affinity Processor 75
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000004C,0x00000001,0x00000000), //GICC Affinity Processor 76
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000004D,0x00000001,0x00000000), //GICC Affinity Processor 77
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000004E,0x00000001,0x00000000), //GICC Affinity Processor 78
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000004F,0x00000001,0x00000000), //GICC Affinity Processor 79
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000050,0x00000001,0x00000000), //GICC Affinity Processor 80
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000051,0x00000001,0x00000000), //GICC Affinity Processor 81
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000052,0x00000001,0x00000000), //GICC Affinity Processor 82
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000053,0x00000001,0x00000000), //GICC Affinity Processor 83
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000054,0x00000001,0x00000000), //GICC Affinity Processor 84
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000055,0x00000001,0x00000000), //GICC Affinity Processor 85
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000056,0x00000001,0x00000000), //GICC Affinity Processor 86
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000057,0x00000001,0x00000000), //GICC Affinity Processor 87
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000058,0x00000001,0x00000000), //GICC Affinity Processor 88
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000059,0x00000001,0x00000000), //GICC Affinity Processor 89
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000005A,0x00000001,0x00000000), //GICC Affinity Processor 90
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000005B,0x00000001,0x00000000), //GICC Affinity Processor 91
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000005C,0x00000001,0x00000000), //GICC Affinity Processor 92
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000005D,0x00000001,0x00000000), //GICC Affinity Processor 93
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000005E,0x00000001,0x00000000), //GICC Affinity Processor 94
+ EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000005F,0x00000001,0x00000000), //GICC Affinity Processor 95
+ },
+ {
+ EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x00000001, 0x00000000),
+ // EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x00000003, 0x00000001),
+ },
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Srat;
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/MadtHi1620.aslc b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/MadtHi1620.aslc
new file mode 100644
index 0000000000..43b43142af
--- /dev/null
+++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/MadtHi1620.aslc
@@ -0,0 +1,375 @@
+/** @file
+* Multiple APIC Description Table (MADT)
+*
+* Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
+* Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+#include "Hi1620Platform.h"
+
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiNextLib.h>
+
+// Differs from Juno, we have another affinity level beyond cluster and core
+// 0x20000 is only for socket 0
+#define PLATFORM_GET_MPID_TA(ClusterId, CoreId) (0x10000 | ((ClusterId) << 8) | (CoreId))
+#define PLATFORM_GET_MPID_TB(ClusterId, CoreId) (0x30000 | ((ClusterId) << 8) | (CoreId))
+#define PLATFORM_GET_MPID_TA_2(ClusterId, CoreId) (0x50000 | ((ClusterId) << 8) | (CoreId))
+#define PLATFORM_GET_MPID_TB_2(ClusterId, CoreId) (0x70000 | ((ClusterId) << 8) | (CoreId))
+
+//
+// Multiple APIC Description Table
+//
+#pragma pack (1)
+
+typedef struct {
+ EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT];
+ EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
+ EFI_ACPI_6_2_GIC_ITS_STRUCTURE GicITS[EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_COUNT];
+} EFI_ACPI_MULTIPLE_APIC_DESCRIPTION_TABLE;
+
+#pragma pack ()
+
+EFI_ACPI_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ ),
+ //
+ // MADT specific fields
+ //
+ 0, // LocalApicAddress
+ 0, // Flags
+ },
+ {
+ // Format: EFI_ACPI_6_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase,
+ // GsivId, GicRBase, Mpidr)
+ // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of
+ // ACPI v5.1).
+ // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses
+ // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 0, 0, PLATFORM_GET_MPID_TA(0, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAE000000 + 0x100000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 1, 1, PLATFORM_GET_MPID_TA(0, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAE000000 + 0x140000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 2, 2, PLATFORM_GET_MPID_TA(0, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAE000000 + 0x180000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 3, 3, PLATFORM_GET_MPID_TA(0, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAE000000 + 0x1C0000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 4, 4, PLATFORM_GET_MPID_TA(1, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAE000000 + 0x200000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 5, 5, PLATFORM_GET_MPID_TA(1, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAE000000 + 0x240000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 6, 6, PLATFORM_GET_MPID_TA(1, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAE000000 + 0x280000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 7, 7, PLATFORM_GET_MPID_TA(1, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAE000000 + 0x2C0000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 8, 8, PLATFORM_GET_MPID_TA(2, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAE000000 + 0x300000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 9, 9, PLATFORM_GET_MPID_TA(2, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAE000000 + 0x340000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 10, 10, PLATFORM_GET_MPID_TA(2, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAE000000 + 0x380000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 11, 11, PLATFORM_GET_MPID_TA(2, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAE000000 + 0x3C0000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 12, 12, PLATFORM_GET_MPID_TA(3, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAE000000 + 0x400000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 13, 13, PLATFORM_GET_MPID_TA(3, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAE000000 + 0x440000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 14, 14, PLATFORM_GET_MPID_TA(3, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAE000000 + 0x480000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 15, 15, PLATFORM_GET_MPID_TA(3, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAE000000 + 0x4C0000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 16, 16, PLATFORM_GET_MPID_TA(4, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAE000000 + 0x500000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 17, 17, PLATFORM_GET_MPID_TA(4, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAE000000 + 0x540000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 18, 18, PLATFORM_GET_MPID_TA(4, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAE000000 + 0x580000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 19, 19, PLATFORM_GET_MPID_TA(4, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAE000000 + 0x5C0000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 20, 20, PLATFORM_GET_MPID_TA(5, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAE000000 + 0x600000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 21, 21, PLATFORM_GET_MPID_TA(5, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAE000000 + 0x640000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 22, 22, PLATFORM_GET_MPID_TA(5, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAE000000 + 0x680000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 23, 23, PLATFORM_GET_MPID_TA(5, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAE000000 + 0x6C0000 /* GicRBase */, 0),
+
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 24, 24, PLATFORM_GET_MPID_TB(0, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAA000000 + 0x100000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 25, 25, PLATFORM_GET_MPID_TB(0, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAA000000 + 0x140000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 26, 26, PLATFORM_GET_MPID_TB(0, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAA000000 + 0x180000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 27, 27, PLATFORM_GET_MPID_TB(0, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAA000000 + 0x1C0000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 28, 28, PLATFORM_GET_MPID_TB(1, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAA000000 + 0x200000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 29, 29, PLATFORM_GET_MPID_TB(1, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAA000000 + 0x240000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 30, 30, PLATFORM_GET_MPID_TB(1, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAA000000 + 0x280000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 31, 31, PLATFORM_GET_MPID_TB(1, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAA000000 + 0x2C0000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 32, 32, PLATFORM_GET_MPID_TB(2, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAA000000 + 0x300000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 33, 33, PLATFORM_GET_MPID_TB(2, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAA000000 + 0x340000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 34, 34, PLATFORM_GET_MPID_TB(2, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAA000000 + 0x380000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 35, 35, PLATFORM_GET_MPID_TB(2, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAA000000 + 0x3C0000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 36, 36, PLATFORM_GET_MPID_TB(3, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAA000000 + 0x400000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 37, 37, PLATFORM_GET_MPID_TB(3, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAA000000 + 0x440000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 38, 38, PLATFORM_GET_MPID_TB(3, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAA000000 + 0x480000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 39, 39, PLATFORM_GET_MPID_TB(3, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAA000000 + 0x4C0000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 40, 40, PLATFORM_GET_MPID_TB(4, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAA000000 + 0x500000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 41, 41, PLATFORM_GET_MPID_TB(4, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAA000000 + 0x540000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 42, 42, PLATFORM_GET_MPID_TB(4, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAA000000 + 0x580000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 43, 43, PLATFORM_GET_MPID_TB(4, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAA000000 + 0x5C0000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 44, 44, PLATFORM_GET_MPID_TB(5, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAA000000 + 0x600000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 45, 45, PLATFORM_GET_MPID_TB(5, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAA000000 + 0x640000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 46, 46, PLATFORM_GET_MPID_TB(5, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAA000000 + 0x680000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 47, 47, PLATFORM_GET_MPID_TB(5, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0xAA000000 + 0x6C0000 /* GicRBase */, 0),
+
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 48, 48, PLATFORM_GET_MPID_TA_2(0, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AE000000 + 0x100000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 49, 49, PLATFORM_GET_MPID_TA_2(0, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AE000000 + 0x140000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 50, 50, PLATFORM_GET_MPID_TA_2(0, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AE000000 + 0x180000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 51, 51, PLATFORM_GET_MPID_TA_2(0, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AE000000 + 0x1C0000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 52, 52, PLATFORM_GET_MPID_TA_2(1, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AE000000 + 0x200000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 53, 53, PLATFORM_GET_MPID_TA_2(1, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AE000000 + 0x240000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 54, 54, PLATFORM_GET_MPID_TA_2(1, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AE000000 + 0x280000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 55, 55, PLATFORM_GET_MPID_TA_2(1, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AE000000 + 0x2C0000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 56, 56, PLATFORM_GET_MPID_TA_2(2, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AE000000 + 0x300000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 57, 57, PLATFORM_GET_MPID_TA_2(2, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AE000000 + 0x340000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 58, 58, PLATFORM_GET_MPID_TA_2(2, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AE000000 + 0x380000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 59, 59, PLATFORM_GET_MPID_TA_2(2, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AE000000 + 0x3C0000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 60, 60, PLATFORM_GET_MPID_TA_2(3, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AE000000 + 0x400000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 61, 61, PLATFORM_GET_MPID_TA_2(3, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AE000000 + 0x440000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 62, 62, PLATFORM_GET_MPID_TA_2(3, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AE000000 + 0x480000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 63, 63, PLATFORM_GET_MPID_TA_2(3, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AE000000 + 0x4C0000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 64, 64, PLATFORM_GET_MPID_TA_2(4, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AE000000 + 0x500000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 65, 65, PLATFORM_GET_MPID_TA_2(4, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AE000000 + 0x540000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 66, 66, PLATFORM_GET_MPID_TA_2(4, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AE000000 + 0x580000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 67, 67, PLATFORM_GET_MPID_TA_2(4, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AE000000 + 0x5C0000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 68, 68, PLATFORM_GET_MPID_TA_2(5, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AE000000 + 0x600000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 69, 69, PLATFORM_GET_MPID_TA_2(5, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AE000000 + 0x640000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 70, 70, PLATFORM_GET_MPID_TA_2(5, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AE000000 + 0x680000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 71, 71, PLATFORM_GET_MPID_TA_2(5, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AE000000 + 0x6C0000 /* GicRBase */, 0),
+
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 72, 72, PLATFORM_GET_MPID_TB_2(0, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AA000000 + 0x100000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 73, 73, PLATFORM_GET_MPID_TB_2(0, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AA000000 + 0x140000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 74, 74, PLATFORM_GET_MPID_TB_2(0, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AA000000 + 0x180000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 75, 75, PLATFORM_GET_MPID_TB_2(0, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AA000000 + 0x1C0000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 76, 76, PLATFORM_GET_MPID_TB_2(1, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AA000000 + 0x200000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 77, 77, PLATFORM_GET_MPID_TB_2(1, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AA000000 + 0x240000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 78, 78, PLATFORM_GET_MPID_TB_2(1, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AA000000 + 0x280000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 79, 79, PLATFORM_GET_MPID_TB_2(1, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AA000000 + 0x2C0000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 80, 80, PLATFORM_GET_MPID_TB_2(2, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AA000000 + 0x300000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 81, 81, PLATFORM_GET_MPID_TB_2(2, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AA000000 + 0x340000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 82, 82, PLATFORM_GET_MPID_TB_2(2, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AA000000 + 0x380000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 83, 83, PLATFORM_GET_MPID_TB_2(2, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AA000000 + 0x3C0000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 84, 84, PLATFORM_GET_MPID_TB_2(3, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AA000000 + 0x400000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 85, 85, PLATFORM_GET_MPID_TB_2(3, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AA000000 + 0x440000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 86, 86, PLATFORM_GET_MPID_TB_2(3, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AA000000 + 0x480000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 87, 87, PLATFORM_GET_MPID_TB_2(3, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AA000000 + 0x4C0000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 88, 88, PLATFORM_GET_MPID_TB_2(4, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AA000000 + 0x500000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 89, 89, PLATFORM_GET_MPID_TB_2(4, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AA000000 + 0x540000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 90, 90, PLATFORM_GET_MPID_TB_2(4, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AA000000 + 0x580000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 91, 91, PLATFORM_GET_MPID_TB_2(4, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AA000000 + 0x5C0000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 92, 92, PLATFORM_GET_MPID_TB_2(5, 0), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AA000000 + 0x600000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 93, 93, PLATFORM_GET_MPID_TB_2(5, 1), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AA000000 + 0x640000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 94, 94, PLATFORM_GET_MPID_TB_2(5, 2), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AA000000 + 0x680000 /* GicRBase */, 0),
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
+ 95, 95, PLATFORM_GET_MPID_TB_2(5, 3), EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+ 0x0, 0x0, 25, 0x4000AA000000 + 0x6C0000 /* GicRBase */, 0),
+ },
+
+ EFI_ACPI_6_1_GIC_DISTRIBUTOR_INIT(0, 0xAA000000, 0, 0x4),
+ {
+ EFI_ACPI_6_1_GIC_ITS_INIT(0,0x202100000), //peri a
+// EFI_ACPI_6_1_GIC_ITS_INIT(1,0x400202100000), //peri a
+ }
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Madt;
--
2.18.0
next prev parent reply other threads:[~2018-08-23 16:09 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-23 16:07 [PATCH edk2-platforms v4 00/31] Upload for D06 platform Ming Huang
2018-08-23 16:07 ` [PATCH edk2-platforms v4 01/31] Silicon/Hisilicon/Acpi: Move some macro to PlatformArch.h Ming Huang
2018-08-30 18:29 ` Leif Lindholm
2018-08-23 16:07 ` [PATCH edk2-platforms v4 02/31] Silicon/Hisilicon/D0x: Move RAS " Ming Huang
2018-08-30 18:29 ` Leif Lindholm
2018-08-23 16:07 ` [PATCH edk2-platforms v4 03/31] Silicon/Hisilicon: Fix I2CLib enable fail issue Ming Huang
2018-08-23 16:07 ` [PATCH edk2-platforms v4 04/31] Silicon/Hisilicon: Add I2CLib delay for HNS auto config Ming Huang
2018-08-23 16:07 ` [PATCH edk2-platforms v4 05/31] Silicon/Hisilicon: Optimize I2CLib for HNS config CDR time Ming Huang
2018-08-23 16:07 ` [PATCH edk2-platforms v4 06/31] Hisilicon/D06: Add several base file for D06 Ming Huang
2018-08-30 18:14 ` Leif Lindholm
2018-08-23 16:07 ` [PATCH edk2-platforms v4 07/31] Platform/Hisilicon/D06: Add M41T83RealTimeClockLib Ming Huang
2018-08-30 19:00 ` Leif Lindholm
2018-08-23 16:07 ` [PATCH edk2-platforms v4 08/31] Platform/Hisilicon/D06: Add edk2-non-osi components for D06 Ming Huang
2018-08-30 18:59 ` Leif Lindholm
2018-08-23 16:07 ` [PATCH edk2-platforms v4 09/31] Hisilicon/D06: Add OemMiscLibD06 Ming Huang
2018-08-23 16:07 ` [PATCH edk2-platforms v4 10/31] Silicon/Hisilicon/D06: Wait for all disk ready Ming Huang
2018-08-30 16:51 ` Leif Lindholm
2018-08-23 16:07 ` [PATCH edk2-platforms v4 11/31] Silicon/Hisilicon/Acpi: Unify HisiAcpiPlatformDxe Ming Huang
2018-08-30 18:39 ` Leif Lindholm
2018-08-31 2:12 ` Ming
2018-08-23 16:07 ` [PATCH edk2-platforms v4 12/31] Hisilicon/D06: Add Debug Serial Port Init Driver Ming Huang
2018-08-23 16:07 ` Ming Huang [this message]
2018-08-23 16:07 ` [PATCH edk2-platforms v4 14/31] Hisilicon/D06: Add Hi1620OemConfigUiLib Ming Huang
2018-08-30 18:58 ` Leif Lindholm
2018-08-23 16:07 ` [PATCH edk2-platforms v4 15/31] Silicon/Hisilicon/D06: Stop watchdog Ming Huang
2018-08-23 16:07 ` [PATCH edk2-platforms v4 16/31] Silicon/Hisilicon/Setup: Add Setup Item "EnableGOP" Ming Huang
2018-08-30 18:41 ` Leif Lindholm
2018-08-23 16:07 ` [PATCH edk2-platforms v4 17/31] Hisilicon/Hi1620: Add ACPI PPTT table Ming Huang
2018-08-23 16:07 ` [PATCH edk2-platforms v4 18/31] Platform/Hisilicon/D06: Enable ACPI PPTT Ming Huang
2018-08-23 16:07 ` [PATCH edk2-platforms v4 19/31] Platform/Hisilicon/D06: Add OemNicLib Ming Huang
2018-08-30 18:45 ` Leif Lindholm
2018-08-23 16:07 ` [PATCH edk2-platforms v4 20/31] Platform/Hisilicon/D06: Add OemNicConfig2P Driver Ming Huang
2018-08-23 16:07 ` [PATCH edk2-platforms v4 21/31] Hisilicon/D0x: Update SMBIOS type9 info Ming Huang
2018-08-23 16:07 ` [PATCH edk2-platforms v4 22/31] Platform/Hisilicon/D06: Add EarlyConfigPeim peim Ming Huang
2018-08-23 16:07 ` [PATCH edk2-platforms v4 23/31] Platform/Hisilicon/D06: Add PciHostBridgeLib Ming Huang
2018-08-23 16:07 ` [PATCH edk2-platforms v4 24/31] Hisilicon/D06: add apei driver Ming Huang
2018-08-30 18:47 ` Leif Lindholm
2018-08-23 16:07 ` [PATCH edk2-platforms v4 25/31] Platform/Hisilicon/D06: Add capsule upgrade support Ming Huang
2018-08-30 18:49 ` Leif Lindholm
2018-08-23 16:07 ` [PATCH edk2-platforms v4 26/31] Silicon/Hisilicon: Modify for close slave core clock Ming Huang
2018-08-30 18:50 ` Leif Lindholm
2018-08-23 16:07 ` [PATCH edk2-platforms v4 27/31] Silicon/Hisilicon: Add I2C Bus Exception handle function Ming Huang
2018-08-30 18:51 ` Leif Lindholm
2018-08-23 16:07 ` [PATCH edk2-platforms v4 28/31] Silicon/Hisilicon/Setup: Support SPCR table switch Ming Huang
2018-08-30 18:52 ` Leif Lindholm
2018-08-23 16:07 ` [PATCH edk2-platforms v4 29/31] Silicon/Hisilicon/setup: Enable/disable SMMU Ming Huang
2018-08-30 18:55 ` Leif Lindholm
2018-08-23 16:07 ` [PATCH edk2-platforms v4 30/31] Hisilicon/D06: Add PciPlatformLib Ming Huang
2018-08-30 16:15 ` Leif Lindholm
2018-08-31 6:17 ` Ming
2018-08-23 16:07 ` [PATCH edk2-platforms v4 31/31] Platform/Hisilicon/D0x: Update version string to 18.08 Ming Huang
2018-08-30 20:20 ` [PATCH edk2-platforms v4 00/31] Upload for D06 platform Leif Lindholm
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