From: Ming Huang <ming.huang@linaro.org>
To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org,
edk2-devel@lists.01.org, graeme.gregory@linaro.org
Cc: ard.biesheuvel@linaro.org, michael.d.kinney@intel.com,
lersek@redhat.com, guoheyi@huawei.com, wanghuiqiang@huawei.com,
huangming23@huawei.com, zhangjinsong2@huawei.com,
huangdaode@hisilicon.com, john.garry@huawei.com,
xinliang.liu@linaro.org, Sun Yuanchen <sunyuanchen@huawei.com>,
Ming Huang <ming.huang@linaro.org>
Subject: [PATCH edk2-platforms v4 21/31] Hisilicon/D0x: Update SMBIOS type9 info
Date: Fri, 24 Aug 2018 00:07:33 +0800 [thread overview]
Message-ID: <20180823160743.45638-22-ming.huang@linaro.org> (raw)
In-Reply-To: <20180823160743.45638-1-ming.huang@linaro.org>
From: Sun Yuanchen <sunyuanchen@huawei.com>
Move board level code to OemMiscLibD0x for unifying D0x.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <ming.huang@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf | 1 +
Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf | 1 +
Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf | 4 +
Platform/Hisilicon/D06/Include/Library/CpldD06.h | 2 +
Silicon/Hisilicon/Include/Library/OemMiscLib.h | 1 +
Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c | 32 +++++++
Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c | 27 +++++-
Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c | 90 ++++++++++++++++++++
Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.c | 14 +--
9 files changed, 159 insertions(+), 13 deletions(-)
diff --git a/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf
index 310bbaea84..0fa7fdf80f 100644
--- a/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf
+++ b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf
@@ -34,6 +34,7 @@
Silicon/Hisilicon/HisiPkg.dec
[LibraryClasses]
+ BaseMemoryLib
PcdLib
TimerLib
diff --git a/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf
index bf44ff7440..022c3e940a 100644
--- a/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf
+++ b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf
@@ -33,6 +33,7 @@
Silicon/Hisilicon/HisiPkg.dec
[LibraryClasses]
+ BaseMemoryLib
PcdLib
TimerLib
diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf
index 8f68f7cec5..bd984a6fe3 100644
--- a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf
+++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf
@@ -30,9 +30,13 @@
ArmPkg/ArmPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
+ Platform/Hisilicon/D06/D06.dec
Silicon/Hisilicon/HisiPkg.dec
[LibraryClasses]
+ BaseMemoryLib
+ CpldIoLib
+ IoLib
PcdLib
SerdesLib
TimerLib
diff --git a/Platform/Hisilicon/D06/Include/Library/CpldD06.h b/Platform/Hisilicon/D06/Include/Library/CpldD06.h
index be3548c8d1..ec9b49f4e7 100644
--- a/Platform/Hisilicon/D06/Include/Library/CpldD06.h
+++ b/Platform/Hisilicon/D06/Include/Library/CpldD06.h
@@ -29,6 +29,8 @@
#define CPLD_LOGIC_COMPILE_DAY (0x3)
#define CPLD_RISER_PRSNT_FLAG 0x40
+#define CPU1_RISER_PRESENT BIT6
+#define CPU0_RISER_PRESENT BIT7
#define CPLD_RISER2_BOARD_ID 0x44
#define CPLD_X8_X8_X8_BOARD_ID 0x92
diff --git a/Silicon/Hisilicon/Include/Library/OemMiscLib.h b/Silicon/Hisilicon/Include/Library/OemMiscLib.h
index efecb9aa77..86ea6a1b3d 100644
--- a/Silicon/Hisilicon/Include/Library/OemMiscLib.h
+++ b/Silicon/Hisilicon/Include/Library/OemMiscLib.h
@@ -34,6 +34,7 @@ typedef struct _REPORT_PCIEDIDVID2BMC{
UINTN Slot;
}REPORT_PCIEDIDVID2BMC;
extern REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX];
+extern VOID GetPciDidVid (REPORT_PCIEDIDVID2BMC *Report);
BOOLEAN OemIsSocketPresent (UINTN Socket);
VOID CoreSelectBoot(VOID);
diff --git a/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c
index fa1039bda1..b57fdfa68e 100644
--- a/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c
+++ b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c
@@ -15,6 +15,7 @@
#include <Uefi.h>
+#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/TimerLib.h>
@@ -31,6 +32,37 @@ REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX] = {
{0xFFFF,0xFFFF,0xFFFF,0xFFFF}
};
+REPORT_PCIEDIDVID2BMC PcieDeviceToReport2P[PCIEDEVICE_REPORT_MAX] = {
+ {0x79,0,0,0},
+ {0xFF,0xFF,0xFF,1},
+ {0xC1,0,0,2},
+ {0xF9,0,0,3},
+ {0xFF,0xFF,0xFF,4},
+ {0x11,0,0,5},
+ {0x31,0,0,6},
+ {0x21,0,0,7}
+};
+
+VOID
+GetPciDidVid (
+ REPORT_PCIEDIDVID2BMC *Report
+ )
+{
+ if (OemIsMpBoot ()) {
+ (VOID)CopyMem (
+ (VOID *)Report,
+ (VOID *)PcieDeviceToReport2P,
+ sizeof (PcieDeviceToReport2P)
+ );
+ } else {
+ (VOID)CopyMem (
+ (VOID *)Report,
+ (VOID *)PcieDeviceToReport,
+ sizeof (PcieDeviceToReport)
+ );
+ }
+}
+
// Right now we only support 1P
BOOLEAN OemIsSocketPresent (UINTN Socket)
{
diff --git a/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c
index b17eeada16..4c4c944dbe 100644
--- a/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c
+++ b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c
@@ -1,7 +1,7 @@
/** @file
*
-* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
-* Copyright (c) 2016, Linaro Limited. All rights reserved.
+* Copyright (c) 2016 - 2018, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016 - 2018, Linaro Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
@@ -16,6 +16,7 @@
#include <PlatformArch.h>
#include <Uefi.h>
+#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/LpcLib.h>
@@ -37,6 +38,28 @@ REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX] = {
{0xFFFF,0xFFFF,0xFFFF,0xFFFF}
};
+REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P[PCIEDEVICE_REPORT_MAX] = {
+ {0x79,0,0,0},
+ {0xFF,0xFF,0xFF,1},
+ {0xC1,0,0,2},
+ {0xF9,0,0,3},
+ {0xFF,0xFF,0xFF,4},
+ {0x11,0,0,5},
+ {0x31,0,0,6},
+ {0x21,0,0,7}
+};
+
+VOID
+GetPciDidVid (
+ REPORT_PCIEDIDVID2BMC *Report
+ )
+{
+ if (OemIsMpBoot ()) {
+ (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport_2P, sizeof (PcieDeviceToReport_2P));
+ } else {
+ (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport, sizeof (PcieDeviceToReport));
+ }
+}
BOOLEAN OemIsSocketPresent (UINTN Socket)
{
diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c
index 95521752ff..2a9db46d1f 100644
--- a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c
+++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c
@@ -15,6 +15,8 @@
#include <Uefi.h>
#include <PlatformArch.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/CpldD06.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/LpcLib.h>
@@ -33,6 +35,94 @@ REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX] = {
{0xFFFF,0xFFFF,0xFFFF,0xFFFF}
};
+//Cpu0 Riser type is (X16 + X8) & Cpu1 Riser type is (X16 + X8)
+REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P_Type1 [PCIEDEVICE_REPORT_MAX] = {
+ {0x01,0,0,0},
+ {0x03,0,0,1},
+ {0xFF,0xFF,0xFF,2},
+ {0x81,0,0,3},
+ {0x84,0,0,4},
+ {0xFF,0xFF,0xFF,5}
+};
+
+//Cpu0 Riser type is (X16 + X8) & Cpu1 Riser type is (3 * X8)
+REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P_Type2 [PCIEDEVICE_REPORT_MAX] = {
+ {0x01,0,0,0},
+ {0x03,0,0,1},
+ {0xFF,0xFF,0xFF,2},
+ {0xFF,0xFF,0xFF,3},
+ {0x81,0,0,4},
+ {0x85,0,0,5}
+};
+
+//Cpu0 Riser type is (3 * X8) & Cpu1 Riser type is (X16 + X8)
+REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P_Type3 [PCIEDEVICE_REPORT_MAX] = {
+ {0xFF,0xFF,0xFF,0},
+ {0x01,0,0,1},
+ {0x04,0,0,2},
+ {0x81,0,0,3},
+ {0x84,0,0,4},
+ {0xFF,0xFF,0xFF,5}
+};
+
+//Cpu0 Riser type is (3 * X8) & Cpu1 Riser type is (3 * X8)
+REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P_Type4 [PCIEDEVICE_REPORT_MAX] = {
+ {0xFF,0xFF,0xFF,0},
+ {0x01,0,0,1},
+ {0x04,0,0,2},
+ {0xFF,0xFF,0xFF,3},
+ {0x81,0,0,4},
+ {0x85,0,0,5}
+};
+
+VOID
+GetPciDidVid (
+ REPORT_PCIEDIDVID2BMC *Report
+ )
+{
+ UINT32 PresentStatus;
+ UINT32 CardType;
+ UINT8 Cpu0CardType = 0;
+ UINT8 Cpu1CardType = 0;
+
+ PresentStatus = MmioRead32 (CPLD_BASE_ADDRESS + CPLD_RISER_PRSNT_FLAG);
+ CardType = MmioRead32 (CPLD_BASE_ADDRESS + CPLD_RISER2_BOARD_ID);
+
+ // Offset 0x40: Bit7 = 1 CPU0 Riser present
+ if ((PresentStatus & CPU0_RISER_PRESENT) != 0) {
+ Cpu0CardType = (UINT8) (PresentStatus >> 8);
+ }
+
+ // Offset 0x40: Bit6 = 1 CPU1 Riser present
+ if ((PresentStatus & CPU1_RISER_PRESENT) != 0) {
+ Cpu1CardType = (UINT8)CardType;
+ }
+
+ if (OemIsMpBoot ()) {
+ if (Cpu0CardType == CPLD_X16_X8_BOARD_ID) {
+ if (Cpu1CardType == CPLD_X16_X8_BOARD_ID) {
+ (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport_2P_Type1,
+ sizeof (PcieDeviceToReport_2P_Type1));
+ } else {
+ (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport_2P_Type2,
+ sizeof (PcieDeviceToReport_2P_Type2));
+ }
+ } else {
+ if (Cpu1CardType == CPLD_X16_X8_BOARD_ID) {
+ (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport_2P_Type3,
+ sizeof (PcieDeviceToReport_2P_Type3));
+ } else {
+ (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport_2P_Type4,
+ sizeof (PcieDeviceToReport_2P_Type4));
+ }
+ }
+ } else {
+ (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport,
+ sizeof (PcieDeviceToReport));
+ }
+}
+
+
// Right now we only support 1P
BOOLEAN
OemIsSocketPresent (
diff --git a/Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.c b/Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.c
index 8d8dacd3e0..cc1131577d 100644
--- a/Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.c
+++ b/Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.c
@@ -18,12 +18,6 @@
extern SMBIOS_TABLE_TYPE9 gPcieSlotInfo[];
extern UINT8 OemGetPcieSlotNumber ();
-REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P[PCIEDEVICE_REPORT_MAX] = {
- {67,0,0,0},
- {225,0,0,3},
- {0xFFFF,0xFFFF,0xFFFF,0xFFFF},
- {0xFFFF,0xFFFF,0xFFFF,0xFFFF}
-};
VOID
EFIAPI
UpdateSmbiosType9Info(
@@ -41,11 +35,9 @@ UpdateSmbiosType9Info(
UINTN FunctionNumber;
UINTN Index;
REPORT_PCIEDIDVID2BMC ReportPcieDidVid[PCIEDEVICE_REPORT_MAX];
- if(OemIsMpBoot()){
- (VOID)CopyMem((VOID *)ReportPcieDidVid,(VOID *)PcieDeviceToReport_2P,sizeof(PcieDeviceToReport_2P));
- } else {
- (VOID)CopyMem((VOID *)ReportPcieDidVid,(VOID *)PcieDeviceToReport,sizeof(PcieDeviceToReport));
- }
+
+ GetPciDidVid ((VOID *) ReportPcieDidVid);
+
Status = gBS->LocateHandleBuffer (
ByProtocol,
&gEfiPciIoProtocolGuid,
--
2.18.0
next prev parent reply other threads:[~2018-08-23 16:10 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-23 16:07 [PATCH edk2-platforms v4 00/31] Upload for D06 platform Ming Huang
2018-08-23 16:07 ` [PATCH edk2-platforms v4 01/31] Silicon/Hisilicon/Acpi: Move some macro to PlatformArch.h Ming Huang
2018-08-30 18:29 ` Leif Lindholm
2018-08-23 16:07 ` [PATCH edk2-platforms v4 02/31] Silicon/Hisilicon/D0x: Move RAS " Ming Huang
2018-08-30 18:29 ` Leif Lindholm
2018-08-23 16:07 ` [PATCH edk2-platforms v4 03/31] Silicon/Hisilicon: Fix I2CLib enable fail issue Ming Huang
2018-08-23 16:07 ` [PATCH edk2-platforms v4 04/31] Silicon/Hisilicon: Add I2CLib delay for HNS auto config Ming Huang
2018-08-23 16:07 ` [PATCH edk2-platforms v4 05/31] Silicon/Hisilicon: Optimize I2CLib for HNS config CDR time Ming Huang
2018-08-23 16:07 ` [PATCH edk2-platforms v4 06/31] Hisilicon/D06: Add several base file for D06 Ming Huang
2018-08-30 18:14 ` Leif Lindholm
2018-08-23 16:07 ` [PATCH edk2-platforms v4 07/31] Platform/Hisilicon/D06: Add M41T83RealTimeClockLib Ming Huang
2018-08-30 19:00 ` Leif Lindholm
2018-08-23 16:07 ` [PATCH edk2-platforms v4 08/31] Platform/Hisilicon/D06: Add edk2-non-osi components for D06 Ming Huang
2018-08-30 18:59 ` Leif Lindholm
2018-08-23 16:07 ` [PATCH edk2-platforms v4 09/31] Hisilicon/D06: Add OemMiscLibD06 Ming Huang
2018-08-23 16:07 ` [PATCH edk2-platforms v4 10/31] Silicon/Hisilicon/D06: Wait for all disk ready Ming Huang
2018-08-30 16:51 ` Leif Lindholm
2018-08-23 16:07 ` [PATCH edk2-platforms v4 11/31] Silicon/Hisilicon/Acpi: Unify HisiAcpiPlatformDxe Ming Huang
2018-08-30 18:39 ` Leif Lindholm
2018-08-31 2:12 ` Ming
2018-08-23 16:07 ` [PATCH edk2-platforms v4 12/31] Hisilicon/D06: Add Debug Serial Port Init Driver Ming Huang
2018-08-23 16:07 ` [PATCH edk2-platforms v4 13/31] Hisilicon/D06: Add ACPI Tables for D06 Ming Huang
2018-08-23 16:07 ` [PATCH edk2-platforms v4 14/31] Hisilicon/D06: Add Hi1620OemConfigUiLib Ming Huang
2018-08-30 18:58 ` Leif Lindholm
2018-08-23 16:07 ` [PATCH edk2-platforms v4 15/31] Silicon/Hisilicon/D06: Stop watchdog Ming Huang
2018-08-23 16:07 ` [PATCH edk2-platforms v4 16/31] Silicon/Hisilicon/Setup: Add Setup Item "EnableGOP" Ming Huang
2018-08-30 18:41 ` Leif Lindholm
2018-08-23 16:07 ` [PATCH edk2-platforms v4 17/31] Hisilicon/Hi1620: Add ACPI PPTT table Ming Huang
2018-08-23 16:07 ` [PATCH edk2-platforms v4 18/31] Platform/Hisilicon/D06: Enable ACPI PPTT Ming Huang
2018-08-23 16:07 ` [PATCH edk2-platforms v4 19/31] Platform/Hisilicon/D06: Add OemNicLib Ming Huang
2018-08-30 18:45 ` Leif Lindholm
2018-08-23 16:07 ` [PATCH edk2-platforms v4 20/31] Platform/Hisilicon/D06: Add OemNicConfig2P Driver Ming Huang
2018-08-23 16:07 ` Ming Huang [this message]
2018-08-23 16:07 ` [PATCH edk2-platforms v4 22/31] Platform/Hisilicon/D06: Add EarlyConfigPeim peim Ming Huang
2018-08-23 16:07 ` [PATCH edk2-platforms v4 23/31] Platform/Hisilicon/D06: Add PciHostBridgeLib Ming Huang
2018-08-23 16:07 ` [PATCH edk2-platforms v4 24/31] Hisilicon/D06: add apei driver Ming Huang
2018-08-30 18:47 ` Leif Lindholm
2018-08-23 16:07 ` [PATCH edk2-platforms v4 25/31] Platform/Hisilicon/D06: Add capsule upgrade support Ming Huang
2018-08-30 18:49 ` Leif Lindholm
2018-08-23 16:07 ` [PATCH edk2-platforms v4 26/31] Silicon/Hisilicon: Modify for close slave core clock Ming Huang
2018-08-30 18:50 ` Leif Lindholm
2018-08-23 16:07 ` [PATCH edk2-platforms v4 27/31] Silicon/Hisilicon: Add I2C Bus Exception handle function Ming Huang
2018-08-30 18:51 ` Leif Lindholm
2018-08-23 16:07 ` [PATCH edk2-platforms v4 28/31] Silicon/Hisilicon/Setup: Support SPCR table switch Ming Huang
2018-08-30 18:52 ` Leif Lindholm
2018-08-23 16:07 ` [PATCH edk2-platforms v4 29/31] Silicon/Hisilicon/setup: Enable/disable SMMU Ming Huang
2018-08-30 18:55 ` Leif Lindholm
2018-08-23 16:07 ` [PATCH edk2-platforms v4 30/31] Hisilicon/D06: Add PciPlatformLib Ming Huang
2018-08-30 16:15 ` Leif Lindholm
2018-08-31 6:17 ` Ming
2018-08-23 16:07 ` [PATCH edk2-platforms v4 31/31] Platform/Hisilicon/D0x: Update version string to 18.08 Ming Huang
2018-08-30 20:20 ` [PATCH edk2-platforms v4 00/31] Upload for D06 platform Leif Lindholm
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