From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::441; helo=mail-pf1-x441.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf1-x441.google.com (mail-pf1-x441.google.com [IPv6:2607:f8b0:4864:20::441]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3BA9921106A0E for ; Thu, 23 Aug 2018 09:10:04 -0700 (PDT) Received: by mail-pf1-x441.google.com with SMTP id p12-v6so2992087pfh.2 for ; Thu, 23 Aug 2018 09:10:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=yaUejUqF7AoneMxrvA8XQ+i9VvoWQblGNnxSIXCM6wA=; b=geYdBeEurXWoy8cIjV2FGKWq6e7ahnmXHjPHc3VDDjmBIhIA8WfWaWoN84ZnA6LqwQ d7BUiAH+dZa48eTupEB2eHVgeTDuuAZcpaSRenVUcHa1WipWi2DZHWBVmC1GuV8p4RCz NZ463RNTjOJ1ePFhvHatkV0kjvXmXRkfMRGOQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=yaUejUqF7AoneMxrvA8XQ+i9VvoWQblGNnxSIXCM6wA=; b=paE5Pdxt1VW39GXCG30NXzznlUuQWz7cHi9vhXcW4QoRjop8uCznIcN1VllpXYowBk GvXyV9TdC3t0yARqP681lxU66ZLjh3XMMOg5U2ahNq6l1Fg5dESTEuR+Ftji+4lU2VgW s0dFkalNhPtl/hHSYpdBpgVx/fXxabJ3rP/Fp3jUJ0dwpexReVTmPZyxIH6PvFQg2CUd eOqAuqy4t7uOJPdcbqOfokv1dbuXAeaqOZw0n+VMEBH3cVK1qt8/d4jKHN4HSLhAADqV 4N+aFPMUO7HoVLWDQ/1fJGR5ouqgtYlZekWofHo9ZMvMHij1wTLfaa7GDo+c8LBrFjFk /r1Q== X-Gm-Message-State: AOUpUlGf8o2N9MQO+e1xNPPNMedF47/vjzBQ/i92AeWfj5lh4yAA6L7V cVPI010PAL+wMUhZOWZGEOq8CA== X-Google-Smtp-Source: AA+uWPzW2TbxLfF8TrFB9klsUy6vvteQyUl9Llq2kS3xuNP+tY1Pzm/fVl8OXpCvtTtbgX/abcmdjg== X-Received: by 2002:a63:cc4f:: with SMTP id q15-v6mr29954501pgi.217.1535040603829; Thu, 23 Aug 2018 09:10:03 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id d19-v6sm5788083pgv.61.2018.08.23.09.10.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 23 Aug 2018 09:10:03 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Cc: ard.biesheuvel@linaro.org, michael.d.kinney@intel.com, lersek@redhat.com, guoheyi@huawei.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, john.garry@huawei.com, xinliang.liu@linaro.org, Ming Huang Date: Fri, 24 Aug 2018 00:07:34 +0800 Message-Id: <20180823160743.45638-23-ming.huang@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180823160743.45638-1-ming.huang@linaro.org> References: <20180823160743.45638-1-ming.huang@linaro.org> Subject: [PATCH edk2-platforms v4 22/31] Platform/Hisilicon/D06: Add EarlyConfigPeim peim X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 23 Aug 2018 16:10:04 -0000 This peim configures SMMU,BSP,MN(Miscellaneous Node). Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Reviewed-by: Leif Lindholm --- Platform/Hisilicon/D06/D06.dsc | 1 + Platform/Hisilicon/D06/D06.fdf | 1 + Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf | 50 +++++++++ Silicon/Hisilicon/Include/Library/OemAddressMapLib.h | 2 + Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.c | 107 ++++++++++++++++++++ 5 files changed, 161 insertions(+) diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc index 5571028f42..3de09ea870 100644 --- a/Platform/Hisilicon/D06/D06.dsc +++ b/Platform/Hisilicon/D06/D06.dsc @@ -263,6 +263,7 @@ MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf Silicon/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf { diff --git a/Platform/Hisilicon/D06/D06.fdf b/Platform/Hisilicon/D06/D06.fdf index 184d5d4dcf..bd3ea47226 100644 --- a/Platform/Hisilicon/D06/D06.fdf +++ b/Platform/Hisilicon/D06/D06.fdf @@ -359,6 +359,7 @@ READ_LOCK_STATUS = TRUE INF ArmPkg/Drivers/CpuPei/CpuPei.inf INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf + INF Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf diff --git a/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf b/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf new file mode 100644 index 0000000000..8296ee02de --- /dev/null +++ b/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf @@ -0,0 +1,50 @@ +#/** @file +# +# Copyright (c) 2018, Hisilicon Limited. All rights reserved. +# Copyright (c) 2017, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = EarlyConfigPeimD06 + FILE_GUID = FB8C65EB-0199-40C3-A82B-029921A9E9B3 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = EarlyConfigEntry + +[Sources.common] + EarlyConfigPeimD06.c + +[Packages] + ArmPkg/ArmPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Hisilicon/HisiPkg.dec + +[LibraryClasses] + ArmLib + CacheMaintenanceLib + DebugLib + IoLib + PcdLib + PeimEntryPoint + PlatformSysCtrlLib + +[Pcd] + gHisiTokenSpaceGuid.PcdMailBoxAddress + gHisiTokenSpaceGuid.PcdPeriSubctrlAddress + gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable + +[Depex] +## As we will clean mailbox in this module, need to wait memory init complete + gEfiPeiMemoryDiscoveredPpiGuid diff --git a/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h b/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h index 332a79343f..b5de34f5fa 100644 --- a/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h +++ b/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h @@ -16,6 +16,8 @@ #ifndef _OEM_ADDRESS_MAP_LIB_H_ #define _OEM_ADDRESS_MAP_LIB_H_ +#include + typedef struct _DDRC_BASE_ID{ UINTN Base; UINTN Id; diff --git a/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.c b/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.c new file mode 100644 index 0000000000..0790f7941a --- /dev/null +++ b/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.c @@ -0,0 +1,107 @@ +/** @file +* +* Copyright (c) 2018, Hisilicon Limited. All rights reserved. +* Copyright (c) 2018, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PERI_SUBCTRL_BASE (0x40000000) +#define MDIO_SUBCTRL_BASE (0x60000000) +#define PCIE2_SUBCTRL_BASE (0xA0000000) +#define PCIE0_SUBCTRL_BASE (0xB0000000) +#define ALG_BASE (0xD0000000) + +#define SC_BROADCAST_EN_REG (0x16220) +#define SC_BROADCAST_SCL1_ADDR0_REG (0x16230) +#define SC_BROADCAST_SCL1_ADDR1_REG (0x16234) +#define SC_BROADCAST_SCL2_ADDR0_REG (0x16238) +#define SC_BROADCAST_SCL2_ADDR1_REG (0x1623C) +#define SC_BROADCAST_SCL3_ADDR0_REG (0x16240) +#define SC_BROADCAST_SCL3_ADDR1_REG (0x16244) +#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG (0x1000) +#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG (0x1010) +#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG (0x1014) +#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG (0x1018) +#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG (0x101C) +#define PCIE_SUBCTRL_SC_REMAP_CTRL_REG (0x1200) +#define SC_ITS_M3_INT_MUX_SEL_REG (0x21F0) +#define SC_TM_CLKEN0_REG (0x2050) + +#define SC_TM_CLKEN0_REG_VALUE (0x3) +#define SC_BROADCAST_EN_REG_VALUE (0x7) +#define SC_BROADCAST_SCLx_ADDRx_REG_VALUE0 (0x0) +#define SC_BROADCAST_SCLx_ADDRx_REG_VALUE1 (0x40016260) +#define SC_BROADCAST_SCLx_ADDRx_REG_VALUE2 (0x60016260) +#define SC_BROADCAST_SCLx_ADDRx_REG_VALUE3 (0x400) +#define SC_ITS_M3_INT_MUX_SEL_REG_VALUE (0x7) +#define PCIE_SUBCTRL_SC_REMAP_CTRL_REG_VALUE0 (0x0) +#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE0 (0x27) +#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE1 (0x2F) +#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE2 (0x77) +#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG_VALUE0 (0x178033) +#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG_VALUE0 (0x17003c) +#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE0 (0x15003d) +#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE1 (0x170035) +#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG_VALUE0 (0x16003e) + +STATIC +VOID +QResetAp ( + VOID + ) +{ + MmioWrite64 (FixedPcdGet64 (PcdMailBoxAddress), 0x0); + (VOID)WriteBackInvalidateDataCacheRange ( + (VOID *)FixedPcdGet64 (PcdMailBoxAddress), + sizeof (UINT64) + ); + + //SCCL A + if (!PcdGet64 (PcdTrustedFirmwareEnable)) { + StartupAp (); + } +} + + +EFI_STATUS +EFIAPI +EarlyConfigEntry ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + DEBUG ((DEBUG_INFO,"SMMU CONFIG.........")); + (VOID)SmmuConfigForBios (); + DEBUG ((DEBUG_INFO,"Done\n")); + + DEBUG ((DEBUG_INFO,"AP CONFIG.........")); + (VOID)QResetAp (); + DEBUG ((DEBUG_INFO,"Done\n")); + + DEBUG ((DEBUG_INFO,"MN CONFIG.........")); + (VOID)MN_CONFIG (); + DEBUG ((DEBUG_INFO,"Done\n")); + + return EFI_SUCCESS; +} + -- 2.18.0