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* [Patch][edk2-platforms/devel-IntelAtomProcessorE3900] LPDDR4 Change.
@ 2018-08-28  8:29 zwei4
  0 siblings, 0 replies; only message in thread
From: zwei4 @ 2018-08-28  8:29 UTC (permalink / raw)
  To: edk2-devel; +Cc: David Wei, Mike Wu, Mang Guo

Change MRC parameters in FSP-M UPD to enable different memory configurations.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: David Wei <david.wei@intel.com>
CC: Mike Wu  <mike.wu@intel.com>
CC: Mang Guo <mang.guo@intel.com>
---
 .../Board/UP2/BoardInitPreMem/BoardInitMiscs.c     | 145 ++++++++++++++++-----
 .../Board/UP2/BoardInitPreMem/PlatformId.c         |  59 +++++++++
 .../Board/UP2/BoardInitPreMem/PlatformId.h         |   7 +
 .../PlatformSetupDxe/SouthClusterConfig.vfi        |   4 +-
 4 files changed, 184 insertions(+), 31 deletions(-)

diff --git a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/BoardInitMiscs.c b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/BoardInitMiscs.c
index d5092c2490..b155830523 100644
--- a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/BoardInitMiscs.c
+++ b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/BoardInitMiscs.c
@@ -15,6 +15,7 @@
 
 #include "BoardInitMiscs.h"
 #include "MmrcData.h"
+#include "PlatformId.h"
 
 UPDATE_FSPM_UPD_FUNC mUp2UpdateFspmUpdPtr = Up2UpdateFspmUpd;
 DRAM_CREATE_POLICY_DEFAULTS_FUNC   mUp2DramCreatePolicyDefaultsPtr = Up2DramCreatePolicyDefaults;
@@ -43,6 +44,10 @@ Up2UpdateFspmUpd (
   BOOT_VARIABLE_NV_DATA          *BootVariableNvData;
   MRC_PARAMS_SAVE_RESTORE        *MrcParamsHob;
   BOOT_VARIABLE_NV_DATA          *BootVariableNvDataHob;
+  SYSTEM_CONFIGURATION            SystemConfiguration;
+  UINTN                           VariableSize;
+  EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariablePpi;
+  UINT8                           DdrId;
 
   Status = (*PeiServices)->LocatePpi (
                              PeiServices,
@@ -98,13 +103,6 @@ Up2UpdateFspmUpd (
     }
 
   }
-  //
-  // Override RankEnable settings for UP2
-  //
-  FspUpdRgn->FspmConfig.Ch0_RankEnable   = 1;
-  FspUpdRgn->FspmConfig.Ch1_RankEnable   = 1;
-  FspUpdRgn->FspmConfig.Ch2_RankEnable   = 0;
-  FspUpdRgn->FspmConfig.Ch3_RankEnable   = 0;
 
   DEBUG ((DEBUG_INFO, "UpdateFspmUpd - gEfiPlatformInfoGuid\n"));
   Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);
@@ -131,34 +129,97 @@ Up2UpdateFspmUpd (
   FspUpdRgn->FspmConfig.DIMM1SPDAddress = 0;
   FspUpdRgn->FspmConfig.DDR3LPageSize   = 0;
   FspUpdRgn->FspmConfig.DDR3LASR        = 0;
-
-  FspUpdRgn->FspmConfig.Ch0_RankEnable   = 1; // 
-  FspUpdRgn->FspmConfig.Ch0_DeviceWidth  = 1; 
-  FspUpdRgn->FspmConfig.Ch0_DramDensity  = 2;
-  FspUpdRgn->FspmConfig.Ch0_Option       = 3;
-
-  FspUpdRgn->FspmConfig.Ch1_RankEnable   = 1; 
-  FspUpdRgn->FspmConfig.Ch1_DeviceWidth  = 1; // x16
-  FspUpdRgn->FspmConfig.Ch1_DramDensity  = 2; // 8GB
-  FspUpdRgn->FspmConfig.Ch1_Option       = 3;
-
-  FspUpdRgn->FspmConfig.Ch2_RankEnable   = 0; // empty
-  FspUpdRgn->FspmConfig.Ch2_DeviceWidth  = 1;
-  FspUpdRgn->FspmConfig.Ch2_DramDensity  = 2;
-  FspUpdRgn->FspmConfig.Ch2_Option       = 3;
-
-  FspUpdRgn->FspmConfig.Ch3_RankEnable   = 0;
-  FspUpdRgn->FspmConfig.Ch3_DeviceWidth  = 1;
-  FspUpdRgn->FspmConfig.Ch3_DramDensity  = 2;
-  FspUpdRgn->FspmConfig.Ch3_Option       = 3;
-
   FspUpdRgn->FspmConfig.ChannelHashMask       = 0;
   FspUpdRgn->FspmConfig.SliceHashMask         = 0;
   FspUpdRgn->FspmConfig.ChannelsSlicesEnable  = 0;
   FspUpdRgn->FspmConfig.ScramblerSupport      = 1;
   FspUpdRgn->FspmConfig.InterleavedMode       = 0;
   FspUpdRgn->FspmConfig.MinRefRate2xEnable    = 0;
-  FspUpdRgn->FspmConfig.DualRankSupportEnable = 0;
+
+  //
+  // DDR_ID1    DDR_ID0  Memory
+  // GPIO_215   GPIO_214
+  //  0          0        2G
+  //  0          1        4G
+  //  1          0        8G
+  //
+  Status = Up2GetDdrId(PeiServices, &DdrId);
+  
+  if (DdrId == 0x00) { // 2GB, SK, Single Rank
+  
+    FspUpdRgn->FspmConfig.DualRankSupportEnable = 0;
+
+    FspUpdRgn->FspmConfig.Ch0_RankEnable   = 1;  
+    FspUpdRgn->FspmConfig.Ch0_DeviceWidth  = 1; 
+    FspUpdRgn->FspmConfig.Ch0_DramDensity  = 2;
+    FspUpdRgn->FspmConfig.Ch0_Option       = 3;
+
+    FspUpdRgn->FspmConfig.Ch1_RankEnable   = 1; 
+    FspUpdRgn->FspmConfig.Ch1_DeviceWidth  = 1; // x16
+    FspUpdRgn->FspmConfig.Ch1_DramDensity  = 2; // 8GB
+    FspUpdRgn->FspmConfig.Ch1_Option       = 3;
+ 
+    FspUpdRgn->FspmConfig.Ch2_RankEnable   = 0; // empty
+    FspUpdRgn->FspmConfig.Ch2_DeviceWidth  = 1;
+    FspUpdRgn->FspmConfig.Ch2_DramDensity  = 2;
+    FspUpdRgn->FspmConfig.Ch2_Option       = 3;
+
+    FspUpdRgn->FspmConfig.Ch3_RankEnable   = 0; // empty
+    FspUpdRgn->FspmConfig.Ch3_DeviceWidth  = 1;
+    FspUpdRgn->FspmConfig.Ch3_DramDensity  = 2;
+    FspUpdRgn->FspmConfig.Ch3_Option       = 3;
+    
+  }else if (DdrId == 0x01) { // 4GB, SK, Single Rank
+  
+    FspUpdRgn->FspmConfig.DualRankSupportEnable = 0;
+
+    FspUpdRgn->FspmConfig.Ch0_RankEnable   = 1; // 
+    FspUpdRgn->FspmConfig.Ch0_DeviceWidth  = 1; 
+    FspUpdRgn->FspmConfig.Ch0_DramDensity  = 2;
+    FspUpdRgn->FspmConfig.Ch0_Option       = 3;
+
+    FspUpdRgn->FspmConfig.Ch1_RankEnable   = 1; 
+    FspUpdRgn->FspmConfig.Ch1_DeviceWidth  = 1; // x16
+    FspUpdRgn->FspmConfig.Ch1_DramDensity  = 2; // 8GB
+    FspUpdRgn->FspmConfig.Ch1_Option       = 3;
+
+    FspUpdRgn->FspmConfig.Ch2_RankEnable   = 1; // empty
+    FspUpdRgn->FspmConfig.Ch2_DeviceWidth  = 1;
+    FspUpdRgn->FspmConfig.Ch2_DramDensity  = 2;
+    FspUpdRgn->FspmConfig.Ch2_Option       = 3;
+
+    FspUpdRgn->FspmConfig.Ch3_RankEnable   = 1;
+    FspUpdRgn->FspmConfig.Ch3_DeviceWidth  = 1;
+    FspUpdRgn->FspmConfig.Ch3_DramDensity  = 2;
+    FspUpdRgn->FspmConfig.Ch3_Option       = 3;
+    
+  }else if (DdrId == 0x02) { // 8GB, Micron, Dual Rank
+
+    //
+    // Micron #MT53B512M32D2NP-062 AIT:C) from Platfrom4 profile
+    //
+    FspUpdRgn->FspmConfig.DualRankSupportEnable = 1;
+
+    FspUpdRgn->FspmConfig.Ch0_RankEnable        = 0x03; // [0]: Rank 0 [1]: Rank 1
+    FspUpdRgn->FspmConfig.Ch0_DeviceWidth       = 0x01; // x16
+    FspUpdRgn->FspmConfig.Ch0_DramDensity       = 0x02; // 8Gb
+    FspUpdRgn->FspmConfig.Ch0_Option            = 0x03;
+
+    FspUpdRgn->FspmConfig.Ch1_RankEnable        = 0x03; // [0]: Rank 0 [1]: Rank 1
+    FspUpdRgn->FspmConfig.Ch1_DeviceWidth       = 0x01; // x16
+    FspUpdRgn->FspmConfig.Ch1_DramDensity       = 0x02; // 8Gb
+    FspUpdRgn->FspmConfig.Ch1_Option            = 0x03;
+
+    FspUpdRgn->FspmConfig.Ch2_RankEnable        = 0x03; // [0]: Rank 0 [1]: Rank 1
+    FspUpdRgn->FspmConfig.Ch2_DeviceWidth       = 0x01; // x16
+    FspUpdRgn->FspmConfig.Ch2_DramDensity       = 0x02; // 8Gb
+    FspUpdRgn->FspmConfig.Ch2_Option            = 0x03;
+
+    FspUpdRgn->FspmConfig.Ch3_RankEnable        = 0x03; // [0]: Rank 0 [1]: Rank 1
+    FspUpdRgn->FspmConfig.Ch3_DeviceWidth       = 0x01; // x16
+    FspUpdRgn->FspmConfig.Ch3_DramDensity       = 0x02; // 8Gb
+    FspUpdRgn->FspmConfig.Ch3_Option            = 0x03;
+  }
 
   //
   // Swizzling
@@ -170,6 +231,32 @@ Up2UpdateFspmUpd (
     CopyMem (&(FspUpdRgn->FspmConfig.Ch3_Bit_swizzling), ChSwizzle_UP2[3], DRAM_POLICY_NUMBER_BITS * sizeof(UINT8));
   }
 
+
+  //
+  // Enable or disable NPK based on DciEn
+  //
+  Status = PeiServicesLocatePpi (&gEfiPeiReadOnlyVariable2PpiGuid, 0, NULL, (VOID **) &VariablePpi);
+  if (!EFI_ERROR (Status)) {
+    VariableSize = sizeof (SYSTEM_CONFIGURATION);
+    Status = VariablePpi->GetVariable (
+                            VariablePpi,
+                            PLATFORM_SETUP_VARIABLE_NAME,
+                            &gEfiSetupVariableGuid,
+                            NULL,
+                            &VariableSize,
+                            &SystemConfiguration
+                            );
+    if (!EFI_ERROR (Status)) {
+      if (SystemConfiguration.DciEn == 0) {
+        FspUpdRgn->FspmConfig.NpkEn = 0;
+      } else if (SystemConfiguration.DciAutoDetect == 1) {
+        FspUpdRgn->FspmConfig.NpkEn = 3;
+      } else {
+        FspUpdRgn->FspmConfig.NpkEn = 1;
+      }
+    }
+  }
+
   return EFI_SUCCESS;
 }
 
diff --git a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/PlatformId.c b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/PlatformId.c
index 5708e05dae..20fdb6fb21 100644
--- a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/PlatformId.c
+++ b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/PlatformId.c
@@ -54,4 +54,63 @@ Up2GetEmbeddedBoardIdFabId(
   return EFI_SUCCESS;
 }
 
+EFI_STATUS
+EFIAPI
+Up2GetDdrId(
+  IN CONST EFI_PEI_SERVICES     **PeiServices,
+  OUT UINT8                     *DdrId
+  )
+{
+  BXT_CONF_PAD0   padConfg0;
+  BXT_CONF_PAD1   padConfg1;
+  IN UINT32       CommAndOffset;
+
+  //
+  // DDR_ID1    DDR_ID0  Memory
+  // GPIO_215   GPIO_214
+  //  0          0        2G
+  //  0          1        4G
+  //  1          0        8G
+  //
+  
+  //BXT_GPIO_PAD_CONF(L"GPIO_214 PMIC_BCUDISW2",   M0   ,    GPO   ,GPIO_D,  HI     ,   NA      ,Wake_Disabled, P_20K_L,    NA   ,    NA  ,NA        ,     NA,  GPIO_PADBAR+0x00D8,  NORTHWEST),//Feature: BT WAKE to Device Net in Sch: NGFF_BT_DEV_WAKE_N
+  //BXT_GPIO_PAD_CONF(L"GPIO_215 PMIC_BCUDISCRIT", M0   ,    GPO   ,GPIO_D,  HI     ,   NA      ,Wake_Disabled, P_20K_L,    NA   ,    NA  ,NA        ,     NA,  GPIO_PADBAR+0x00E0,  NORTHWEST),//Feature: RF_KILL_GPS       Net in Sch: RF_KILL_GPS_1P8_N
+
+  //
+  // DDR_ID0: GPIO_214
+  //
+  CommAndOffset = GetCommOffset (NORTHWEST, 0x00D8);
+  padConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);
+  padConfg0.r.PMode = 0;
+  padConfg0.r.GPIORxTxDis = 0x1;
+  GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCnf0);
+  //
+  // Set to Pull Up 20K
+  //
+  padConfg1.r.Term = 0xC;
+  GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCnf1);
+  
+  
+  //
+  // DDR_ID1: GPIO_215
+  //
+  CommAndOffset = GetCommOffset (NORTHWEST, 0x00E0);
+  padConfg0.padCnf0 = GpioPadRead (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET);
+  padConfg0.r.PMode = 0;
+  padConfg0.r.GPIORxTxDis = 0x1;
+  GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF0_OFFSET, padConfg0.padCnf0);
+  //Set to Pull Up 20K
+  padConfg1.r.Term = 0xC;
+  GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCnf1);
+ 
+
+  *DdrId = (UINT8) (((GpioPadRead (GetCommOffset (NORTHWEST, 0x00D8) + BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) | \
+                      (((GpioPadRead (GetCommOffset (NORTHWEST, 0x00E0) + BXT_GPIO_PAD_CONF0_OFFSET) & BIT1) >> 1) << 1));
+
+  DEBUG ((EFI_D_INFO,  "Ddr4Id is: %02X\n", *DdrId));
+
+
+  return EFI_SUCCESS;
+}
+
 
diff --git a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/PlatformId.h b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/PlatformId.h
index 8e98dcdce8..2288bc1e7d 100644
--- a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/PlatformId.h
+++ b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/PlatformId.h
@@ -70,5 +70,12 @@ Up2GetBomIdPss (
   OUT UINT8                     *BomIdPss
   );
 
+EFI_STATUS
+EFIAPI
+Up2GetDdrId(
+  IN CONST EFI_PEI_SERVICES     **PeiServices,
+  OUT UINT8                     *DdrId
+  );
+
 #endif
 
diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/SouthClusterConfig.vfi b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/SouthClusterConfig.vfi
index 9d2c9783eb..9738e4d912 100644
--- a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/SouthClusterConfig.vfi
+++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/SouthClusterConfig.vfi
@@ -163,8 +163,8 @@ form formid     = MISC_OPTIONS_FORM_ID,
   oneof varid = Setup.DciEn,
     prompt   = STRING_TOKEN(STR_DCI_HDCIEN_PROMPT),
     help     = STRING_TOKEN(STR_DCI_HDCIEN_HELP),
-    option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;
-    option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = RESET_REQUIRED;
+    option text = STRING_TOKEN(STR_DISABLE), value = 0, flags =  RESET_REQUIRED;
+    option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;
   endoneof;
 
   suppressif ideqval Setup.DciEn == 1;
-- 
2.14.1.windows.1



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