From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.65; helo=mga03.intel.com; envelope-from=ruiyu.ni@intel.com; receiver=edk2-devel@lists.01.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6BBD421BADAB2 for ; Wed, 29 Aug 2018 19:01:33 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Aug 2018 19:01:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,305,1531810800"; d="scan'208";a="84534464" Received: from ray-dev.ccr.corp.intel.com ([10.239.9.8]) by fmsmga004.fm.intel.com with ESMTP; 29 Aug 2018 19:01:32 -0700 From: Ruiyu Ni To: edk2-devel@lists.01.org Cc: Hao Wu , Andrew Fish Date: Thu, 30 Aug 2018 10:02:10 +0800 Message-Id: <20180830020213.148968-7-ruiyu.ni@intel.com> X-Mailer: git-send-email 2.16.1.windows.1 In-Reply-To: <20180830020213.148968-1-ruiyu.ni@intel.com> References: <20180830020213.148968-1-ruiyu.ni@intel.com> Subject: [PATCH v2 6/9] EmulatorPkg/AutoScanPei: Report the correct CPU address size X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 30 Aug 2018 02:01:33 -0000 REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1119 Today's implementation reports CPU address size as 36 through CPU HOB. But when WinHost is running at 64bit, the system memory might be allocated above 2^36. It causes system asserts when DxeCore code tries to find the corresponding GCD entry for a given valid address. The patch uses 57 as the CPU address size which is maximum linear address size when 5-level paging is enabled in host OS. Using 64 seems more proper and a one-time change even 6-level paging might be invented. But it causes CoreInitializeGcdServices() assertion on following code: Entry->EndAddress = LShiftU64 (1, SizeOfMemorySpace) - 1; Because LShiftU64 expects SizeOfMemorySpace < 64. So to be practical, I didn't report 64 and change CoreInitializeGcdServices(). Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni Cc: Hao Wu Cc: Andrew Fish --- EmulatorPkg/AutoScanPei/AutoScanPei.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/EmulatorPkg/AutoScanPei/AutoScanPei.c b/EmulatorPkg/AutoScanPei/AutoScanPei.c index 78a40db3a2..9316ea549b 100644 --- a/EmulatorPkg/AutoScanPei/AutoScanPei.c +++ b/EmulatorPkg/AutoScanPei/AutoScanPei.c @@ -1,6 +1,6 @@ /*++ @file -Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
Portions copyright (c) 2011, Apple Inc. All rights reserved. This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License @@ -101,9 +101,9 @@ Returns: } while (!EFI_ERROR (Status)); // - // Build the CPU hob with 36-bit addressing and 16-bits of IO space. + // Build the CPU hob with 57-bit addressing and 16-bits of IO space. // - BuildCpuHob (36, 16); + BuildCpuHob (57, 16); return Status; } -- 2.16.1.windows.1