From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::241; helo=mail-wm0-x241.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4D19221107831 for ; Fri, 31 Aug 2018 15:57:55 -0700 (PDT) Received: by mail-wm0-x241.google.com with SMTP id f21-v6so6519595wmc.5 for ; Fri, 31 Aug 2018 15:57:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=uXN3FJO9fe0TRK78mcW3hny83YfKZ6yERdBjWTzDzu8=; b=O1ePr/SiSqcZEnsQ3dES4BJk+LkdSj+ixbZMEuKWB3AG5NqEMIY+vscQ1md5Rnf/Xc bcMOK/OQxJujXMyuV+OYm/hAlyxb+fvfXhWibTU2Ge1M+VwKxRkznKsadrAMdXxdsCvU l2VB1wMd4Af6Nw/4uM01cv8m1eZy70FKmrLCc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=uXN3FJO9fe0TRK78mcW3hny83YfKZ6yERdBjWTzDzu8=; b=JpVVpBq9/uDT61BhjaztQxdfP5YiUsr88tZMTubk7C0QEp2GRxJHUkv0A+Fu+jxRpk OmEVCEGSxp/lyVk31I18UkDrJXdWJ2ZoL4EZ1VGcI+F1YWCvUxDad8I5znwn/cvRdoHz qh089qGge5nrws74R8F3ydiA6jOgFe2uxH5qAPe6vtjTs7WlWso0emRdh29qYMK6RHD0 mJDpjlldETzxvznSv7NBUJuqlvmalr9YxPoVEqFbiUTq39e9+rn3TrxJTgDLySx3IPew gVTZ5Hm9+5g2eZrL03UOoQMI54IRp7BQQfdrAi/VpLwjibfu9ypFRr5ZMqYnl9miIWsw UR2Q== X-Gm-Message-State: APzg51A0kD3koXfh0yaJckBihZfTLWtZgo0cnWAVEDUKKbDgEJkMsEp5 jxgNUOI/Tg1l+FmMOmHLFLyQBQ== X-Google-Smtp-Source: ANB0VdYMvgiY5uTHDbdJ3RtFep0XRRgpulPqujYvEayTNAsgQC6aLcqH4kgT5Dj1EY1CVR5B9z5BTA== X-Received: by 2002:a1c:2787:: with SMTP id n129-v6mr5809219wmn.101.1535756273073; Fri, 31 Aug 2018 15:57:53 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id m8-v6sm6810723wrn.72.2018.08.31.15.57.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 31 Aug 2018 15:57:52 -0700 (PDT) Date: Fri, 31 Aug 2018 23:57:50 +0100 From: Leif Lindholm To: Ming Huang Cc: linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org, ard.biesheuvel@linaro.org, michael.d.kinney@intel.com, lersek@redhat.com, guoheyi@huawei.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, john.garry@huawei.com, xinliang.liu@linaro.org, zhangfeng56@huawei.com Message-ID: <20180831225749.imng2rqecqiwnss7@bivouac.eciton.net> References: <20180831132710.23055-1-ming.huang@linaro.org> MIME-Version: 1.0 In-Reply-To: <20180831132710.23055-1-ming.huang@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms v5 00/28] Upload for D06 platform X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 31 Aug 2018 22:57:55 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hi Ming, Thanks for the quick turnaround. The difference since v4 is substantial. I think this is good to go - I spotted a couple of misplaced spaces and such, bit I think I'll let them slip. Will wait with pushing until Monday, when my head is hopefully a bit clearer. Have a great weekend, Leif On Fri, Aug 31, 2018 at 09:26:42PM +0800, Ming Huang wrote: > The major features of this patchset include: > 1 D06 source code; > 2 Unify some D0x modules; > > Change since v4: > 1 build on every commit: > Squash "Add PciPlatformLib" to "Add several base file for D06"; > Reorder OemMiscLibD06 before "Add edk2-non-osi components for D06"; > Move some mudules after "Add edk2-non-osi components for D06"; > Move gOemConfigGuid to "Stop watchdog"; > 2 Delete needless SnpDxe; > 3 Reorder "Unify HisiAcpiPlatformDxe"; > 4 Modify Signed-off-by and add Reviewed-by; > 5 Modify other comments in v4; > > Code can also be found in github: https://github.com/hisilicon/OpenPlatformPkg.git > branch: d06-platform-v5 > > > Heyi Guo (3): > Hisilicon/D06: Add Debug Serial Port Init Driver > Hisilicon/Hi1620: Add ACPI PPTT table > Platform/Hisilicon/D06: Enable ACPI PPTT > > Luqi Jiang (1): > Hisilicon/D06: add apei driver > > Ming Huang (19): > Hisilicon/D0x: Modify PcdBootManagerMenuFile for build > Silicon/Hisilicon/Acpi: Unify HisiAcpiPlatformDxe > Hisilicon/D06: Add several base file for D06 > Platform/Hisilicon/D06: Add M41T83RealTimeClockLib > Hisilicon/D06: Add OemMiscLibD06 > Platform/Hisilicon/D06: Add edk2-non-osi components for D06 > Hisilicon/D06: Add some modules > Silicon/Hisilicon/D06: Wait for all disk ready > Hisilicon/D06: Add ACPI Tables for D06 > Silicon/Hisilicon/D06: Stop watchdog > Platform/Hisilicon/D06: Add OemNicLib > Platform/Hisilicon/D06: Add OemNicConfig2P Driver > Platform/Hisilicon/D06: Add EarlyConfigPeim peim > Platform/Hisilicon/D06: Add PciHostBridgeLib > Platform/Hisilicon/D06: Add capsule upgrade support > Silicon/Hisilicon: Add I2C Bus Exception handle function > Silicon/Hisilicon/Setup: Support SPCR table switch > Silicon/Hisilicon/setup: Enable/disable SMMU > Platform/Hisilicon/D0x: Update version string to 18.08 > > Sun Yuanchen (2): > Silicon/Hisilicon/D0x: Move RAS macro to PlatformArch.h > Hisilicon/D0x: Update SMBIOS type9 info > > Yang XinYi (2): > Hisilicon/D06: Add Hi1620OemConfigUiLib > Silicon/Hisilicon/Hi1620/Setup: Add Setup Item "EnableGOP" > > ZhenYao (1): > Silicon/Hisilicon: Modify for disable slave core clock. > > Platform/Hisilicon/D06/D06.dec | 29 + > Silicon/Hisilicon/Hi1620/Hi1620.dec | 23 + > Silicon/Hisilicon/HisiPkg.dec | 1 + > Platform/Hisilicon/D03/D03.dsc | 4 +- > Platform/Hisilicon/D05/D05.dsc | 4 +- > Platform/Hisilicon/D06/D06.dsc | 489 ++++ > Platform/Hisilicon/D06/D06.fdf | 441 ++++ > .../OemMiscLib2P/OemMiscLib2PHi1610.inf | 1 + > .../Library/OemMiscLibD05/OemMiscLibD05.inf | 1 + > .../OemNicConfig2PHi1620/OemNicConfig2P.inf | 43 + > .../SystemFirmwareDescriptor.inf | 50 + > .../EarlyConfigPeim/EarlyConfigPeimD06.inf | 50 + > .../Library/OemMiscLibD06/OemMiscLibD06.inf | 50 + > .../D06/Library/OemNicLib/OemNicLib.inf | 35 + > .../PciHostBridgeLib/PciHostBridgeLib.inf | 36 + > .../HisiAcpiPlatformDxe/AcpiPlatformDxe.inf | 3 +- > .../Hisilicon/Hi1620/Drivers/Apei/Apei.inf | 59 + > .../Pl011DebugSerialPortInitDxe.inf | 48 + > .../Hi1620AcpiTables/AcpiTablesHi1620.inf | 60 + > .../Hi1620OemConfigUiLib/OemConfigUiLib.inf | 68 + > .../Hi1620PciPlatformLib.inf | 30 + > Silicon/Hisilicon/Hi1620/Pptt/Pptt.inf | 48 + > .../M41T83RealTimeClockLib.inf | 46 + > .../PlatformBootManagerLib.inf | 5 + > .../OemNicConfig2PHi1620/OemNicConfig.h | 25 + > .../Hisilicon/D06/Include/Library/CpldD06.h | 39 + > .../Hisilicon/Hi1610/Include/PlatformArch.h | 15 +- > .../Hisilicon/Hi1616/Include/PlatformArch.h | 12 + > Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.h | 41 + > .../Hisilicon/Hi1620/Drivers/Apei/Bert/Bert.h | 43 + > .../Hisilicon/Hi1620/Drivers/Apei/Einj/Einj.h | 146 ++ > .../Hi1620/Drivers/Apei/ErrorSource/Ghes.h | 110 + > .../Hisilicon/Hi1620/Drivers/Apei/Erst/Erst.h | 140 ++ > .../Hisilicon/Hi1620/Drivers/Apei/Hest/Hest.h | 59 + > .../Hi1620/Drivers/Apei/OemApeiHi1620.h | 43 + > .../Hi1620/Hi1620AcpiTables/Hi1620Platform.h | 27 + > .../Hi1620/Hi1620OemConfigUiLib/OemConfig.h | 142 ++ > .../Hi1620/Hi1620OemConfigUiLib/OemConfigUi.h | 64 + > .../Hi1620/Include/Library/SerdesLib.h | 85 + > .../Hisilicon/Hi1620/Include/PlatformArch.h | 67 + > Silicon/Hisilicon/Hi1620/Pptt/Pptt.h | 68 + > .../Hisilicon/Include/Library/AcpiNextLib.h | 31 +- > .../Hisilicon/Include/Library/IpmiCmdLib.h | 16 + > .../Include/Library/OemAddressMapLib.h | 8 + > .../Hisilicon/Include/Library/OemConfigData.h | 84 + > .../Hisilicon/Include/Library/OemMiscLib.h | 7 +- > Silicon/Hisilicon/Include/Library/OemNicLib.h | 57 + > .../Include/Library/PlatformSysCtrlLib.h | 6 + > .../M41T83RealTimeClock.h | 158 ++ > .../Hi1620OemConfigUiLib/OemConfigVfr.vfr | 89 + > .../Library/OemMiscLib2P/OemMiscLib2PHi1610.c | 32 + > .../D05/Library/OemMiscLibD05/OemMiscLibD05.c | 27 +- > .../OemNicConfig2PHi1620/OemNicConfig2P.c | 71 + > .../SystemFirmwareDescriptorPei.c | 70 + > .../D06/EarlyConfigPeim/EarlyConfigPeimD06.c | 107 + > .../Library/OemMiscLibD06/BoardFeatureD06.c | 432 ++++ > .../D06/Library/OemMiscLibD06/OemMiscLibD06.c | 209 ++ > .../D06/Library/OemNicLib/OemNicLib.c | 569 +++++ > .../PciHostBridgeLib/PciHostBridgeLib.c | 635 ++++++ > .../HisiAcpiPlatformDxe/UpdateAcpiTable.c | 91 +- > .../Smbios/AddSmbiosType9/AddSmbiosType9.c | 14 +- > Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.c | 108 + > .../Hisilicon/Hi1620/Drivers/Apei/Bert/Bert.c | 91 + > .../Hisilicon/Hi1620/Drivers/Apei/Einj/Einj.c | 349 +++ > .../Hi1620/Drivers/Apei/ErrorSource/Ghes.c | 330 +++ > .../Hisilicon/Hi1620/Drivers/Apei/Erst/Erst.c | 374 ++++ > .../Hisilicon/Hi1620/Drivers/Apei/Hest/Hest.c | 118 + > .../Hi1620/Drivers/Apei/OemApeiHi1620.c | 337 +++ > .../Pl011DebugSerialPortInitDxe.c | 64 + > .../Hi1620/Hi1620OemConfigUiLib/OemConfig.c | 363 +++ > .../Hi1620PciPlatformLib.c | 67 + > Silicon/Hisilicon/Hi1620/Pptt/Pptt.c | 543 +++++ > .../M41T83RealTimeClockLib.c | 559 +++++ > .../PlatformBootManagerLib/PlatformBm.c | 59 + > .../SystemFirmwareUpdateConfig.ini | 46 + > .../SystemFirmwareDescriptor.aslc | 81 + > .../OemMiscLibD06/BoardFeatureD06Strings.uni | 66 + > .../Hi1620/Hi1620AcpiTables/Dsdt/CPU.asl | 409 ++++ > .../Hi1620/Hi1620AcpiTables/Dsdt/Com.asl | 30 + > .../Hi1620AcpiTables/Dsdt/DsdtHi1620.asl | 35 + > .../Hi1620AcpiTables/Dsdt/Hi1620Apei.asl | 93 + > .../Hi1620AcpiTables/Dsdt/Hi1620Ged.asl | 58 + > .../Hi1620AcpiTables/Dsdt/Hi1620Mbig.asl | 1459 ++++++++++++ > .../Hi1620AcpiTables/Dsdt/Hi1620Mctp.asl | 41 + > .../Hi1620AcpiTables/Dsdt/Hi1620Pci.asl | 1216 ++++++++++ > .../Hi1620AcpiTables/Dsdt/Hi1620Power.asl | 28 + > .../Hi1620AcpiTables/Dsdt/Hi1620Rde.asl | 47 + > .../Hi1620AcpiTables/Dsdt/Hi1620Sec.asl | 57 + > .../Dsdt/Hi1620Socip4_i2c100k.asl | 249 +++ > .../Dsdt/Hi1620Socip4_i2c400k.asl | 249 +++ > .../Hi1620AcpiTables/Dsdt/LpcUart_clk.asl | 49 + > .../Hi1620AcpiTables/Dsdt/Pv680UncorePmu.asl | 1658 ++++++++++++++ > .../Hi1620/Hi1620AcpiTables/Dsdt/ipmi.asl | 49 + > .../Hi1620/Hi1620AcpiTables/Facs.aslc | 67 + > .../Hi1620/Hi1620AcpiTables/Fadt.aslc | 91 + > .../Hi1620/Hi1620AcpiTables/Gtdt.aslc | 86 + > .../Hi1620/Hi1620AcpiTables/Hi1620Dbg2.aslc | 86 + > .../Hi1620/Hi1620AcpiTables/Hi1620Iort.asl | 1989 +++++++++++++++++ > .../Hi1620AcpiTables/Hi1620IortNoSmmu.asl | 1736 ++++++++++++++ > .../Hi1620/Hi1620AcpiTables/Hi1620Mcfg.aslc | 64 + > .../Hi1620/Hi1620AcpiTables/Hi1620Slit.aslc | 64 + > .../Hi1620/Hi1620AcpiTables/Hi1620Spcr.aslc | 81 + > .../Hi1620/Hi1620AcpiTables/Hi1620Srat.aslc | 166 ++ > .../Hi1620/Hi1620AcpiTables/MadtHi1620.aslc | 375 ++++ > .../Hi1620OemConfigUiLib/MemoryConfig.hfr | 154 ++ > .../Hi1620OemConfigUiLib/MemoryConfig.uni | 103 + > .../Hi1620OemConfigUiLib/MiscConfig.hfr | 41 + > .../Hi1620OemConfigUiLib/MiscConfig.uni | 27 + > .../Hi1620OemConfigUiLib/OemConfigUiLib.uni | 24 + > .../OemConfigUiLibStrings.uni | 42 + > .../Hi1620OemConfigUiLib/PcieConfig.hfr | 219 ++ > .../PcieConfigStrings.uni | 111 + > .../Hi1620OemConfigUiLib/PciePortConfig.hfr | 167 ++ > .../Hi1620/Hi1620OemConfigUiLib/RasConfig.hfr | 172 ++ > .../Hi1620/Hi1620OemConfigUiLib/RasConfig.uni | 85 + > .../Hi1620OemConfigUiLib/iBMCConfig.hfr | 81 + > .../Hi1620OemConfigUiLib/iBMCConfig.uni | 34 + > 117 files changed, 20778 insertions(+), 32 deletions(-) > create mode 100644 Platform/Hisilicon/D06/D06.dec > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620.dec > create mode 100644 Platform/Hisilicon/D06/D06.dsc > create mode 100644 Platform/Hisilicon/D06/D06.fdf > create mode 100644 Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig2P.inf > create mode 100644 Platform/Hisilicon/D06/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf > create mode 100644 Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf > create mode 100644 Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf > create mode 100644 Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.inf > create mode 100644 Platform/Hisilicon/D06/Library/PciHostBridgeLib/PciHostBridgeLib.inf > create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.inf > create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.inf > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620.inf > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUiLib.inf > create mode 100644 Silicon/Hisilicon/Hi1620/Library/Hi1620PciPlatformLib/Hi1620PciPlatformLib.inf > create mode 100644 Silicon/Hisilicon/Hi1620/Pptt/Pptt.inf > create mode 100644 Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.inf > create mode 100644 Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig.h > create mode 100644 Platform/Hisilicon/D06/Include/Library/CpldD06.h > create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.h > create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Bert/Bert.h > create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Einj/Einj.h > create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/ErrorSource/Ghes.h > create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Erst/Erst.h > create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Hest/Hest.h > create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/OemApeiHi1620.h > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Platform.h > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.h > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUi.h > create mode 100644 Silicon/Hisilicon/Hi1620/Include/Library/SerdesLib.h > create mode 100644 Silicon/Hisilicon/Hi1620/Include/PlatformArch.h > create mode 100644 Silicon/Hisilicon/Hi1620/Pptt/Pptt.h > create mode 100644 Silicon/Hisilicon/Include/Library/OemConfigData.h > create mode 100644 Silicon/Hisilicon/Include/Library/OemNicLib.h > create mode 100644 Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClock.h > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr > create mode 100644 Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig2P.c > create mode 100644 Platform/Hisilicon/D06/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c > create mode 100644 Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.c > create mode 100644 Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c > create mode 100644 Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c > create mode 100644 Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.c > create mode 100644 Platform/Hisilicon/D06/Library/PciHostBridgeLib/PciHostBridgeLib.c > create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.c > create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Bert/Bert.c > create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Einj/Einj.c > create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/ErrorSource/Ghes.c > create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Erst/Erst.c > create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Hest/Hest.c > create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/OemApeiHi1620.c > create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.c > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c > create mode 100644 Silicon/Hisilicon/Hi1620/Library/Hi1620PciPlatformLib/Hi1620PciPlatformLib.c > create mode 100644 Silicon/Hisilicon/Hi1620/Pptt/Pptt.c > create mode 100644 Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.c > create mode 100644 Platform/Hisilicon/D06/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini > create mode 100644 Platform/Hisilicon/D06/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc > create mode 100644 Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06Strings.uni > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/CPU.asl > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Com.asl > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/DsdtHi1620.asl > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Apei.asl > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Ged.asl > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mbig.asl > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mctp.asl > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Power.asl > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Rde.asl > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Sec.asl > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Socip4_i2c100k.asl > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Socip4_i2c400k.asl > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/LpcUart_clk.asl > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Pv680UncorePmu.asl > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/ipmi.asl > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Facs.aslc > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Fadt.aslc > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Gtdt.aslc > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Dbg2.aslc > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Iort.asl > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620IortNoSmmu.asl > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Mcfg.aslc > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Slit.aslc > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Spcr.aslc > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Srat.aslc > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/MadtHi1620.aslc > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MemoryConfig.hfr > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MemoryConfig.uni > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MiscConfig.hfr > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MiscConfig.uni > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUiLib.uni > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUiLibStrings.uni > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PciePortConfig.hfr > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/RasConfig.hfr > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/RasConfig.uni > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/iBMCConfig.hfr > create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/iBMCConfig.uni > > -- > 2.18.0 >