From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Permerror (SPF Permanent Error: Two or more type TXT spf records found.) identity=mailfrom; client-ip=134.134.136.100; helo=mga07.intel.com; envelope-from=jian.j.wang@intel.com; receiver=edk2-devel@lists.01.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1BA94210FCF56 for ; Sun, 2 Sep 2018 20:15:54 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 02 Sep 2018 20:15:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,323,1531810800"; d="scan'208";a="259323754" Received: from shwdeopenpsi777.ccr.corp.intel.com ([10.239.158.27]) by fmsmga005.fm.intel.com with ESMTP; 02 Sep 2018 20:15:52 -0700 From: Jian J Wang To: edk2-devel@lists.01.org Cc: Star Zeng , Ruiyu Ni , Jiewen Yao , "Ware, Ryan R" Date: Mon, 3 Sep 2018 11:15:47 +0800 Message-Id: <20180903031550.4440-2-jian.j.wang@intel.com> X-Mailer: git-send-email 2.16.2.windows.1 In-Reply-To: <20180903031550.4440-1-jian.j.wang@intel.com> References: <20180903031550.4440-1-jian.j.wang@intel.com> Subject: [PATCH 1/4] MdeModulePkg/DxeIpl: disable paging before creating new page table X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 03 Sep 2018 03:15:54 -0000 PEI Stack Guard needs to enable paging before DxeIpl. This might cause #GP in the transition from 32-bit PEI to 64-bit DXE due to the code trying to write CR3 register with PML4 page table while the processor is enabled with PAE paging. Simply disabling paging before updating CR3 can solve this conflict. There's no such issue for 64-bit PEI so this change applies only to 32-bit code. Cc: Star Zeng Cc: Ruiyu Ni Cc: Jiewen Yao Cc: "Ware, Ryan R" Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang --- MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c b/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c index 8a939b6c24..d28baa3615 100644 --- a/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c +++ b/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c @@ -325,6 +325,11 @@ HandOffToDxeCore ( PERF_EVENT_SIGNAL_END (gEndOfPeiSignalPpi.Guid); ASSERT_EFI_ERROR (Status); + // + // Paging might be already enabled. To avoid conflict configuration, + // disable paging first anyway. + // + AsmWriteCr0 (AsmReadCr0 () & (~BIT31)); AsmWriteCr3 (PageTables); // @@ -445,6 +450,11 @@ HandOffToDxeCore ( ASSERT_EFI_ERROR (Status); if (BuildPageTablesIa32Pae) { + // + // Paging might be already enabled. To avoid conflict configuration, + // disable paging first anyway. + // + AsmWriteCr0 (AsmReadCr0 () & (~BIT31)); AsmWriteCr3 (PageTables); // // Set Physical Address Extension (bit 5 of CR4). -- 2.16.2.windows.1