From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.24; helo=mga09.intel.com; envelope-from=eric.dong@intel.com; receiver=edk2-devel@lists.01.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D28562113A11F for ; Mon, 17 Sep 2018 18:44:20 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Sep 2018 18:44:20 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,387,1531810800"; d="scan'208";a="91415066" Received: from ydong10-win10.ccr.corp.intel.com ([10.239.9.125]) by orsmga001.jf.intel.com with ESMTP; 17 Sep 2018 18:44:09 -0700 From: Eric Dong To: edk2-devel@lists.01.org Cc: Michael D Kinney , Ruiyu Ni , Laszlo Ersek Date: Tue, 18 Sep 2018 09:43:30 +0800 Message-Id: <20180918014330.28336-15-eric.dong@intel.com> X-Mailer: git-send-email 2.15.0.windows.1 In-Reply-To: <20180918014330.28336-1-eric.dong@intel.com> References: <20180918014330.28336-1-eric.dong@intel.com> Subject: [Patch 14/14] UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h: Change structure definition. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 18 Sep 2018 01:44:21 -0000 Changes includes: 1. Update MSR structure definition, change some reserved fields to useful fields: 1. MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER 2. MSR_XEON_PHI_SMM_MCA_CAP_REGISTER 2. For MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER structure, it expand the field range. Old definition like below: typedef union { /// /// Individual bit fields /// struct { /// /// [Bits 15:0] LVL_2 Base Address (R/W). /// UINT32 Lvl2Base:16; /// /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the /// maximum C-State code name to be included when IO read to MWAIT /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 100b - C4 /// is the max C-State to include 110b - C6 is the max C-State to include. /// UINT32 CStateRange:3; UINT32 Reserved1:13; UINT32 Reserved2:32; } Bits; /// /// All bit fields as a 32-bit value /// UINT32 Uint32; /// /// All bit fields as a 64-bit value /// UINT64 Uint64; } MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER; This patch make below changes for this data structure, it expand "CStateRange" field width. old one: UINT32 CStateRange:3; UINT32 Reserved1:13; new one: UINT32 CStateRange:7; UINT32 Reserved1:9; Cc: Michael D Kinney Cc: Ruiyu Ni Cc: Laszlo Ersek Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong --- UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h | 53 ++++++++++++++++++++++------ 1 file changed, 42 insertions(+), 11 deletions(-) diff --git a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h index da74c2402c..77bd310d83 100644 --- a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h +++ b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h @@ -278,8 +278,26 @@ typedef union { /// [Bit 15] CFG Lock (R/WO). /// UINT32 CFGLock:1; - UINT32 Reserved3:16; - UINT32 Reserved4:32; + UINT32 Reserved3:10; + /// + /// [Bit 26] C1 State Auto Demotion Enable (R/W) When set, the processor + /// will conditionally demote C3/C6/C7 requests to C1 based on uncore + /// auto-demote information. + /// + UINT32 C1StateAutoDemotionEnable:1; + UINT32 Reserved4:1; + /// + /// [Bit 28] C1 State Auto Undemotion Enable (R/W) When set, enables + /// Undemotion from Demoted C1. + /// + UINT32 C1StateAutoUndemotionEnable:1; + /// + /// [Bit 29] PKG C-State Auto Demotion Enable (R/W) When set, enables + /// Package C state demotion. + /// + UINT32 PKGC_StateAutoDemotionEnable:1; + UINT32 Reserved5:2; + UINT32 Reserved6:32; } Bits; /// /// All bit fields as a 32-bit value @@ -325,13 +343,12 @@ typedef union { /// UINT32 Lvl2Base:16; /// - /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the - /// maximum C-State code name to be included when IO read to MWAIT - /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 100b - C4 - /// is the max C-State to include 110b - C6 is the max C-State to include. + /// [Bits 22:16] C-State Range (R/W) The IO-port block size in which + /// IO-redirection will be executed (0-127). Should be programmed based on + /// the number of LVLx registers existing in the chipset. /// - UINT32 CStateRange:3; - UINT32 Reserved1:13; + UINT32 CStateRange:7; + UINT32 Reserved1:9; UINT32 Reserved2:32; } Bits; /// @@ -477,8 +494,22 @@ typedef union { /// Individual bit fields /// struct { - UINT32 Reserved1:32; - UINT32 Reserved2:26; + /// + /// [Bits 31:0] Bank Support (SMM-RO) One bit per MCA bank. If the bit is + /// set, that bank supports Enhanced MCA (Default all 0; does not support + /// EMCA). + /// + UINT32 BankSupport:32; + UINT32 Reserved1:24; + /// + /// [Bit 56] Targeted SMI (SMM-RO) Set if targeted SMI is supported. + /// + UINT32 TargetedSMI:1; + /// + /// [Bit 57] SMM_CPU_SVRSTR (SMM-RO) Set if SMM SRAM save/restore feature + /// is supported. + /// + UINT32 SMM_CPU_SVRSTR:1; /// /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the /// SMM code access restriction is supported and a host-space interface @@ -491,7 +522,7 @@ typedef union { /// available to SMM handler. /// UINT32 Long_Flow_Indication:1; - UINT32 Reserved3:4; + UINT32 Reserved2:4; } Bits; /// /// All bit fields as a 64-bit value -- 2.15.0.windows.1