From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.31; helo=mga06.intel.com; envelope-from=eric.dong@intel.com; receiver=edk2-devel@lists.01.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 615E32113A117 for ; Mon, 17 Sep 2018 18:44:05 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Sep 2018 18:44:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,387,1531810800"; d="scan'208";a="91415026" Received: from ydong10-win10.ccr.corp.intel.com ([10.239.9.125]) by orsmga001.jf.intel.com with ESMTP; 17 Sep 2018 18:44:01 -0700 From: Eric Dong To: edk2-devel@lists.01.org Cc: Michael D Kinney , Ruiyu Ni , Laszlo Ersek Date: Tue, 18 Sep 2018 09:43:24 +0800 Message-Id: <20180918014330.28336-9-eric.dong@intel.com> X-Mailer: git-send-email 2.15.0.windows.1 In-Reply-To: <20180918014330.28336-1-eric.dong@intel.com> References: <20180918014330.28336-1-eric.dong@intel.com> Subject: [Patch 08/14] UefiCpuPkg/Include/Register/ArchitecturalMsr.h: Change structure definition. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 18 Sep 2018 01:44:05 -0000 Changes includes: 1. Change fields which is reserved in old version: MSR_IA32_RTIT_CTL_REGISTER Cc: Michael D Kinney Cc: Ruiyu Ni Cc: Laszlo Ersek Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong --- UefiCpuPkg/Include/Register/ArchitecturalMsr.h | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h index b467ffaf26..312cbaf3da 100644 --- a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h +++ b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h @@ -4647,7 +4647,14 @@ typedef union { /// [Bit 3] User. /// UINT32 User:1; - UINT32 Reserved1:2; + /// + /// [Bit 4] PwrEvtEn. + /// + UINT32 PwrEvtEn:1; + /// + /// [Bit 5] FUPonPTW. + /// + UINT32 FUPonPTW:1; /// /// [Bit 6] FabricEn. If (CPUID.(EAX=07H, ECX=0):ECX[3] = 1). /// @@ -4672,7 +4679,10 @@ typedef union { /// [Bit 11] DisRETC. /// UINT32 DisRETC:1; - UINT32 Reserved2:1; + /// + /// [Bit 12] PTWEn. + /// + UINT32 PTWEn:1; /// /// [Bit 13] BranchEn. /// @@ -4681,17 +4691,17 @@ typedef union { /// [Bits 17:14] MTCFreq. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1). /// UINT32 MTCFreq:4; - UINT32 Reserved3:1; + UINT32 Reserved1:1; /// /// [Bits 22:19] CYCThresh. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1). /// UINT32 CYCThresh:4; - UINT32 Reserved4:1; + UINT32 Reserved2:1; /// /// [Bits 27:24] PSBFreq. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1). /// UINT32 PSBFreq:4; - UINT32 Reserved5:4; + UINT32 Reserved3:4; /// /// [Bits 35:32] ADDR0_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 0). /// @@ -4708,7 +4718,7 @@ typedef union { /// [Bits 47:44] ADDR3_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 3). /// UINT32 ADDR3_CFG:4; - UINT32 Reserved6:16; + UINT32 Reserved4:16; } Bits; /// /// All bit fields as a 64-bit value -- 2.15.0.windows.1