From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.126; helo=mga18.intel.com; envelope-from=ruiyu.ni@intel.com; receiver=edk2-devel@lists.01.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 759112114B135 for ; Fri, 21 Sep 2018 00:24:48 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Sep 2018 00:24:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,284,1534834800"; d="scan'208";a="72593621" Received: from ray-dev.ccr.corp.intel.com ([10.239.9.8]) by fmsmga008.fm.intel.com with ESMTP; 21 Sep 2018 00:24:47 -0700 From: Ruiyu Ni To: edk2-devel@lists.01.org Cc: Star Zeng , Kirkendall, Garrett Date: Fri, 21 Sep 2018 15:25:38 +0800 Message-Id: <20180921072539.268068-3-ruiyu.ni@intel.com> X-Mailer: git-send-email 2.16.1.windows.1 In-Reply-To: <20180921072539.268068-1-ruiyu.ni@intel.com> References: <20180921072539.268068-1-ruiyu.ni@intel.com> Subject: [PATCH 2/3] MdeModulePkg/PciHostBridge: Fix a bug that prevents PMEM access X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 21 Sep 2018 07:24:48 -0000 REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1196 RootBridgeIoCheckParameter() verifies that the requested MMIO access can fit in any of the MEM/PMEM 32/64 ranges. But today's logic somehow only checks the requested access against MEM 32/64 ranges. It should also check the requested access against PMEM 32/64 ranges. The patch fixes this issue. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni Cc: Star Zeng Cc: Kirkendall, Garrett --- MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c index 0b6b56f846..f6234b5d11 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c @@ -411,12 +411,18 @@ RootBridgeIoCheckParameter ( // By comparing the Address against Limit we know which range to be used // for checking // - if (Address + Length <= RootBridge->Mem.Limit + 1) { - Base = RootBridge->Mem.Base; + if ((Address >= RootBridge->Mem.Base) && (Address + Length <= RootBridge->Mem.Limit + 1)) { + Base = RootBridge->Mem.Base; Limit = RootBridge->Mem.Limit; - } else { - Base = RootBridge->MemAbove4G.Base; + } else if ((Address >= RootBridge->PMem.Base) && (Address + Length <= RootBridge->PMem.Limit + 1)) { + Base = RootBridge->PMem.Base; + Limit = RootBridge->PMem.Limit; + } else if ((Address >= RootBridge->MemAbove4G.Base) && (Address + Length <= RootBridge->MemAbove4G.Limit + 1)) { + Base = RootBridge->MemAbove4G.Base; Limit = RootBridge->MemAbove4G.Limit; + } else { + Base = RootBridge->PMemAbove4G.Base; + Limit = RootBridge->PMemAbove4G.Limit; } } else { PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &Address; -- 2.16.1.windows.1