From: Ruiyu Ni <ruiyu.ni@intel.com>
To: edk2-devel@lists.01.org
Cc: Star Zeng <star.zeng@intel.com>
Subject: [PATCH 3/3] MdeModulePkg/PciHostBridge: Add RESOURCE_VALID() to simplify code
Date: Fri, 21 Sep 2018 15:25:39 +0800 [thread overview]
Message-ID: <20180921072539.268068-4-ruiyu.ni@intel.com> (raw)
In-Reply-To: <20180921072539.268068-1-ruiyu.ni@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
---
.../Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 26 ++++++++++------------
1 file changed, 12 insertions(+), 14 deletions(-)
diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
index f6234b5d11..916709e276 100644
--- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
+++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -21,6 +21,8 @@ extern EDKII_IOMMU_PROTOCOL *mIoMmuProtocol;
#define NO_MAPPING (VOID *) (UINTN) -1
+#define RESOURCE_VALID(R) ((R).Base <= (R).Limit)
+
//
// Lookup table for increment values based on transfer widths
//
@@ -122,25 +124,25 @@ CreateRootBridge (
//
// Make sure Mem and MemAbove4G apertures are valid
//
- if (Bridge->Mem.Base <= Bridge->Mem.Limit) {
+ if (RESOURCE_VALID (Bridge->Mem)) {
ASSERT (Bridge->Mem.Limit < SIZE_4GB);
if (Bridge->Mem.Limit >= SIZE_4GB) {
return NULL;
}
}
- if (Bridge->MemAbove4G.Base <= Bridge->MemAbove4G.Limit) {
+ if (RESOURCE_VALID (Bridge->MemAbove4G)) {
ASSERT (Bridge->MemAbove4G.Base >= SIZE_4GB);
if (Bridge->MemAbove4G.Base < SIZE_4GB) {
return NULL;
}
}
- if (Bridge->PMem.Base <= Bridge->PMem.Limit) {
+ if (RESOURCE_VALID (Bridge->PMem)) {
ASSERT (Bridge->PMem.Limit < SIZE_4GB);
if (Bridge->PMem.Limit >= SIZE_4GB) {
return NULL;
}
}
- if (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit) {
+ if (RESOURCE_VALID (Bridge->PMemAbove4G)) {
ASSERT (Bridge->PMemAbove4G.Base >= SIZE_4GB);
if (Bridge->PMemAbove4G.Base < SIZE_4GB) {
return NULL;
@@ -157,11 +159,9 @@ CreateRootBridge (
// support separate windows for Non-prefetchable and Prefetchable
// memory.
//
- ASSERT (Bridge->PMem.Base > Bridge->PMem.Limit);
- ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit);
- if ((Bridge->PMem.Base <= Bridge->PMem.Limit) ||
- (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit)
- ) {
+ ASSERT (!RESOURCE_VALID (Bridge->PMem));
+ ASSERT (!RESOURCE_VALID (Bridge->PMemAbove4G));
+ if (RESOURCE_VALID (Bridge->PMem) || RESOURCE_VALID (Bridge->PMemAbove4G)) {
return NULL;
}
}
@@ -171,11 +171,9 @@ CreateRootBridge (
// If this bit is not set, then the PCI Root Bridge does not support
// 64 bit memory windows.
//
- ASSERT (Bridge->MemAbove4G.Base > Bridge->MemAbove4G.Limit);
- ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit);
- if ((Bridge->MemAbove4G.Base <= Bridge->MemAbove4G.Limit) ||
- (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit)
- ) {
+ ASSERT (!RESOURCE_VALID (Bridge->MemAbove4G));
+ ASSERT (!RESOURCE_VALID (Bridge->PMemAbove4G));
+ if (RESOURCE_VALID (Bridge->MemAbove4G) || RESOURCE_VALID (Bridge->PMemAbove4G)) {
return NULL;
}
}
--
2.16.1.windows.1
next prev parent reply other threads:[~2018-09-21 7:24 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-21 7:25 [PATCH 0/3] Fix a bug that prevents PMEM access Ruiyu Ni
2018-09-21 7:25 ` [PATCH 1/3] MdeModulePkg/PciHostBridge: Enhance boundary check in Io/Mem.Read/Write Ruiyu Ni
2018-09-21 10:53 ` Laszlo Ersek
2018-09-24 13:18 ` Kirkendall, Garrett
2018-09-25 2:14 ` Zeng, Star
2018-09-25 2:43 ` Ni, Ruiyu
2018-09-25 3:02 ` Zeng, Star
2018-09-21 7:25 ` [PATCH 2/3] MdeModulePkg/PciHostBridge: Fix a bug that prevents PMEM access Ruiyu Ni
2018-09-21 11:06 ` Laszlo Ersek
2018-09-25 2:11 ` Ni, Ruiyu
2018-09-24 13:19 ` Kirkendall, Garrett
2018-09-25 2:15 ` Zeng, Star
2018-09-21 7:25 ` Ruiyu Ni [this message]
2018-09-21 11:12 ` [PATCH 3/3] MdeModulePkg/PciHostBridge: Add RESOURCE_VALID() to simplify code Laszlo Ersek
2018-09-25 2:25 ` Ni, Ruiyu
2018-09-25 2:35 ` Zeng, Star
2018-09-25 2:47 ` Ni, Ruiyu
2018-09-25 3:13 ` Zeng, Star
2018-09-25 5:03 ` Ni, Ruiyu
2018-09-24 13:20 ` Kirkendall, Garrett
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