From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.120; helo=mga04.intel.com; envelope-from=eric.dong@intel.com; receiver=edk2-devel@lists.01.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2942F21BADAB6 for ; Fri, 21 Sep 2018 00:42:32 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Sep 2018 00:42:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,284,1534834800"; d="scan'208";a="92479689" Received: from ydong10-win10.ccr.corp.intel.com ([10.239.9.125]) by orsmga001.jf.intel.com with ESMTP; 21 Sep 2018 00:41:52 -0700 From: Eric Dong To: edk2-devel@lists.01.org Cc: Michael D Kinney , Ruiyu Ni , Laszlo Ersek Date: Fri, 21 Sep 2018 15:41:31 +0800 Message-Id: <20180921074133.9140-13-eric.dong@intel.com> X-Mailer: git-send-email 2.15.0.windows.1 In-Reply-To: <20180921074133.9140-1-eric.dong@intel.com> References: <20180921074133.9140-1-eric.dong@intel.com> Subject: [Patch v2 12/14] UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h: Add new MSR name and keep old one. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 21 Sep 2018 07:42:32 -0000 Changes includes: 1. Change MSR name: 1. MSR_SKYLAKE_SGXOWNER0 => MSR_SKYLAKE_SGXOWNEREPOCH0 2. MSR_SKYLAKE_SGXOWNER1 => MSR_SKYLAKE_SGXOWNEREPOCH1 2. Keep old MSR definition(MSR_SKYLAKE_SGXOWNER0/1) for compatibility 1. Use below coding style to define old MSR #define MSR_SKYLAKE_SGXOWNER0 MSR_SKYLAKE_SGXOWNEREPOCH0 Cc: Michael D Kinney Cc: Ruiyu Ni Cc: Laszlo Ersek Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong --- UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h | 40 +++++++++++++++++++--------- 1 file changed, 27 insertions(+), 13 deletions(-) diff --git a/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h b/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h index 90cde86ccb..88f2c28eae 100644 --- a/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h +++ b/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h @@ -197,10 +197,12 @@ typedef union { /** - Package. Lower 64 Bit OwnerEpoch Component of SGX Key (RO). Low 64 bits of - an 128-bit external entropy value for key derivation of an enclave. + Package. Lower 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update + CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in + the package. Lower 64 bits of an 128-bit external entropy value for key + derivation of an enclave. - @param ECX MSR_SKYLAKE_SGXOWNER0 (0x00000300) + @param ECX MSR_SKYLAKE_SGXOWNEREPOCH0 (0x00000300) @param EAX Lower 32-bits of MSR value. @param EDX Upper 32-bits of MSR value. @@ -208,18 +210,24 @@ typedef union { @code UINT64 Msr; - Msr = AsmReadMsr64 (MSR_SKYLAKE_SGXOWNER0); + Msr = 0; + AsmWriteMsr64 (MSR_SKYLAKE_SGXOWNEREPOCH0, Msr); @endcode - @note MSR_SKYLAKE_SGXOWNER0 is defined as MSR_SGXOWNER0 in SDM. + @note MSR_SKYLAKE_SGXOWNEREPOCH0 is defined as MSR_SGXOWNER0 in SDM. **/ -#define MSR_SKYLAKE_SGXOWNER0 0x00000300 - +#define MSR_SKYLAKE_SGXOWNEREPOCH0 0x00000300 +// +// Define MSR_SKYLAKE_SGXOWNER0 for compatibility due to name change in the SDM. +// +#define MSR_SKYLAKE_SGXOWNER0 MSR_SKYLAKE_SGXOWNEREPOCH0 /** - Package. Upper 64 Bit OwnerEpoch Component of SGX Key (RO). Upper 64 bits of - an 128-bit external entropy value for key derivation of an enclave. + Package. Upper 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update + CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in + the package. Upper 64 bits of an 128-bit external entropy value for key + derivation of an enclave. - @param ECX MSR_SKYLAKE_SGXOWNER1 (0x00000301) + @param ECX MSR_SKYLAKE_SGXOWNEREPOCH1 (0x00000301) @param EAX Lower 32-bits of MSR value. @param EDX Upper 32-bits of MSR value. @@ -227,11 +235,17 @@ typedef union { @code UINT64 Msr; - Msr = AsmReadMsr64 (MSR_SKYLAKE_SGXOWNER1); + Msr = 0; + AsmWriteMsr64 (MSR_SKYLAKE_SGXOWNEREPOCH1, Msr); @endcode - @note MSR_SKYLAKE_SGXOWNER1 is defined as MSR_SGXOWNER1 in SDM. + @note MSR_SKYLAKE_SGXOWNEREPOCH1 is defined as MSR_SGXOWNER1 in SDM. **/ -#define MSR_SKYLAKE_SGXOWNER1 0x00000301 +#define MSR_SKYLAKE_SGXOWNEREPOCH1 0x00000301 + +// +// Define MSR_SKYLAKE_SGXOWNER1 for compatibility due to name change in the SDM. +// +#define MSR_SKYLAKE_SGXOWNER1 MSR_SKYLAKE_SGXOWNEREPOCH1 /** -- 2.15.0.windows.1