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DIR:OUT; SFP:1102; SCL:1; SRVR:DM5PR2101MB0727; H:DM5PR2101MB1128.namprd21.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: microsoft.com does not designate permitted sender hosts) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Christopher.Co@microsoft.com; x-microsoft-antispam-message-info: Im4kU9WVNMFr65LNeaum/uMzMRqI43+Oh5cXmso0ecpuMRpM60A05HaCOUdzl8zyLEkT+JEZmhYGrDs+jIZTyLMI5GU+PZ4n+kKzJm7m2gx1rLTfgfbOuIMHE5WzPOcxMvTMwCx/VXro/z4EWWqjSujdGqcBvSGATI/MzpuDHXL3o8HLlCCX/gtWNYHv88tDMruED4/8EKM1gkTfZIUkvmsHFC9qr4FdAiz1r2XqLpCRUIcndqNORe6kdpST8KvylYKQRjTL/Sp/3Ed7n5SQtcABJHTLOP1B2N9/rzTll/ItX70S0CgLrdf4vLKME6UU45vtkmCGogAoxkOa+DTzsyyvOE+bDitNgebrzgkLL9RAbNNuhTqyC2ledDaYwuc2LzAk7hBLjwGtnnprSToa32qDDv8mRwm1vP5B4ob9rZ0Jp4Gifwc65DU0jUIx7e0CKtAXgjrmE1ogt9hTxVaBdRh2793NhpaBDKn6MEJ1O0p76uLEAU4+z1GEPV57dV4Mr7qcXnw42YhFKzaLjbtqSp81KcmgR4cuxG//snlrPXo7d2hLieFcPCS/rK4+EsyI spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: microsoft.com X-MS-Exchange-CrossTenant-Network-Message-Id: a163ee0a-14e0-4f39-c25c-08d61f9be6de X-MS-Exchange-CrossTenant-originalarrivaltime: 21 Sep 2018 08:26:17.8566 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 72f988bf-86f1-41af-91ab-2d7cd011db47 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR2101MB0727 Subject: [PATCH edk2-platforms 25/27] Platform/Solidrun: Add Hummingboard Peripheral Initialization X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 21 Sep 2018 08:26:27 -0000 Content-Language: en-US Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable This adds support to initialize the different peripherals on the Solidrun i.MX 6Quad Hummingboard Edge. It will initialize the pad mux and clocks for the different peripherals. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Christopher Co Cc: Michael D Kinney Cc: Ard Biesheuvel Cc: Leif Lindholm --- Platform/SolidRun/HummingBoardEdge_iMX6Q_2GB/Library/iMX6BoardLib/iMX6Boar= dInit.c | 634 ++++++++++++++++++ Platform/SolidRun/HummingBoardEdge_iMX6Q_2GB/Library/iMX6BoardLib/iMX6Boar= dInit.h | 705 ++++++++++++++++++++ Platform/SolidRun/HummingBoardEdge_iMX6Q_2GB/Library/iMX6BoardLib/iMX6Boar= dLib.inf | 91 +++ 3 files changed, 1430 insertions(+) diff --git a/Platform/SolidRun/HummingBoardEdge_iMX6Q_2GB/Library/iMX6Board= Lib/iMX6BoardInit.c b/Platform/SolidRun/HummingBoardEdge_iMX6Q_2GB/Library/= iMX6BoardLib/iMX6BoardInit.c new file mode 100644 index 000000000000..73e63484288c --- /dev/null +++ b/Platform/SolidRun/HummingBoardEdge_iMX6Q_2GB/Library/iMX6BoardLib/iMX= 6BoardInit.c @@ -0,0 +1,634 @@ +/** @file +* +* Copyright (c) 2018 Microsoft Corporation. All rights reserved. +* Copyright 2018 NXP +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "iMX6BoardInit.h" + +STATIC CONST IMX_CLK_GATE GatesToTurnOff[] =3D { + IMX_ASRC_CLK_ENABLE, + IMX_CAN1_CLK_ENABLE, + IMX_CAN1_SERIAL_CLK_ENABLE, + IMX_CAN2_CLK_ENABLE, + IMX_CAN2_SERIAL_CLK_ENABLE, + IMX_DCIC1_CLK_ENABLE, + IMX_DCIC2_CLK_ENABLE, + IMX_DTCP_CLK_ENABLE, + IMX_ECSPI1_CLK_ENABLE, + IMX_ECSPI2_CLK_ENABLE, + IMX_ECSPI3_CLK_ENABLE, + IMX_ECSPI4_CLK_ENABLE, + IMX_ECSPI5_CLK_ENABLE, + IMX_ENET_CLK_ENABLE, + IMX_ESAI_CLK_ENABLE, + IMX_I2C1_SERIAL_CLK_ENABLE, + IMX_I2C2_SERIAL_CLK_ENABLE, + IMX_I2C3_SERIAL_CLK_ENABLE, + IMX_IIM_CLK_ENABLE, + IMX_IPSYNC_IP2APB_TZASC1_IPG_MASTER_CLK_ENABLE, + IMX_IPSYNC_IP2APB_TZASC2_IPG_MASTER_CLK_ENABLE, + IMX_IPSYNC_VDOA_IPG_MASTER_CLK_ENABLE, + IMX_IPU1_DI1_CLK_ENABLE, + IMX_IPU2_CLK_ENABLE, + IMX_IPU2_DI0_CLK_ENABLE, + IMX_IPU2_DI1_CLK_ENABLE, + IMX_LDB_DI0_CLK_ENABLE, + IMX_LDB_DI1_CLK_ENABLE, + IMX_MIPI_CORE_CFG_CLK_ENABLE, + IMX_MLB_CLK_ENABLE, + IMX_PL301_MX6QPER1_BCHCLK_ENABLE, + IMX_PWM2_CLK_ENABLE, + IMX_PWM3_CLK_ENABLE, + IMX_PWM4_CLK_ENABLE, + IMX_RAWNAND_U_BCH_INPUT_APB_CLK_ENABLE, + IMX_RAWNAND_U_GPMI_BCH_INPUT_BCH_CLK_ENABLE, + IMX_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_CLK_ENABLE, + IMX_RAWNAND_U_GPMI_INPUT_APB_CLK_ENABLE, + IMX_SPDIF_CLK_ENABLE, + IMX_SSI1_CLK_ENABLE, + IMX_SSI2_CLK_ENABLE, + IMX_SSI3_CLK_ENABLE, + IMX_EIM_SLOW_CLK_ENABLE, + IMX_VDOAXICLK_CLK_ENABLE, + IMX_VPU_CLK_ENABLE, +}; + +STATIC CONST IMX_CLK_GATE GatesToTurnOn[] =3D { + IMX_SDMA_CLK_ENABLE, + IMX_SPBA_CLK_ENABLE, + IMX_GPT_SERIAL_CLK_ENABLE, + IMX_USBOH3_CLK_ENABLE, + IMX_PWM1_CLK_ENABLE +}; + +STATIC IMX_PAD GpioPins[] =3D { + IMX_PAD_ENET_RX_ER, + IMX_PAD_EIM_A22, + IMX_PAD_EIM_A21, + IMX_PAD_EIM_A20, + IMX_PAD_EIM_A19, + IMX_PAD_EIM_A18, + IMX_PAD_EIM_A17, + IMX_PAD_EIM_A16, + IMX_PAD_EIM_EB0, + IMX_PAD_EIM_EB1, + IMX_PAD_EIM_DA0, + IMX_PAD_EIM_DA1, + IMX_PAD_EIM_DA2, + IMX_PAD_EIM_DA3, + IMX_PAD_EIM_DA4, + IMX_PAD_EIM_DA5, + IMX_PAD_EIM_DA6, + IMX_PAD_EIM_DA7, + IMX_PAD_EIM_DA8, + IMX_PAD_EIM_DA9, + IMX_PAD_EIM_DA10, + IMX_PAD_EIM_DA11, + IMX_PAD_EIM_DA12, + IMX_PAD_EIM_DA13, + IMX_PAD_EIM_DA14, + IMX_PAD_EIM_DA15, + IMX_PAD_EIM_D26, + IMX_PAD_EIM_D27, + IMX_PAD_EIM_D30, + IMX_PAD_EIM_D31, + IMX_PAD_EIM_A24, + IMX_PAD_EIM_A23, + IMX_PAD_GPIO_16, +}; + +CONST IMX_CLK_GATE UartClockGatesToTurnOn[] =3D { + IMX_PLL3_MAIN_CLK, // IMX_UART_CLK_ENABLE, + IMX_UART_CLK_ROOT // UART_SERIAL_CLK_ENABLE, +}; + +/** + Turn off clock gates which are not needed during boot. The PEP is respon= sible + to ungate clocks as needed. +**/ +STATIC +VOID +GateUnusedClocks ( + VOID + ) +{ + ImxClkPwrSetClockGates ( + GatesToTurnOff, + sizeof (GatesToTurnOff) / sizeof (GatesToTurnOff[0]), + IMX_CLOCK_GATE_STATE_OFF); +} + +/** + Turn on required clocks, that are not handled by the PEP. +**/ +STATIC +VOID +UngateRequiredClocks ( + VOID + ) +{ + ImxClkPwrSetClockGates ( + GatesToTurnOn, + sizeof (GatesToTurnOn) / sizeof (GatesToTurnOn[0]), + IMX_CLOCK_GATE_STATE_ON); +} + +STATIC +VOID +EnetInit ( + VOID + ) +{ + volatile IMX_CCM_ANALOG_REGISTERS *pCcmAnalogReg; + IMX_CCM_ANALOG_PLL_ENET_REG CcmAnalogPllReg; + UINT32 Counter; + + // Apply ENET pin-muxing configurations (ALT 1) + ImxPadConfig (IMX_PAD_ENET_MDIO, IMX_PAD_ENET_MDIO_ENET_MDIO); + ImxPadConfig (IMX_PAD_ENET_MDC, IMX_PAD_ENET_MDC_ENET_MDC); + ImxPadConfig (IMX_PAD_KEY_ROW4, IMX_PAD_CFG_KEY_ROW4_GPIO4_IO15); + ImxPadConfig (IMX_PAD_DI0_PIN2, IMX_PAD_DI0_PIN2_GPIO4_IO18); + ImxPadConfig (IMX_PAD_GPIO_16, IMX_PAD_GPIO_16_ENET_REF_CLK); + ImxPadConfig (IMX_PAD_ENET_REF_CLK, IMX_PAD_ENET_REF_CLK_ENET_REF_CLK); + ImxPadConfig (IMX_PAD_RGMII_TD0, IMX_PAD_RGMII_TD0_RGMII_TD0); + ImxPadConfig (IMX_PAD_RGMII_TD1, IMX_PAD_RGMII_TD1_RGMII_TD1); + ImxPadConfig (IMX_PAD_RGMII_TD2, IMX_PAD_RGMII_TD2_RGMII_TD2); + ImxPadConfig (IMX_PAD_RGMII_TD3, IMX_PAD_RGMII_TD3_RGMII_TD3); + ImxPadConfig (IMX_PAD_RGMII_TXC, IMX_PAD_RGMII_TXC_RGMII_TXC); + ImxPadConfig (IMX_PAD_RGMII_TX_CTL, IMX_PAD_RGMII_TX_CTL_RGMII_TX_CTL); + + ImxPadConfig (IMX_PAD_RGMII_RD0, IMX_PAD_RGMII_RD0_ENET_RGMII_RD0); + ImxPadConfig (IMX_PAD_RGMII_RD1, IMX_PAD_RGMII_RD1_ENET_RGMII_RD1); + ImxPadConfig (IMX_PAD_RGMII_RD2, IMX_PAD_RGMII_RD2_ENET_RGMII_RD2); + ImxPadConfig (IMX_PAD_RGMII_RD3, IMX_PAD_RGMII_RD3_ENET_RGMII_RD3); + ImxPadConfig (IMX_PAD_RGMII_RXC, IMX_PAD_RGMII_RXC_ENET_RGMII_RXC); + ImxPadConfig (IMX_PAD_RGMII_RX_CTL, IMX_PAD_RGMII_RX_CTL_RGMII_RX_CTL); + + // Enable ENET PLL, also required for PCIe + pCcmAnalogReg =3D (IMX_CCM_ANALOG_REGISTERS *)IMX_CCM_ANALOG_BASE; + CcmAnalogPllReg.AsUint32 =3D MmioRead32 ((UINTN)&pCcmAnalogReg->PLL_ENET= ); + CcmAnalogPllReg.POWERDOWN =3D 0; + CcmAnalogPllReg.ENABLE =3D 1; + MmioWrite32 ((UINTN)&pCcmAnalogReg->PLL_ENET, CcmAnalogPllReg.AsUint32); + + for (Counter =3D 0; Counter < 100; Counter++) { + CcmAnalogPllReg.AsUint32 =3D MmioRead32 ((UINTN)&pCcmAnalogReg->PLL_EN= ET); + if (CcmAnalogPllReg.LOCK !=3D 0) { + break; + } + MicroSecondDelay (100); + } + if (CcmAnalogPllReg.LOCK =3D=3D 0) { + DEBUG ((DEBUG_ERROR, "%a: PLL_ENET is not locked!\n", __FUNCTION__)); + return; + } + + // Enable PCIe output 125Mhz + CcmAnalogPllReg.BYPASS =3D 0; + CcmAnalogPllReg.ENABLE_125M =3D 1; + CcmAnalogPllReg.DIV_SELECT =3D PLL_ENET_DIV_SELECT_25MHZ; + MmioWrite32 ((UINTN)&pCcmAnalogReg->PLL_ENET, CcmAnalogPllReg.AsUint32); + MicroSecondDelay (50000); + + if (CcmAnalogPllReg.LOCK =3D=3D 0) { + DEBUG ((DEBUG_ERROR, "%a: PLL_ENET is not locked!\n", __FUNCTION__)); + } +} + +/** + Set SSI3 clock dividers to provide a bit clock capable of + providing a clock suitable for stereo 44.1 KHz playback at 32 bit + from PLL3 PFD2 which runs at 508.2 MHz. + + We only need to scale down the PLL3 FPD2 clock by 1:15 to provide a + reference clock. The WDM audio class driver will later setup additional + dividers in the SSI3 block to provide the required bit clock rate. + + This routine also handles all GPIO/PadConfig init required for audio. +**/ +STATIC +VOID +SetupAudio ( + VOID + ) +{ + volatile IMX_CCM_REGISTERS *pCcmReg; + IMX_CCM_CCOSR_REG CcosrReg; + IMX_CCM_CS1CDR_REG CsicdrReg; + + pCcmReg =3D (IMX_CCM_REGISTERS *)IMX_CCM_BASE; + CsicdrReg =3D (IMX_CCM_CS1CDR_REG) MmioRead32 ((UINTN)&pCcmReg->CS1CDR); + CsicdrReg.ssi3_clk_pred =3D 0; // divide by 1. + CsicdrReg.ssi3_clk_podf =3D 14; // divide by 15. + MmioWrite32 ((UINTN)&pCcmReg->CS1CDR, CsicdrReg.AsUint32); + + // Enable output on CCM_CLKO1, select pll3_sw_clk/2 as the source. + CcosrReg =3D (IMX_CCM_CCOSR_REG) MmioRead32 ((UINTN)&pCcmReg->CCOSR); + CcosrReg.CLKO1_SEL =3D 0; + CcosrReg.CLKO1_DIV =3D 0; + CcosrReg.CLKO1_EN =3D 1; + + MmioWrite32 ((UINTN)&pCcmReg->CCOSR, CcosrReg.AsUint32); + // Set GPIO05 alt config to ALT3 (CCM_CLKO1). + // This clock drives the master clock for the audio codec. + ImxPadConfig (IMX_PAD_GPIO_5, IMX_PAD_CFG_GPIO_5_CCM_CLKO1); + + // Set alt config for KEY_COL0, KEY_ROW0, KEY_COL1 to ALT2 (AUD5_TXC/TXD= /TXFS) + // DSP_DAT19 is set to ALT3 for AUD5_RXD. + ImxPadConfig (IMX_PAD_KEY_COL0, IMX_PAD_CFG_KEY_COL0_AUD5_TXC); + ImxPadConfig (IMX_PAD_KEY_ROW0, IMX_PAD_CFG_KEY_ROW0_AUD5_TXD); + ImxPadConfig (IMX_PAD_KEY_COL1, IMX_PAD_CFG_KEY_COL1_AUD5_TXFS); + ImxPadConfig (IMX_PAD_DISP0_DAT19, IMX_PAD_CFG_DISP0_DAT19_AUD5_RXD); +} + +/** + Initialize clock and power for modules on the SoC. +**/ +VOID +ImxClkPwrInit ( + VOID + ) +{ + EFI_STATUS Status; + + GateUnusedClocks(); + UngateRequiredClocks(); + + if (FeaturePcdGet (PcdGpuEnable)) { + Status =3D ImxClkPwrGpuEnable (); + ASSERT_EFI_ERROR (Status); + } + + if (FeaturePcdGet (PcdLvdsEnable)) { + Status =3D ImxClkPwrIpuLDBxEnable (); + ASSERT_EFI_ERROR (Status); + } + + Status =3D ImxClkPwrIpuDIxEnable(); + ASSERT_EFI_ERROR (Status); + + ASSERT_EFI_ERROR (ImxClkPwrValidateClocks ()); +} + +/** + Initialize SDHC modules on the SOC and perform required pin-muxing +**/ +VOID +SdhcInit ( + VOID + ) +{ + // uSDHC2: SDCard Socket + ImxPadConfig (IMX_PAD_SD2_CLK, IMX_PAD_CFG_SD2_CLK_SD2_CLK); + ImxPadConfig (IMX_PAD_SD2_CMD, IMX_PAD_CFG_SD2_CMD_SD2_CMD); + ImxPadConfig (IMX_PAD_SD2_DAT0, IMX_PAD_CFG_SD2_DAT0_SD2_DATA0); + ImxPadConfig (IMX_PAD_SD2_DAT1, IMX_PAD_CFG_SD2_DAT1_SD2_DATA1); + ImxPadConfig (IMX_PAD_SD2_DAT2, IMX_PAD_CFG_SD2_DAT2_SD2_DATA2); + ImxPadConfig (IMX_PAD_SD2_DAT3, IMX_PAD_CFG_SD2_DAT3_SD2_DATA3); + ImxPadConfig (IMX_PAD_GPIO_4, IMX_PAD_CFG_GPIO_4_SD2_CD_B); + ImxPadConfig (IMX_PAD_KEY_ROW1, IMX_PAD_CFG_KEY_ROW1_SD2_VSELECT); + +#if DEBUG + DEBUG ((DEBUG_INIT, "uSDHC2 PAD Config:\n")); + ImxPadDumpConfig ("CLK", IMX_PAD_SD2_CLK); + ImxPadDumpConfig ("CMD", IMX_PAD_SD2_CMD); + ImxPadDumpConfig ("DAT0", IMX_PAD_SD2_DAT0); + ImxPadDumpConfig ("DAT1", IMX_PAD_SD2_DAT1); + ImxPadDumpConfig ("DAT2", IMX_PAD_SD2_DAT2); + ImxPadDumpConfig ("DAT3", IMX_PAD_SD2_DAT3); + ImxPadDumpConfig ("VSELECT", IMX_PAD_KEY_ROW1); + ImxPadDumpConfig ("CD", IMX_PAD_GPIO_4); +#endif // DEBUG + + // Power-on SDCard through the GPIO signal connected to + // Q1 MOSFET Gate acting as a switch to SDCard VDD supply voltage + ImxPadConfig (IMX_PAD_DISP0_DAT9, IMX_PAD_CFG_DISP0_DAT9_GPIO4_IO30); + ImxGpioDirection (IMX_GPIO_BANK4, 30, IMX_GPIO_DIR_OUTPUT); + ImxGpioWrite (IMX_GPIO_BANK4, 30, IMX_GPIO_LOW); + + // Pre-configure the GPIO ALT5 of all SD2_* pads to be input pins. + // SD2_CLK: GPIO1_IO10 + ImxGpioDirection (IMX_GPIO_BANK1, 10, IMX_GPIO_DIR_INPUT); + + // SD2_CMD: GPIO1_IO11 + ImxGpioDirection (IMX_GPIO_BANK1, 11, IMX_GPIO_DIR_INPUT); + + // SD2_DATA0: GPIO1_IO15 + ImxGpioDirection (IMX_GPIO_BANK1, 15, IMX_GPIO_DIR_INPUT); + + // SD2_DATA1: GPIO1_IO14 + ImxGpioDirection (IMX_GPIO_BANK1, 14, IMX_GPIO_DIR_INPUT); + + // SD2_DATA2: GPIO1_IO13 + ImxGpioDirection (IMX_GPIO_BANK1, 13, IMX_GPIO_DIR_INPUT); + + // SD2_DATA3: GPIO1_IO12 + ImxGpioDirection (IMX_GPIO_BANK1, 12, IMX_GPIO_DIR_INPUT); + + // uSDHC3: eMMC Socket + ImxPadConfig (IMX_PAD_SD3_CLK, IMX_PAD_CFG_SD3_CLK_SD3_CLK); + ImxPadConfig (IMX_PAD_SD3_CMD, IMX_PAD_CFG_SD3_CMD_SD3_CMD); + ImxPadConfig (IMX_PAD_SD3_RST, IMX_PAD_CFG_SD3_RST_SD3_RST); + ImxPadConfig (IMX_PAD_SD3_DAT0, IMX_PAD_CFG_SD3_DAT0_SD3_DATA0); + ImxPadConfig (IMX_PAD_SD3_DAT1, IMX_PAD_CFG_SD3_DAT1_SD3_DATA1); + ImxPadConfig (IMX_PAD_SD3_DAT2, IMX_PAD_CFG_SD3_DAT2_SD3_DATA2); + ImxPadConfig (IMX_PAD_SD3_DAT3, IMX_PAD_CFG_SD3_DAT3_SD3_DATA3); + ImxPadConfig (IMX_PAD_SD3_DAT4, IMX_PAD_CFG_SD3_DAT4_SD3_DATA4); + ImxPadConfig (IMX_PAD_SD3_DAT5, IMX_PAD_CFG_SD3_DAT5_SD3_DATA5); + ImxPadConfig (IMX_PAD_SD3_DAT6, IMX_PAD_CFG_SD3_DAT6_SD3_DATA6); + ImxPadConfig (IMX_PAD_SD3_DAT7, IMX_PAD_CFG_SD3_DAT7_SD3_DATA7); +} + +/** + Initialize EHCI modules on the SOC and perform required pin-muxing. + This routine also initializes PHY0(OTG) and PHY1 (USBH1). +**/ +VOID +EhciInit ( + VOID + ) +{ + volatile IMX_IOMUXC_GPR_REGISTERS *pIoMuxGprReg; + IMX_IOMUXC_GPR1_REG IoMuxGpr1Reg; + + // Pin-mux OTG Over Current + ImxPadConfig (IMX_PAD_KEY_COL4, IMX_PAD_CFG_KEY_COL4_USB_OTG_OC); + + // Pin-mux and enable OTG power + ImxPadConfig (IMX_PAD_EIM_D22, IMX_PAD_CFG_EIM_DATA22_GPIO3_IO22_USB_OTG= _PWR); + ImxGpioDirection (IMX_GPIO_BANK3, 22, IMX_GPIO_DIR_OUTPUT); + ImxGpioWrite (IMX_GPIO_BANK3, 22, IMX_GPIO_HIGH); + + // Pin-mux and configure USB_OTG_ID as HOST + ImxPadConfig (IMX_PAD_GPIO_1, IMX_PAD_CFG_GPIO01_USB_OTG_ID_HOST); + + // Configure USB_OTG_ID pin + pIoMuxGprReg =3D (IMX_IOMUXC_GPR_REGISTERS *) IOMUXC_GPR_BASE_ADDRESS; + IoMuxGpr1Reg =3D (IMX_IOMUXC_GPR1_REG) MmioRead32 ((UINTN)&pIoMuxGprReg-= >GPR1); + IoMuxGpr1Reg.USB_OTG_ID_SEL =3D IMX_IOMUXC_GPR1_USB_OTG_ID_SEL_GPIO_1; + MmioWrite32 ((UINTN)&pIoMuxGprReg->GPR1, IoMuxGpr1Reg.AsUint32); + + // Pin-mux and enable USBH1 power + ImxPadConfig (IMX_PAD_GPIO_0, IMX_PAD_CFG_GPIO0_GPIO1_IO0_USBH1_PWR); + ImxGpioDirection (IMX_GPIO_BANK1, 0, IMX_GPIO_DIR_OUTPUT); + ImxGpioWrite (IMX_GPIO_BANK1, 0, IMX_GPIO_HIGH); + + // Initialize PHY0 (OTG) + ImxUsbPhyInit (IMX_USBPHY0); + + // Initialize PHY1 (USBH1) + ImxUsbPhyInit (IMX_USBPHY1); +} + +/** + Initialize I2C modules on the SOC and perform required pin-muxing +**/ +VOID +I2cInit ( + VOID + ) +{ + // Enable 1.8V and 3.3V power rails for sensors connected to I2C1. + // The SENSOR_PWR_EN on EIM_EB3 line powers the pullups on I2c1. + ImxPadConfig (IMX_PAD_EIM_EB3, IMX_PAD_CFG_EIM_EB3_GPIO2_IO31); + ImxGpioDirection (IMX_GPIO_BANK2, 31, IMX_GPIO_DIR_OUTPUT); + ImxGpioWrite (IMX_GPIO_BANK2, 31, IMX_GPIO_HIGH); // set GPIO2_IO31 to 1 + DEBUG ((DEBUG_INFO, "%a: Mux IMX_PAD_EIM_EB3 to GPIO Alt5. Set GPIO2_IO3= 1\n", + __FUNCTION__)); + + // Configure I2C1. EIM_D21 is I2C1_SCL and EIM_D28 is I2C1_SDA. Alt6, Al= t1 + ImxPadConfig (IMX_PAD_EIM_D21, IMX_PAD_CFG_EIM_D21_I2C1_SCL); + ImxPadConfig (IMX_PAD_EIM_D28, IMX_PAD_CFG_EIM_D28_I2C1_SDA); + DEBUG ((DEBUG_INFO, "%a: I2C1 pin muxed via EIM D28,21\n", __FUNCTION__)= ); + + // I2C2 is used by GOP/Windows display driver. Do not configure I2C2 SCL= via KEY_COL3, SDA via KEY_ROW3 + + // Configure I2C3 SCL via EIM_D17, SDA via EIM_D18. Inputs Alt6 + ImxPadConfig (IMX_PAD_EIM_D17, IMX_PAD_CFG_EIM_D17_I2C3_SCL); + ImxPadConfig (IMX_PAD_EIM_D18, IMX_PAD_CFG_EIM_D18_I2C3_SDA); + DEBUG ((DEBUG_INFO, "%a: I2C3 pin muxed EIM_D17, 18\n", __FUNCTION__)); +} + +/** + Initialize SPI modules on the SOC and perform required pin-muxing +**/ +VOID +SpiInit ( + VOID + ) +{ + UINT32 RegValue; + // On Hummingboard only ESPI2 is exposed. + // Configure the return path for ECSPI2_MISO + RegValue =3D MmioRead32 (IOMUXC_ECSPI2_MISO_SELECT_INPUT); + RegValue &=3D ~3; + RegValue |=3D (IMX_IOMUXC_ECSPI2_MISO_EIM_OE_B_ALT2 << 0); + MmioWrite32 (IOMUXC_ECSPI2_MISO_SELECT_INPUT, RegValue); +} + +/** + Initialize PCI Express module on the SOC and perform required pin-muxing +**/ +VOID +PcieInit ( + VOID + ) +{ + // PCIe GPIO Reset + ImxPadConfig (IMX_PAD_SD4_DAT3, IMX_PAD_CFG_SD4_DATA3_GPIO2_IO11); + ImxGpioDirection (IMX_GPIO_BANK2, 11, IMX_GPIO_DIR_OUTPUT); + ImxGpioWrite (IMX_GPIO_BANK2, 11, IMX_GPIO_LOW); +} + +/** + Initialize exposed GPIO pins on carrier board. By default some + pins are set to CMOS inputs while others are set to Schmitt + triggers. Normalize them all to Schmitt trigger inputs by setting + the hysteresis bit (16) in the pad ctl register. +**/ +VOID +GpioInit ( + VOID + ) +{ + UINT32 i; + IMX_PAD CurPad; + + for (i =3D 0; i < sizeof (GpioPins) / sizeof (IMX_PAD); ++i) { + CurPad =3D GpioPins[i]; + MmioOr32 (IMX_IOMUXC_BASE + _IMX_PAD_CTL_OFFSET (CurPad), 1 << 16); + } +} + +/** + Initalize the PWM controllers + PWM1 is exposed through Mikrobus header + Pinmux pad DISP0_DAT8 to (ALT2) PWM1_OUT +**/ +VOID +PwmInit ( + VOID + ) +{ + ImxPadConfig (IMX_PAD_DISP0_DAT8, IMX_PAD_CFG_DISP0_DAT8_PWM1_OUT); +} + +/** + Initalize the UART controllers +**/ +VOID +UartInit ( + VOID + ) +{ + // UARTs share same Clock: + // PLL3 (480 MHz) -> pll3_sw_clk -> CG -> /6 -> uart_clk_root =3D 80 MHz + ImxClkPwrSetClockGates ( + UartClockGatesToTurnOn, + sizeof (UartClockGatesToTurnOn) / sizeof (UartClockGatesToTurnOn[0]), + IMX_CLOCK_GATE_STATE_ON); + + // Configure pin mux for UART 1 and UART 3 + ImxPadConfig (IMX_PAD_CSI0_DAT11, IMX_PAD_UART1_RX_DATA); + ImxPadConfig (IMX_PAD_CSI0_DAT10, IMX_PAD_UART1_TX_DATA); + ImxPadConfig (IMX_PAD_EIM_D25, IMX_PAD_UART3_RX_DATA); + ImxPadConfig (IMX_PAD_EIM_D24, IMX_PAD_UART3_TX_DATA); + + SerialPortInitialize (); + SerialPortWrite ( + (UINT8 *)SERIAL_DEBUG_PORT_INIT_MSG, + (UINTN)sizeof (SERIAL_DEBUG_PORT_INIT_MSG)); +} + +/** + Initialize the TPM2 control area. +**/ +VOID +Tpm2AcpiControlAreaInit ( + VOID + ) +{ + EFI_TPM2_ACPI_CONTROL_AREA *pControlArea; + EFI_PHYSICAL_ADDRESS BaseAddress; + UINT32 BufferSize; + + BaseAddress =3D PcdGet64 (PcdTpm2AcpiBufferBase); + BufferSize =3D PcdGet32 (PcdTpm2AcpiBufferSize); + + if ((BaseAddress =3D=3D 0) || (BufferSize =3D=3D 0)) { + // TPM not enabled + return; + } + + ASSERT (BufferSize >=3D EFI_PAGE_SIZE * 3); + + pControlArea =3D (EFI_TPM2_ACPI_CONTROL_AREA *) ((UINTN)BaseAddress); + ZeroMem (pControlArea, sizeof (EFI_TPM2_ACPI_CONTROL_AREA)); + BufferSize =3D EFI_PAGE_SIZE; + pControlArea->Command =3D (UINT64) ((UINTN) (pControlArea + 1)); + pControlArea->CommandSize =3D BufferSize; + pControlArea->Response =3D pControlArea->Command + BufferSize; + pControlArea->ResponseSize =3D BufferSize; +} + +/** + Initalize LVDS +**/ +VOID +LvdsInit ( + VOID + ) +{ + volatile IMX_CCM_REGISTERS *pCcmReg; + IMX_CCM_CCGR3_REG Ccgr3Reg; + + pCcmReg =3D (IMX_CCM_REGISTERS *) IMX_CCM_BASE; + Ccgr3Reg =3D (IMX_CCM_CCGR3_REG) MmioRead32 ((UINTN) &pCcmReg->CCGR[3]); + Ccgr3Reg.ldb_di0_clk_enable =3D 0x3; + MmioWrite32 ((UINTN) &pCcmReg->CCGR[3], Ccgr3Reg.AsUint32); + + // initalize backlight pin + ImxPadConfig (IMX_PAD_SD4_DAT1, IMX_PAD_CFG_SD4_DATA1_GPIO2_IO09); + ImxGpioDirection (IMX_GPIO_BANK2, 9, IMX_GPIO_DIR_OUTPUT); + ImxGpioWrite (IMX_GPIO_BANK2, 9, IMX_GPIO_HIGH); +} + +/** + Initialize controllers that must setup at the early stage for iMX6 Quad +**/ +RETURN_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + if (!ArmPlatformIsPrimaryCore (MpId)) { + return RETURN_SUCCESS; + } + + ImxClkPwrInit (); + + // initialize default UEFI debug port early so we can use its debug outp= ut + SerialPortInitialize (); + SerialPortWrite ( + (UINT8 *)SERIAL_DEBUG_PORT_INIT_MSG, + (UINTN)sizeof (SERIAL_DEBUG_PORT_INIT_MSG)); + + // Initialize timer early on because the following init path will be cal= ling + // delay functions. PrePi.c calls ArmPlatformInitialize before it calls + // TimerConstructor to initialize the timer. + TimerConstructor (); + + SdhcInit (); + EhciInit (); + EnetInit (); + I2cInit (); + SpiInit (); + PcieInit (); + SetupAudio (); + GpioInit (); + PwmInit (); + + if (FeaturePcdGet (PcdLvdsEnable)) { + LvdsInit (); + } + + Tpm2AcpiControlAreaInit (); + + return RETURN_SUCCESS; +} + +/** + Return the current Boot Mode + + This function returns the boot reason on the platform + +**/ +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} diff --git a/Platform/SolidRun/HummingBoardEdge_iMX6Q_2GB/Library/iMX6Board= Lib/iMX6BoardInit.h b/Platform/SolidRun/HummingBoardEdge_iMX6Q_2GB/Library/= iMX6BoardLib/iMX6BoardInit.h new file mode 100644 index 000000000000..08ac78b16e8f --- /dev/null +++ b/Platform/SolidRun/HummingBoardEdge_iMX6Q_2GB/Library/iMX6BoardLib/iMX= 6BoardInit.h @@ -0,0 +1,705 @@ +/** @file +* +* Copyright (c) 2018 Microsoft Corporation. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#ifndef _IMX6_BOARD_INIT_H_ +#define _IMX6_BOARD_INIT_H_ + +#include +#include +#include +#include +#include + +// Prebaked pad configurations that include mux and drive settings where +// each enum named as IMX__PADCFG contains configurations +// for pads used by that module +typedef enum { + IMX_PAD_ENET_MDIO_ENET_MDIO =3D _IMX_MAKE_PADCFG ( + IMX_SRE_SLOW, + IMX_DSE_40_OHM, + IMX_SPEED_MEDIUM, + IMX_ODE_ENABLE, + IMX_PKE_DISABLE, + IMX_PUE_PULL, + IMX_PUS_100K_OHM_PU, + IMX_HYS_ENABLED, + IMX_SION_DISABLED, + IMX_IOMUXC_ENET_MDIO_ALT1_ENET_MDIO), + + IMX_PAD_ENET_MDC_ENET_MDC =3D _IMX_MAKE_PADCFG ( + IMX_SRE_SLOW, + IMX_DSE_40_OHM, + IMX_SPEED_MEDIUM, + IMX_ODE_DISABLE, + IMX_PKE_DISABLE, + IMX_PUE_PULL, + IMX_PUS_100K_OHM_PU, + IMX_HYS_ENABLED, + IMX_SION_DISABLED, + IMX_IOMUXC_ENET_MDC_ALT1_ENET_MDC), + + IMX_PAD_CFG_KEY_ROW4_GPIO4_IO15 =3D _IMX_MAKE_PADCFG ( + IMX_SRE_SLOW, + IMX_DSE_40_OHM, + IMX_SPEED_MEDIUM, + IMX_ODE_DISABLE, + IMX_PKE_DISABLE, + IMX_PUE_PULL, + IMX_PUS_100K_OHM_PD, + IMX_HYS_ENABLED, + IMX_SION_DISABLED, + IMX_IOMUXC_KEY_ROW4_ALT5_GPIO4_IO15)= , + + IMX_PAD_DI0_PIN2_GPIO4_IO18 =3D _IMX_MAKE_PADCFG ( + IMX_SRE_SLOW, + IMX_DSE_40_OHM, + IMX_SPEED_MEDIUM, + IMX_ODE_DISABLE, + IMX_PKE_DISABLE, + IMX_PUE_PULL, + IMX_PUS_100K_OHM_PD, + IMX_HYS_ENABLED, + IMX_SION_DISABLED, + IMX_IOMUXC_DI0_PIN2_ALT5_GPIO4_IO18), + + IMX_PAD_GPIO_16_ENET_REF_CLK =3D _IMX_MAKE_PADCFG_INPSEL ( + IMX_SRE_SLOW, + IMX_DSE_40_OHM, + IMX_SPEED_MEDIUM, + IMX_ODE_DISABLE, + IMX_PKE_DISABLE, + IMX_PUE_PULL, + IMX_PUS_100K_OHM_PU, + IMX_HYS_ENABLED, + IMX_SION_DISABLED, + IMX_IOMUXC_GPIO_16_ALT2_ENET_REF_CLK, + IOMUXC_ENET_REF_CLK_SELECT_INPUT, + GPIO16_ALT2), + + IMX_PAD_RGMII_TXC_RGMII_TXC =3D _IMX_MAKE_PADCFG ( + IMX_SRE_SLOW, + IMX_DSE_40_OHM, + IMX_SPEED_MEDIUM, + IMX_ODE_DISABLE, + IMX_PKE_DISABLE, + IMX_PUE_PULL, + IMX_PUS_100K_OHM_PU, + IMX_HYS_ENABLED, + IMX_SION_DISABLED, + IMX_IOMUXC_RGMII_TXC_ALT1_RGMII_TXC), + + IMX_PAD_RGMII_TD0_RGMII_TD0 =3D _IMX_MAKE_PADCFG ( + IMX_SRE_SLOW, + IMX_DSE_40_OHM, + IMX_SPEED_MEDIUM, + IMX_ODE_DISABLE, + IMX_PKE_DISABLE, + IMX_PUE_KEEP, + IMX_PUS_100K_OHM_PU, + IMX_HYS_ENABLED, + IMX_SION_DISABLED, + IMX_IOMUXC_RGMII_TD0_ALT1_RGMII_TD0), + + IMX_PAD_RGMII_TD1_RGMII_TD1 =3D _IMX_MAKE_PADCFG ( + IMX_SRE_SLOW, + IMX_DSE_40_OHM, + IMX_SPEED_MEDIUM, + IMX_ODE_DISABLE, + IMX_PKE_DISABLE, + IMX_PUE_KEEP, + IMX_PUS_100K_OHM_PU, + IMX_HYS_ENABLED, + IMX_SION_DISABLED, + IMX_IOMUXC_RGMII_TD1_ALT1_RGMII_TD1), + + IMX_PAD_RGMII_TD2_RGMII_TD2 =3D _IMX_MAKE_PADCFG ( + IMX_SRE_SLOW, + IMX_DSE_40_OHM, + IMX_SPEED_MEDIUM, + IMX_ODE_DISABLE, + IMX_PKE_DISABLE, + IMX_PUE_KEEP, + IMX_PUS_100K_OHM_PU, + IMX_HYS_ENABLED, + IMX_SION_DISABLED, + IMX_IOMUXC_RGMII_TD2_ALT1_RGMII_TD2), + + IMX_PAD_RGMII_TD3_RGMII_TD3 =3D _IMX_MAKE_PADCFG ( + IMX_SRE_SLOW, + IMX_DSE_40_OHM, + IMX_SPEED_MEDIUM, + IMX_ODE_DISABLE, + IMX_PKE_DISABLE, + IMX_PUE_KEEP, + IMX_PUS_100K_OHM_PU, + IMX_HYS_ENABLED, + IMX_SION_DISABLED, + IMX_IOMUXC_RGMII_TD3_ALT1_RGMII_TD3), + + IMX_PAD_RGMII_TX_CTL_RGMII_TX_CTL =3D _IMX_MAKE_PADCFG ( + IMX_SRE_SLOW, + IMX_DSE_40_OHM, + IMX_SPEED_MEDIUM, + IMX_ODE_DISABLE, + IMX_PKE_DISABLE, + IMX_PUE_PULL, + IMX_PUS_100K_OHM_PU, + IMX_HYS_ENABLED, + IMX_SION_DISABLED, + IMX_IOMUXC_RGMII_TX_CTL_ALT1_RGMII= _TX_CTL), + + IMX_PAD_ENET_REF_CLK_ENET_REF_CLK =3D _IMX_MAKE_PADCFG ( + IMX_SRE_FAST, + IMX_DSE_40_OHM, + IMX_SPEED_MEDIUM, + IMX_ODE_DISABLE, + IMX_PKE_DISABLE, + IMX_PUE_KEEP, + IMX_PUS_100K_OHM_PD, + IMX_HYS_DISABLED, + IMX_SION_DISABLED, + IMX_IOMUXC_ENET_REF_CLK_ALT1_ENET_= TX_CLK), + + IMX_PAD_RGMII_RXC_ENET_RGMII_RXC =3D _IMX_MAKE_PADCFG ( + IMX_SRE_SLOW, + IMX_DSE_40_OHM, + IMX_SPEED_MEDIUM, + IMX_ODE_DISABLE, + IMX_PKE_DISABLE, + IMX_PUE_KEEP, + IMX_PUS_100K_OHM_PU, + IMX_HYS_ENABLED, + IMX_SION_DISABLED, + IMX_IOMUXC_RGMII_RXC_ALT1_RGMII_RXC= ), + + IMX_PAD_RGMII_RD0_ENET_RGMII_RD0 =3D _IMX_MAKE_PADCFG ( + IMX_SRE_SLOW, + IMX_DSE_40_OHM, + IMX_SPEED_MEDIUM, + IMX_ODE_DISABLE, + IMX_PKE_DISABLE, + IMX_PUE_KEEP, + IMX_PUS_100K_OHM_PD, + IMX_HYS_ENABLED, + IMX_SION_DISABLED, + IMX_IOMUXC_RGMII_RD0_ALT1_RGMII_RD0= ), + + IMX_PAD_RGMII_RD1_ENET_RGMII_RD1 =3D _IMX_MAKE_PADCFG ( + IMX_SRE_SLOW, + IMX_DSE_40_OHM, + IMX_SPEED_MEDIUM, + IMX_ODE_DISABLE, + IMX_PKE_DISABLE, + IMX_PUE_KEEP, + IMX_PUS_100K_OHM_PD, + IMX_HYS_ENABLED, + IMX_SION_DISABLED, + IMX_IOMUXC_RGMII_RD1_ALT1_RGMII_RD1= ), + + IMX_PAD_RGMII_RD2_ENET_RGMII_RD2 =3D _IMX_MAKE_PADCFG ( + IMX_SRE_SLOW, + IMX_DSE_40_OHM, + IMX_SPEED_MEDIUM, + IMX_ODE_DISABLE, + IMX_PKE_DISABLE, + IMX_PUE_KEEP, + IMX_PUS_100K_OHM_PU, + IMX_HYS_ENABLED, + IMX_SION_DISABLED, + IMX_IOMUXC_RGMII_RD2_ALT1_RGMII_RD2= ), + + IMX_PAD_RGMII_RD3_ENET_RGMII_RD3 =3D _IMX_MAKE_PADCFG ( + IMX_SRE_SLOW, + IMX_DSE_40_OHM, + IMX_SPEED_MEDIUM, + IMX_ODE_DISABLE, + IMX_PKE_DISABLE, + IMX_PUE_KEEP, + IMX_PUS_100K_OHM_PU, + IMX_HYS_ENABLED, + IMX_SION_DISABLED, + IMX_IOMUXC_RGMII_RD3_ALT1_RGMII_RD3= ), + + IMX_PAD_RGMII_RX_CTL_RGMII_RX_CTL =3D _IMX_MAKE_PADCFG ( + IMX_SRE_SLOW, + IMX_DSE_40_OHM, + IMX_SPEED_MEDIUM, + IMX_ODE_DISABLE, + IMX_PKE_DISABLE, + IMX_PUE_KEEP, + IMX_PUS_100K_OHM_PD, + IMX_HYS_ENABLED, + IMX_SION_DISABLED, + IMX_IOMUXC_RGMII_RX_CTL_ALT1_RGMII= _RX_CTL), +} IMX_ENET_PADCFG; + +typedef enum { + IMX_PAD_CFG_EIM_DATA22_GPIO3_IO22_USB_OTG_PWR =3D _IMX_MAKE_PADCFG ( + IMX_SRE_SLOW, + IMX_DSE_40_OHM, + IMX_SPEED_MEDIUM, + IMX_ODE_DISABLE, + IMX_PKE_ENABLE, + IMX_PUE_PULL, + IMX_PUS_100K_OHM_PU, + IMX_HYS_ENABLED, + IMX_SION_DISABLED, + IMX_IOMUXC_EIM_D22_ALT= 5_GPIO3_IO22), + + IMX_PAD_CFG_KEY_COL4_USB_OTG_OC =3D _IMX_MAKE_PADCFG_INPSEL ( + IMX_SRE_SLOW, + IMX_DSE_40_OHM, + IMX_SPEED_LOW, + IMX_ODE_DISABLE, + IMX_PKE_ENABLE, + IMX_PUE_PULL, + IMX_PUS_100K_OHM_PU, + IMX_HYS_ENABLED, + IMX_SION_DISABLED, + IMX_IOMUXC_KEY_COL4_ALT2_USB_OTG_OC, + IOMUXC_USB_OTG_OC_SELECT_INPUT, + KEY_COL4_ALT2), + + IMX_PAD_CFG_GPIO0_GPIO1_IO0_USBH1_PWR =3D _IMX_MAKE_PADCFG ( + IMX_SRE_SLOW, + IMX_DSE_40_OHM, + IMX_SPEED_MEDIUM, + IMX_ODE_DISABLE, + IMX_PKE_ENABLE, + IMX_PUE_PULL, + IMX_PUS_100K_OHM_PU, + IMX_HYS_ENABLED, + IMX_SION_DISABLED, + IMX_IOMUXC_GPIO_0_ALT5_GPIO1_I= O00), + + IMX_PAD_CFG_GPIO01_USB_OTG_ID_HOST =3D _IMX_MAKE_PADCFG ( + IMX_SRE_FAST, + IMX_DSE_90_OHM, + IMX_SPEED_MEDIUM, + IMX_ODE_DISABLE, + IMX_PKE_ENABLE, + IMX_PUE_PULL, + IMX_PUS_100K_OHM_PD, + IMX_HYS_ENABLED, + IMX_SION_DISABLED, + IMX_IOMUXC_GPIO_1_ALT3_USB_OTG_ID= ), + + IMX_PAD_CFG_GPIO01_USB_OTG_ID_DEVICE =3D _IMX_MAKE_PADCFG ( + IMX_SRE_FAST, + IMX_DSE_90_OHM, + IMX_SPEED_MEDIUM, + IMX_ODE_DISABLE, + IMX_PKE_ENABLE, + IMX_PUE_PULL, + IMX_PUS_100K_OHM_PU, + IMX_HYS_ENABLED, + IMX_SION_DISABLED, + IMX_IOMUXC_GPIO_1_ALT3_USB_OTG_= ID), +} IMX_EHCI_PADCFG; + +typedef enum { + IMX_PAD_CFG_SD4_DATA3_GPIO2_IO11 =3D _IMX_MAKE_PADCFG ( + IMX_SRE_SLOW, + IMX_DSE_40_OHM, + IMX_SPEED_MEDIUM, + IMX_ODE_DISABLE, + IMX_PKE_ENABLE, + IMX_PUE_PULL, + IMX_PUS_100K_OHM_PU, + IMX_HYS_ENABLED, + IMX_SION_DISABLED, + IMX_IOMUXC_SD4_DAT3_ALT5_GPIO2_IO11= ), +} IMX_IMX6Q_PCIE_PADCFG; + +typedef enum { + IMX_PAD_CFG_EIM_EB3_GPIO2_IO31 =3D _IMX_MAKE_PADCFG ( + IMX_SRE_SLOW, + IMX_DSE_260_OHM, + IMX_SPEED_LOW, + IMX_ODE_DISABLE, + IMX_PKE_DISABLE, + IMX_PUE_PULL, + IMX_PUS_100K_OHM_PU, + IMX_HYS_DISABLED, + IMX_SION_ENABLED, + IMX_IOMUXC_EIM_EB3_ALT5_GPIO2_IO31), + + IMX_PAD_CFG_EIM_D21_I2C1_SCL =3D _IMX_MAKE_PADCFG_INPSEL ( + IMX_SRE_FAST, + IMX_DSE_40_OHM, + IMX_SPEED_MEDIUM, + IMX_ODE_ENABLE, + IMX_PKE_ENABLE, + IMX_PUE_PULL, + IMX_PUS_47K_OHM_PU, + IMX_HYS_ENABLED, + IMX_SION_ENABLED, + IMX_IOMUXC_EIM_D21_ALT6_I2C1_SCL, + IOMUXC_I2C1_SCL_IN_SELECT_INPUT, + EIM_DATA21_ALT6), + + IMX_PAD_CFG_EIM_D28_I2C1_SDA =3D _IMX_MAKE_PADCFG_INPSEL ( + IMX_SRE_FAST, + IMX_DSE_40_OHM, + IMX_SPEED_MEDIUM, + IMX_ODE_ENABLE, + IMX_PKE_ENABLE, + IMX_PUE_PULL, + IMX_PUS_47K_OHM_PU, + IMX_HYS_ENABLED, + IMX_SION_ENABLED, + IMX_IOMUXC_EIM_D28_ALT1_I2C1_SDA, + IOMUXC_I2C1_SDA_IN_SELECT_INPUT, + EIM_DATA28_ALT1), + + IMX_PAD_CFG_EIM_D17_I2C3_SCL =3D _IMX_MAKE_PADCFG_INPSEL ( + IMX_SRE_FAST, + IMX_DSE_40_OHM, + IMX_SPEED_MEDIUM, + IMX_ODE_ENABLE, + IMX_PKE_ENABLE, + IMX_PUE_PULL, + IMX_PUS_47K_OHM_PU, + IMX_HYS_ENABLED, + IMX_SION_ENABLED, + IMX_IOMUXC_EIM_D17_ALT6_I2C3_SCL, + IOMUXC_I2C3_SCL_IN_SELECT_INPUT, + EIM_DATA17_ALT6), + + IMX_PAD_CFG_EIM_D18_I2C3_SDA =3D _IMX_MAKE_PADCFG_INPSEL ( + IMX_SRE_FAST, + IMX_DSE_40_OHM, + IMX_SPEED_MEDIUM, + IMX_ODE_ENABLE, + IMX_PKE_ENABLE, + IMX_PUE_PULL, + IMX_PUS_47K_OHM_PU, + IMX_HYS_ENABLED, + IMX_SION_ENABLED, + IMX_IOMUXC_EIM_D18_ALT6_I2C3_SDA, + IOMUXC_I2C3_SDA_IN_SELECT_INPUT, + EIM_DATA18_ALT6), +} IMX_I2C_PADCFG; + +typedef enum { + IMX_PAD_CFG_GPIO_5_CCM_CLKO1 =3D _IMX_MAKE_PADCFG ( + IMX_SRE_SLOW, + IMX_DSE_40_OHM, + IMX_SPEED_MEDIUM, + IMX_ODE_DISABLE, + IMX_PKE_ENABLE, + IMX_PUE_PULL, + IMX_PUS_100K_OHM_PU, + IMX_HYS_ENABLED, + IMX_SION_DISABLED, + IMX_IOMUXC_GPIO_5_ALT3_CCM_CLKO1), + + IMX_PAD_CFG_KEY_COL0_AUD5_TXC =3D _IMX_MAKE_PADCFG_INPSEL ( + IMX_SRE_SLOW, + IMX_DSE_40_OHM, + IMX_SPEED_MEDIUM, + IMX_ODE_DISABLE, + IMX_PKE_ENABLE, + IMX_PUE_PULL, + IMX_PUS_100K_OHM_PU, + IMX_HYS_ENABLED, + IMX_SION_DISABLED, + IMX_IOMUXC_KEY_COL0_ALT2_AUD5_TXC, + IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INP= UT, + KEY_COL0_ALT2), + + IMX_PAD_CFG_KEY_ROW0_AUD5_TXD =3D _IMX_MAKE_PADCFG_INPSEL ( + IMX_SRE_SLOW, + IMX_DSE_40_OHM, + IMX_SPEED_MEDIUM, + IMX_ODE_DISABLE, + IMX_PKE_ENABLE, + IMX_PUE_PULL, + IMX_PUS_100K_OHM_PU, + IMX_HYS_ENABLED, + IMX_SION_DISABLED, + IMX_IOMUXC_KEY_ROW0_ALT2_AUD5_TXD, + IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT, + KEY_ROW0_ALT2), + + IMX_PAD_CFG_KEY_COL1_AUD5_TXFS =3D _IMX_MAKE_PADCFG_INPSEL ( + IMX_SRE_SLOW, + IMX_DSE_40_OHM, + IMX_SPEED_MEDIUM, + IMX_ODE_DISABLE, + IMX_PKE_ENABLE, + IMX_PUE_PULL, + IMX_PUS_100K_OHM_PU, + IMX_HYS_ENABLED, + IMX_SION_DISABLED, + IMX_IOMUXC_KEY_COL1_ALT2_AUD5_TXFS, + IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INP= UT, + KEY_COL1_ALT2), + + IMX_PAD_CFG_DISP0_DAT19_AUD5_RXD =3D _IMX_MAKE_PADCFG_INPSEL ( + IMX_SRE_SLOW, + IMX_DSE_40_OHM, + IMX_SPEED_MEDIUM, + IMX_ODE_DISABLE, + IMX_PKE_ENABLE, + IMX_PUE_PULL, + IMX_PUS_100K_OHM_PU, + IMX_HYS_ENABLED, + IMX_SION_DISABLED, + IMX_IOMUXC_DISP0_DAT19_ALT3_AUD5_RX= D, + IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INP= UT, + DISP0_DATA19_ALT3), +} IMX_AUDIO_PADCFG; + +typedef enum { + IMX_USDHC_CMD_PAD_CTL =3D _IMX_MAKE_PAD_CTL ( + IMX_SRE_FAST, + IMX_DSE_33_OHM, + IMX_SPEED_MEDIUM, + IMX_ODE_DISABLE, + IMX_PKE_ENABLE, + IMX_PUE_PULL, + IMX_PUS_47K_OHM_PU, + IMX_HYS_ENABLED), + + IMX_USDHC_CLK_PAD_CTL =3D _IMX_MAKE_PAD_CTL ( + IMX_SRE_FAST, + IMX_DSE_33_OHM, + IMX_SPEED_MEDIUM, + IMX_ODE_DISABLE, + IMX_PKE_DISABLE, + 0, + 0, + IMX_HYS_ENABLED), + + IMX_USDHC_DAT_PAD_CTL =3D _IMX_MAKE_PAD_CTL ( + IMX_SRE_FAST, + IMX_DSE_33_OHM, + IMX_SPEED_MEDIUM, + IMX_ODE_DISABLE, + IMX_PKE_ENABLE, + IMX_PUE_PULL, + IMX_PUS_47K_OHM_PU, + IMX_HYS_ENABLED), + + IMX_USDHC_GPIO_PAD_CTL =3D _IMX_MAKE_PAD_CTL ( + IMX_SRE_FAST, + IMX_DSE_33_OHM, + IMX_SPEED_LOW, + IMX_ODE_DISABLE, + IMX_PKE_DISABLE, + 0, + 0, + IMX_HYS_ENABLED), + + IMX_USDHC_CD_PAD_CTL =3D _IMX_MAKE_PAD_CTL ( + IMX_SRE_FAST, + IMX_DSE_33_OHM, + IMX_SPEED_LOW, + IMX_ODE_DISABLE, + IMX_PKE_ENABLE, + IMX_PUE_PULL, + IMX_PUS_47K_OHM_PU, + IMX_HYS_ENABLED), + + IMX_PAD_CFG_SD2_CLK_SD2_CLK =3D _IMX_MAKE_PADCFG2 ( + IMX_USDHC_CLK_PAD_CTL, + IMX_SION_DISABLED, + IMX_IOMUXC_SD2_CLK_ALT0_SD2_CLK), + + IMX_PAD_CFG_SD2_CMD_SD2_CMD =3D _IMX_MAKE_PADCFG2 ( + IMX_USDHC_CMD_PAD_CTL, + IMX_SION_DISABLED, + IMX_IOMUXC_SD2_CMD_ALT0_SD2_CMD), + + IMX_PAD_CFG_SD2_DAT0_SD2_DATA0 =3D _IMX_MAKE_PADCFG2 ( + IMX_USDHC_DAT_PAD_CTL, + IMX_SION_DISABLED, + IMX_IOMUXC_SD2_DAT0_ALT0_SD2_DATA0), + + IMX_PAD_CFG_SD2_DAT1_SD2_DATA1 =3D _IMX_MAKE_PADCFG2 ( + IMX_USDHC_DAT_PAD_CTL, + IMX_SION_DISABLED, + IMX_IOMUXC_SD2_DAT1_ALT0_SD2_DATA1), + + IMX_PAD_CFG_SD2_DAT2_SD2_DATA2 =3D _IMX_MAKE_PADCFG2 ( + IMX_USDHC_DAT_PAD_CTL, + IMX_SION_DISABLED, + IMX_IOMUXC_SD2_DAT2_ALT0_SD2_DATA2), + + IMX_PAD_CFG_SD2_DAT3_SD2_DATA3 =3D _IMX_MAKE_PADCFG2 ( + IMX_USDHC_DAT_PAD_CTL, + IMX_SION_DISABLED, + IMX_IOMUXC_SD2_DAT3_ALT0_SD2_DATA3), + + IMX_PAD_CFG_KEY_ROW1_SD2_VSELECT =3D _IMX_MAKE_PADCFG2 ( + IMX_USDHC_GPIO_PAD_CTL, + IMX_SION_DISABLED, + IMX_IOMUXC_KEY_ROW1_ALT6_SD2_VSELEC= T), + + IMX_PAD_CFG_GPIO_4_SD2_CD_B =3D _IMX_MAKE_PADCFG2 ( + IMX_USDHC_CD_PAD_CTL, + IMX_SION_DISABLED, + IMX_IOMUXC_GPIO_4_ALT6_SD2_CD_B), + + IMX_PAD_CFG_DISP0_DAT9_GPIO4_IO30 =3D _IMX_MAKE_PADCFG2 ( + IMX_USDHC_GPIO_PAD_CTL, + IMX_SION_DISABLED, + IMX_IOMUXC_DISP0_DAT9_ALT5_GPIO4_I= O30), +} IMX_USDHC2_PADCFG; + +typedef enum { + IMX_PAD_CFG_SD3_CLK_SD3_CLK =3D _IMX_MAKE_PADCFG2 ( + IMX_USDHC_CLK_PAD_CTL, + IMX_SION_DISABLED, + IMX_IOMUXC_SD3_CLK_ALT0_SD3_CLK), + + IMX_PAD_CFG_SD3_CMD_SD3_CMD =3D _IMX_MAKE_PADCFG2 ( + IMX_USDHC_CMD_PAD_CTL, + IMX_SION_DISABLED, + IMX_IOMUXC_SD3_CMD_ALT0_SD3_CMD), + + IMX_PAD_CFG_SD3_RST_SD3_RST =3D _IMX_MAKE_PADCFG2 ( + IMX_USDHC_GPIO_PAD_CTL, + IMX_SION_DISABLED, + IMX_IOMUXC_SD3_RST_ALT0_SD3_RESET), + + IMX_PAD_CFG_SD3_DAT0_SD3_DATA0 =3D _IMX_MAKE_PADCFG2 ( + IMX_USDHC_DAT_PAD_CTL, + IMX_SION_DISABLED, + IMX_IOMUXC_SD3_DAT0_ALT0_SD3_DATA0), + + IMX_PAD_CFG_SD3_DAT1_SD3_DATA1 =3D _IMX_MAKE_PADCFG2 ( + IMX_USDHC_DAT_PAD_CTL, + IMX_SION_DISABLED, + IMX_IOMUXC_SD3_DAT1_ALT0_SD3_DATA1), + + IMX_PAD_CFG_SD3_DAT2_SD3_DATA2 =3D _IMX_MAKE_PADCFG2 ( + IMX_USDHC_DAT_PAD_CTL, + IMX_SION_DISABLED, + IMX_IOMUXC_SD3_DAT2_ALT0_SD3_DATA2), + + IMX_PAD_CFG_SD3_DAT3_SD3_DATA3 =3D _IMX_MAKE_PADCFG2 ( + IMX_USDHC_DAT_PAD_CTL, + IMX_SION_DISABLED, + IMX_IOMUXC_SD3_DAT3_ALT0_SD3_DATA3), + + IMX_PAD_CFG_SD3_DAT4_SD3_DATA4 =3D _IMX_MAKE_PADCFG2 ( + IMX_USDHC_DAT_PAD_CTL, + IMX_SION_DISABLED, + IMX_IOMUXC_SD3_DAT4_ALT0_SD3_DATA4), + + IMX_PAD_CFG_SD3_DAT5_SD3_DATA5 =3D _IMX_MAKE_PADCFG2 ( + IMX_USDHC_DAT_PAD_CTL, + IMX_SION_DISABLED, + IMX_IOMUXC_SD3_DAT5_ALT0_SD3_DATA5), + + IMX_PAD_CFG_SD3_DAT6_SD3_DATA6 =3D _IMX_MAKE_PADCFG2 ( + IMX_USDHC_DAT_PAD_CTL, + IMX_SION_DISABLED, + IMX_IOMUXC_SD3_DAT6_ALT0_SD3_DATA6), + + IMX_PAD_CFG_SD3_DAT7_SD3_DATA7 =3D _IMX_MAKE_PADCFG2 ( + IMX_USDHC_DAT_PAD_CTL, + IMX_SION_DISABLED, + IMX_IOMUXC_SD3_DAT7_ALT0_SD3_DATA7), +} IMX_USDHC3_PADCFG; + +typedef enum { + IMX_PWM_CLK_PAD_CTL =3D _IMX_MAKE_PAD_CTL ( + IMX_SRE_FAST, + IMX_DSE_33_OHM, + IMX_SPEED_LOW, + IMX_ODE_DISABLE, + IMX_PKE_DISABLE, + 0, + 0, + IMX_HYS_ENABLED), + + IMX_PAD_CFG_DISP0_DAT8_PWM1_OUT =3D _IMX_MAKE_PADCFG2 ( + IMX_PWM_CLK_PAD_CTL, + IMX_SION_DISABLED, + IMX_IOMUXC_DISP0_DAT8_ALT2_PWM1_OUT)= , +} IMX_PWM_PADCFG; + +typedef enum { + IMX_PAD_UART1_RX_DATA =3D _IMX_MAKE_PADCFG_INPSEL ( + IMX_SRE_SLOW, + IMX_DSE_40_OHM, // 25 Ohm @ 3.3V, 40 Ohm @= 1.8V + IMX_SPEED_MEDIUM, // 10 MEDIUM - 100, 150 MH= z + IMX_ODE_DISABLE, + IMX_PKE_ENABLE, // 12 Pull/Keeper Enable= d + IMX_PUE_PULL, // 13 Pull Enabled + IMX_PUS_100K_OHM_PU, // 14-15 100K Ohm Pull U= p + IMX_HYS_ENABLED, + IMX_SION_DISABLED, + IMX_IOMUXC_CSI0_DAT11_ALT3_UART1_RX_DATA, + IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, + CSI0_DATA11_ALT3), + + IMX_PAD_UART1_TX_DATA =3D _IMX_MAKE_PADCFG ( + IMX_SRE_SLOW, + IMX_DSE_40_OHM, + IMX_SPEED_MEDIUM, + IMX_ODE_DISABLE, + IMX_PKE_ENABLE, + IMX_PUE_PULL, + IMX_PUS_100K_OHM_PU, + IMX_HYS_ENABLED, + IMX_SION_DISABLED, + IMX_IOMUXC_CSI0_DAT10_ALT3_UART1_TX_DATA), + + IMX_PAD_UART3_RX_DATA =3D _IMX_MAKE_PADCFG_INPSEL ( + IMX_SRE_SLOW, + IMX_DSE_40_OHM, + IMX_SPEED_MEDIUM, + IMX_ODE_DISABLE, + IMX_PKE_ENABLE, + IMX_PUE_PULL, + IMX_PUS_100K_OHM_PU, + IMX_HYS_ENABLED, + IMX_SION_DISABLED, + IMX_IOMUXC_EIM_D25_ALT2_UART3_RX_DATA, + IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT, + EIM_DATA25_ALT2), + + IMX_PAD_UART3_TX_DATA =3D _IMX_MAKE_PADCFG ( + IMX_SRE_SLOW, + IMX_DSE_40_OHM, + IMX_SPEED_MEDIUM, + IMX_ODE_DISABLE, + IMX_PKE_ENABLE, + IMX_PUE_PULL, + IMX_PUS_100K_OHM_PU, + IMX_HYS_ENABLED, + IMX_SION_DISABLED, + IMX_IOMUXC_EIM_D24_ALT2_UART3_TX_DATA), +} IMX_UART_PADCFG; + +typedef enum { + IMX_PAD_CFG_SD4_DATA1_GPIO2_IO09 =3D _IMX_MAKE_PADCFG ( + IMX_SRE_SLOW, + IMX_DSE_40_OHM, + IMX_SPEED_MEDIUM, + IMX_ODE_DISABLE, + IMX_PKE_ENABLE, + IMX_PUE_PULL, + IMX_PUS_100K_OHM_PU, + IMX_HYS_ENABLED, + IMX_SION_DISABLED, + IMX_IOMUXC_SD4_DAT1_ALT5_GPIO2_IO09= ), + +} IMX_IMX6Q_LDB_PADCFG; + +#endif /* _IMX6_BOARD_INIT_H_ */ diff --git a/Platform/SolidRun/HummingBoardEdge_iMX6Q_2GB/Library/iMX6Board= Lib/iMX6BoardLib.inf b/Platform/SolidRun/HummingBoardEdge_iMX6Q_2GB/Library= /iMX6BoardLib/iMX6BoardLib.inf new file mode 100644 index 000000000000..687b9a59930d --- /dev/null +++ b/Platform/SolidRun/HummingBoardEdge_iMX6Q_2GB/Library/iMX6BoardLib/iMX= 6BoardLib.inf @@ -0,0 +1,91 @@ +#/* @file +# +# Copyright (c) 2018 Microsoft Corporation. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +#*/ + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D iMX6BoardLib + FILE_GUID =3D 736343a0-1d96-11e0-aaaa-0002a5d5c51b + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmPlatformLib + DEFINE BOARD_LIB_COMMON_DIR =3D Silicon/NXP/iMX6Pkg/Library/iMX6Board= Lib + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Platform/Microsoft/OpteeClientPkg/OpteeClientPkg.dec + Silicon/NXP/iMX6Pkg/iMX6Pkg.dec + Silicon/NXP/iMXPlatformPkg/iMXPlatformPkg.dec + +[LibraryClasses] + ArmLib + iMX6ClkPwrLib + iMX6UsbPhyLib + IoLib + MemoryAllocationLib + SerialPortLib + +[Sources.common] + $(BOARD_LIB_COMMON_DIR)/iMX6BoardHelper.S | GCC + $(BOARD_LIB_COMMON_DIR)/iMX6BoardMem.c + $(BOARD_LIB_COMMON_DIR)/iMX6QBoardCoreDef.c + iMX6BoardInit.c + +[FeaturePcd] + giMX6TokenSpaceGuid.PcdGpuEnable + giMX6TokenSpaceGuid.PcdLvdsEnable + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmPrimaryCore + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + gArmTokenSpaceGuid.PcdFdBaseAddress + gArmTokenSpaceGuid.PcdFdSize + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + + gArmPlatformTokenSpaceGuid.PcdCoreCount + + giMX6TokenSpaceGuid.PcdFrameBufferBase + giMX6TokenSpaceGuid.PcdFrameBufferSize + giMX6TokenSpaceGuid.PcdSrcBase + + giMXPlatformTokenSpaceGuid.PcdGpioBankMemoryRange + + # + # TPM2 control area + # + gOpteeClientPkgTokenSpaceGuid.PcdTpm2AcpiBufferBase + gOpteeClientPkgTokenSpaceGuid.PcdTpm2AcpiBufferSize + + # + # TrustZone private memory + # This memory is managed privately by the OpTEE OS. + # It must match OpTEE optee_os/core/arch/arm/plat-imx/platform_config.h: + # CFG_DDR_TEETZ_RESERVED_START & CFG_DDR_TEETZ_RESERVED_START + # + gOpteeClientPkgTokenSpaceGuid.PcdTrustZonePrivateMemoryBase + gOpteeClientPkgTokenSpaceGuid.PcdTrustZonePrivateMemorySize + + # + # TrustZone shared memory + # This memory is manager by the normal world but shared with the OpTEE O= S. + # It must match OpTEE optee_os/core/arch/arm/plat-imx/platform_config.h: + # CFG_SHMEM_START & CFG_SHMEM_SIZE + # + gOpteeClientPkgTokenSpaceGuid.PcdTrustZoneSharedMemoryBase + gOpteeClientPkgTokenSpaceGuid.PcdTrustZoneSharedMemorySize --=20 2.16.2.gvfs.1.33.gf5370f1