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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable This adds support for interact with the UART controller on NXP i.MX platforms. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Christopher Co Cc: Ard Biesheuvel Cc: Leif Lindholm Cc: Michael D Kinney --- Silicon/NXP/iMXPlatformPkg/Include/iMXUart.h = | 207 +++++++++++++++++ Silicon/NXP/iMXPlatformPkg/Library/UartSerialPortLib/UartSerialPortLib.c = | 243 ++++++++++++++++++++ Silicon/NXP/iMXPlatformPkg/Library/UartSerialPortLib/UartSerialPortLib.inf= | 41 ++++ 3 files changed, 491 insertions(+) diff --git a/Silicon/NXP/iMXPlatformPkg/Include/iMXUart.h b/Silicon/NXP/iMX= PlatformPkg/Include/iMXUart.h new file mode 100644 index 000000000000..ddb61f59c656 --- /dev/null +++ b/Silicon/NXP/iMXPlatformPkg/Include/iMXUart.h @@ -0,0 +1,207 @@ +/** @file +* +* Copyright (c) 2018 Microsoft Corporation. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#ifndef _IMXUART_H_ +#define _IMXUART_H_ + +// UART Receiver Register bit definitions +enum MX6UART_RXD { + MX6UART_RXD_RX_DATA_MASK =3D (0xff << 0), + MX6UART_RXD_PRERR =3D (1 << 10), + MX6UART_RXD_BRK =3D (1 << 11), + MX6UART_RXD_FRMERR =3D (1 << 12), + MX6UART_RXD_OVRRUN =3D (1 << 13), + MX6UART_RXD_ERR =3D (1 << 14), + MX6UART_RXD_CHARRDY =3D (1 << 15), +}; + +// UART Control Register 1 bit definitions +enum MX6UART_UCR1 { + MX6UART_UCR1_UARTEN =3D (1 << 0), + MX6UART_UCR1_DOZE =3D (1 << 1), + MX6UART_UCR1_ATDMAEN =3D (1 << 2), + MX6UART_UCR1_TXDMAEN =3D (1 << 3), + MX6UART_UCR1_SNDBRK =3D (1 << 4), + MX6UART_UCR1_RTSDEN =3D (1 << 5), + MX6UART_UCR1_TXMPTYEN =3D (1 << 6), + MX6UART_UCR1_IREN =3D (1 << 7), + MX6UART_UCR1_RXDMAEN =3D (1 << 8), + MX6UART_UCR1_RRDYEN =3D (1 << 9), + MX6UART_UCR1_ICD_MASK =3D (3 << 10), + MX6UART_UCR1_ICD_4 =3D (0 << 10), + MX6UART_UCR1_ICD_8 =3D (1 << 10), + MX6UART_UCR1_ICD_16 =3D (2 << 10), + MX6UART_UCR1_ICD_32 =3D (3 << 10), + MX6UART_UCR1_IDEN =3D (1 << 12), + MX6UART_UCR1_TRDYEN =3D (1 << 13), + MX6UART_UCR1_ADBR =3D (1 << 14), + MX6UART_UCR1_ADEN =3D (1 << 15), +}; + +// UART Control Register 2 bit definitions +enum MX6UART_UCR2 { + MX6UART_UCR2_SRST =3D (1 << 0), + MX6UART_UCR2_RXEN =3D (1 << 1), + MX6UART_UCR2_TXEN =3D (1 << 2), + MX6UART_UCR2_ATEN =3D (1 << 3), + MX6UART_UCR2_RTSEN =3D (1 << 4), + MX6UART_UCR2_WS =3D (1 << 5), + MX6UART_UCR2_STPB =3D (1 << 6), + MX6UART_UCR2_PROE =3D (1 << 7), + MX6UART_UCR2_PREN =3D (1 << 8), + MX6UART_UCR2_RTEC_MASK =3D (3 << 9), + MX6UART_UCR2_RTEC_RISING =3D (0 << 9), + MX6UART_UCR2_RTEC_FALLING =3D (1 << 9), + MX6UART_UCR2_RTEC_BOTH =3D (2 << 9), + MX6UART_UCR2_ESCEN =3D (1 << 11), + MX6UART_UCR2_CTS =3D (1 << 12), + MX6UART_UCR2_CTSC =3D (1 << 13), + MX6UART_UCR2_IRTS =3D (1 << 14), + MX6UART_UCR2_ESCI =3D (1 << 15), +}; + +// UART Control Register 3 bit definitions +enum MX6UART_UCR3 { + MX6UART_UCR3_ACIEN =3D (1 << 0), + MX6UART_UCR3_INVT =3D (1 << 1), + MX6UART_UCR3_RXDMUXSEL =3D (1 << 2), + MX6UART_UCR3_DTRDEN =3D (1 << 3), + MX6UART_UCR3_AWAKEN =3D (1 << 4), + MX6UART_UCR3_AIRINTEN =3D (1 << 5), + MX6UART_UCR3_RXDSEN =3D (1 << 6), + MX6UART_UCR3_ADNIMP =3D (1 << 7), + MX6UART_UCR3_RI =3D (1 << 8), + MX6UART_UCR3_DCD =3D (1 << 9), + MX6UART_UCR3_DSR =3D (1 << 10), + MX6UART_UCR3_FRAERREN =3D (1 << 11), + MX6UART_UCR3_PARERREN =3D (1 << 12), + MX6UART_UCR3_DTREN =3D (1 << 13), + MX6UART_UCR3_DPEC_MASK =3D (3 << 14), + MX6UART_UCR3_DPEC_RISING =3D (0 << 14), + MX6UART_UCR3_DPEC_FALLING =3D (1 << 14), + MX6UART_UCR3_DPEC_BOTH =3D (2 << 14), +}; + +// UART Control Register 4 bit definitions +enum MX6UART_UCR4 { + MX6UART_UCR4_DREN =3D (1 << 0), + MX6UART_UCR4_OREN =3D (1 << 1), + MX6UART_UCR4_BKEN =3D (1 << 2), + MX6UART_UCR4_TCEN =3D (1 << 3), + MX6UART_UCR4_LPBYP =3D (1 << 4), + MX6UART_UCR4_IRSC =3D (1 << 5), + MX6UART_UCR4_IDDMAEN =3D (1 << 6), + MX6UART_UCR4_WKEN =3D (1 << 7), + MX6UART_UCR4_ENIRI =3D (1 << 8), + MX6UART_UCR4_INVR =3D (1 << 9), + MX6UART_UCR4_CTSTL_MASK =3D (0x3f << 10), + MX6UART_UCR4_CTSTL_SHIFT =3D 10, +}; + +// UART FIFO Control Register bit definitions +enum MX6UART_UFCR { + MX6UART_UFCR_RXTL_MASK =3D (0x3f << 0), + MX6UART_UFCR_RXTL_SHIFT =3D 0, + MX6UART_UFCR_DCEDTE =3D (1 << 6), + MX6UART_UFCR_RFDIV_MASK =3D (7 << 7), + MX6UART_UFCR_RFDIV_6 =3D (0 << 7), + MX6UART_UFCR_RFDIV_5 =3D (1 << 7), + MX6UART_UFCR_RFDIV_4 =3D (2 << 7), + MX6UART_UFCR_RFDIV_3 =3D (3 << 7), + MX6UART_UFCR_RFDIV_2 =3D (4 << 7), + MX6UART_UFCR_RFDIV_1 =3D (5 << 7), + MX6UART_UFCR_RFDIV_7 =3D (6 << 7), + MX6UART_UFCR_TXTL_MASK =3D (0x3f << 10), + MX6UART_UFCR_TXTL_SHIFT =3D 10, +}; + +// UART Status Register 1 bit definitions +enum MX6UART_USR1 { + MX6UART_USR1_SAD =3D (1 << 3), + MX6UART_USR1_AWAKE =3D (1 << 4), + MX6UART_USR1_AIRINT =3D (1 << 5), + MX6UART_USR1_RXDS =3D (1 << 6), + MX6UART_USR1_DTRD =3D (1 << 7), + MX6UART_USR1_AGTIM =3D (1 << 8), + MX6UART_USR1_RRDY =3D (1 << 9), + MX6UART_USR1_FRAMERR =3D (1 << 10), + MX6UART_USR1_ESCF =3D (1 << 11), + MX6UART_USR1_RTSD =3D (1 << 12), + MX6UART_USR1_TRDY =3D (1 << 13), + MX6UART_USR1_RTSS =3D (1 << 14), + MX6UART_USR1_PARITYERR =3D (1 << 15), +}; + +// UART Status Register 2 bit definitions +enum MX6UART_USR2 { + MX6UART_USR2_RDR =3D (1 << 0), + MX6UART_USR2_ORE =3D (1 << 1), + MX6UART_USR2_BRCD =3D (1 << 2), + MX6UART_USR2_TXDC =3D (1 << 3), + MX6UART_USR2_RTSF =3D (1 << 4), + MX6UART_USR2_DCDIN =3D (1 << 5), + MX6UART_USR2_DCDDELT =3D (1 << 6), + MX6UART_USR2_WAKE =3D (1 << 7), + MX6UART_USR2_IRINT =3D (1 << 8), + MX6UART_USR2_RIIN =3D (1 << 9), + MX6UART_USR2_RIDLET =3D (1 << 10), + MX6UART_USR2_ACST =3D (1 << 11), + MX6UART_USR2_IDLE =3D (1 << 12), + MX6UART_USR2_DTRF =3D (1 << 13), + MX6UART_USR2_TXFE =3D (1 << 14), + MX6UART_USR2_ADET =3D (1 << 15), +}; + +// UART Test Register bit definitions +enum MX6UART_UTS { + MX6UART_UTS_SOFTRST =3D (1 << 0), + MX6UART_UTS_RXFULL =3D (1 << 3), + MX6UART_UTS_TXFULL =3D (1 << 4), + MX6UART_UTS_RXEMPTY =3D (1 << 5), + MX6UART_UTS_TXEMPTY =3D (1 << 6), + MX6UART_UTS_RXDBG =3D (1 << 9), + MX6UART_UTS_LOOPIR =3D (1 << 10), + MX6UART_UTS_DBGEN =3D (1 << 11), + MX6UART_UTS_LOOP =3D (1 << 12), + MX6UART_UTS_FRCPERR =3D (1 << 13), +}; + +// Size of RX and TX FIFOs +enum { + MX6UART_FIFO_COUNT =3D 32 +}; + +typedef struct _MX6UART_REGISTERS { + UINT32 Rxd; // 0x00: UART Receiver Register + UINT32 reserved1[15]; + UINT32 Txd; // 0x40: UART Transmitter Register + UINT32 reserved2[15]; + UINT32 Ucr1; // 0x80: UART Control Register 1 + UINT32 Ucr2; // 0x84: UART Control Register 2 + UINT32 Ucr3; // 0x88: UART Control Register 3 + UINT32 Ucr4; // 0x8C: UART Control Register 4 + UINT32 Ufcr; // 0x90: UART FIFO Control Register + UINT32 Usr1; // 0x94: UART Status Register 1 + UINT32 Usr2; // 0x98: UART Status Register 2 + UINT32 Uesc; // 0x9C: UART Escape Character Register + UINT32 Utim; // 0xA0: UART Escape Timer Register + UINT32 Ubir; // 0xA4: UART BRM Incremental Register + UINT32 Ubmr; // 0xA8: UART BRM Modulator Register (UART1= _UBMR) + UINT32 Ubrc; // 0xAC: UART Baud Rate Count Register + UINT32 Onems; // 0xB0: UART One Millisecond Register + UINT32 Uts; // 0xB4: UART Test Register + UINT32 Umcr; // 0xB8: UART RS-485 Mode Control Register +} MX6UART_REGISTERS; + +#endif // _IMXUART_H_ diff --git a/Silicon/NXP/iMXPlatformPkg/Library/UartSerialPortLib/UartSeria= lPortLib.c b/Silicon/NXP/iMXPlatformPkg/Library/UartSerialPortLib/UartSeria= lPortLib.c new file mode 100644 index 000000000000..fbe24d98c6aa --- /dev/null +++ b/Silicon/NXP/iMXPlatformPkg/Library/UartSerialPortLib/UartSerialPortLi= b.c @@ -0,0 +1,243 @@ +/** @file + + Copyright (c) 2006 - 2008, Intel Corporation + Copyright (c) 2018 Microsoft Corporation. All rights reserved. + + All rights reserved. This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include + + +/** + Initialize the serial device hardware. + + If no initialization is required, then return RETURN_SUCCESS. + If the serial device was successfully initialized, then return RETURN_SU= CCESS. + If the serial device could not be initialized, then return RETURN_DEVICE= _ERROR. + + @retval RETURN_SUCCESS The serial device was initialized. + @retval RETURN_DEVICE_ERROR The serial device could not be initialized= . + +**/ +RETURN_STATUS +EFIAPI +SerialPortInitialize ( + VOID + ) +{ + MX6UART_REGISTERS *UartBase; + UINT32 Ucr1; + + UartBase =3D (MX6UART_REGISTERS*)FixedPcdGet32 (PcdSerialRegisterBase); + + Ucr1 =3D MmioRead32 ((UINTN)&UartBase->Ucr1); + if ((Ucr1 & MX6UART_UCR1_UARTEN) =3D=3D 0) { + // UART should have been initialized by previous boot stage + return RETURN_DEVICE_ERROR; + } + + return RETURN_SUCCESS; +} + +/** + Write data from buffer to serial device. + + Writes NumberOfBytes data bytes from Buffer to the serial device. + The number of bytes actually written to the serial device is returned. + If the return value is less than NumberOfBytes, then the write operation= failed. + If Buffer is NULL, then ASSERT(). + If NumberOfBytes is zero, then return 0. + + @param Buffer Pointer to the data buffer to be written. + @param NumberOfBytes Number of bytes to written to the serial device= . + + @retval 0 NumberOfBytes is 0. + @retval >0 The number of bytes written to the serial devic= e. + If this value is less than NumberOfBytes, then = the + read operation failed. + +**/ +UINTN +EFIAPI +SerialPortWrite ( + IN UINT8 *Buffer, + IN UINTN NumberOfBytes + ) +{ + MX6UART_REGISTERS *UartBase; + UINTN BytesSent; + + UartBase =3D (MX6UART_REGISTERS*)FixedPcdGet32 (PcdSerialRegisterBase); + BytesSent =3D 0; + while (BytesSent < NumberOfBytes) { + // Check if FIFO is full and wait if it is. + while ((MmioRead32 ((UINTN)&UartBase->Uts) & MX6UART_UTS_TXFULL) !=3D = 0); + MmioWrite32 ((UINTN)&UartBase->Txd, Buffer[BytesSent]); + BytesSent++; + } + + return BytesSent; +} + +/** + Read data from serial device and save the datas in buffer. + + Reads NumberOfBytes data bytes from a serial device into the buffer + specified by Buffer. The number of bytes actually read is returned. + If the return value is less than NumberOfBytes, then the rest operation = failed. + If Buffer is NULL, then ASSERT(). + If NumberOfBytes is zero, then return 0. + + @param Buffer Pointer to the data buffer to store the data r= ead + from the serial device. + @param NumberOfBytes Number of bytes which will be read. + + @retval 0 Read data failed, No data is to be read. + @retval >0 Actual number of bytes read from serial device= . + +**/ +UINTN +EFIAPI +SerialPortRead ( + OUT UINT8 *Buffer, + IN UINTN NumberOfBytes + ) +{ + MX6UART_REGISTERS *UartBase; + UINTN BytesRead; + UINT32 Rxd; + + UartBase =3D (MX6UART_REGISTERS*)FixedPcdGet32 (PcdSerialRegisterBase); + BytesRead =3D 0; + while (BytesRead < NumberOfBytes) { + Rxd =3D MmioRead32 ((UINTN)&UartBase->Rxd); + if ((Rxd & MX6UART_RXD_CHARRDY) =3D=3D 0) { + break; + } + + Buffer[BytesRead] =3D (UINT8) (Rxd & MX6UART_RXD_RX_DATA_MASK); + BytesRead++; + } + + return BytesRead; +} + +/** + Polls a serial device to see if there is any data waiting to be read. + + Polls a serial device to see if there is any data waiting to be read. + If there is data waiting to be read from the serial device, then TRUE is + returned. + If there is no data waiting to be read from the serial device, then FALS= E is + returned. + + @retval TRUE Data is waiting to be read from the serial device. + @retval FALSE There is no data waiting to be read from the seria= l device. + +**/ +BOOLEAN +EFIAPI +SerialPortPoll ( + VOID + ) +{ + MX6UART_REGISTERS *UartBase; + UINT32 Usr2; + + UartBase =3D (MX6UART_REGISTERS*)FixedPcdGet32 (PcdSerialRegisterBase); + Usr2 =3D MmioRead32 ((UINTN)&UartBase->Usr2); + return (Usr2 & MX6UART_USR2_RDR) !=3D 0; +} + +/** + Sets the control bits on a serial device. + + @param Control Sets the bits of Control that are settable= . + + @retval RETURN_UNSUPPORTED The serial device does not support this op= eration. + +**/ +RETURN_STATUS +EFIAPI +SerialPortSetControl ( + IN UINT32 Control + ) +{ + return RETURN_UNSUPPORTED; +} + +/** + Retrieve the status of the control bits on a serial device. + + @param Control A pointer to return the current control si= gnals + from the serial device. + + @retval RETURN_UNSUPPORTED The serial device does not support this op= eration. + +**/ +RETURN_STATUS +EFIAPI +SerialPortGetControl ( + OUT UINT32 *Control + ) +{ + return RETURN_UNSUPPORTED; +} + +/** + Sets the baud rate, receive FIFO depth, transmit/receice time out, parit= y, + data bits, and stop bits on a serial device. + + @param BaudRate The requested baud rate. A BaudRate value of 0= will + use the device's default interface speed. + On output, the value actually set. + @param ReveiveFifoDepth The requested depth of the FIFO on the receive= side + of the serial interface. A ReceiveFifoDepth va= lue + of 0 will use the device's default FIFO depth. + On output, the value actually set. + @param Timeout The requested time out for a single character = in + microseconds. This timeout applies to both the + transmit and receive side of the interface. A + Timeout value of 0 will use the device's defau= lt + timeout value. + On output, the value actually set. + @param Parity The type of parity to use on this serial devic= e. A + Parity value of DefaultParity will use the dev= ice's + default parity value. + On output, the value actually set. + @param DataBits The number of data bits to use on the serial d= evice. + A DataBits value of 0 will use the device's de= fault + data bit setting. + On output, the value actually set. + @param StopBits The number of stop bits to use on this serial = device. + A StopBits value of DefaultStopBits will use t= he + device's default number of stop bits. + On output, the value actually set. + + @retval RETURN_UNSUPPORTED The serial device does not support thi= s operation. + +**/ +RETURN_STATUS +EFIAPI +SerialPortSetAttributes ( + IN OUT UINT64 *BaudRate, + IN OUT UINT32 *ReceiveFifoDepth, + IN OUT UINT32 *Timeout, + IN OUT EFI_PARITY_TYPE *Parity, + IN OUT UINT8 *DataBits, + IN OUT EFI_STOP_BITS_TYPE *StopBits + ) +{ + return RETURN_UNSUPPORTED; +} diff --git a/Silicon/NXP/iMXPlatformPkg/Library/UartSerialPortLib/UartSeria= lPortLib.inf b/Silicon/NXP/iMXPlatformPkg/Library/UartSerialPortLib/UartSer= ialPortLib.inf new file mode 100644 index 000000000000..9f381b199f38 --- /dev/null +++ b/Silicon/NXP/iMXPlatformPkg/Library/UartSerialPortLib/UartSerialPortLi= b.inf @@ -0,0 +1,41 @@ +## @file +# +# Copyright (c) 2018 Microsoft Corporation. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D SerialPortLib + FILE_GUID =3D C22D85E6-8B3E-4c05-AA5B-5732F3ACD055 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SerialPortLib + +[Sources.common] + UartSerialPortLib.c + +[LibraryClasses] + ArmLib + BaseMemoryLib + CacheMaintenanceLib + IoLib + PcdLib + TimerLib + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + MdePkg/MdePkg.dec + Silicon/NXP/iMXPlatformPkg/iMXPlatformPkg.dec + +[FixedPcd] + giMXPlatformTokenSpaceGuid.PcdSerialRegisterBase --=20 2.16.2.gvfs.1.33.gf5370f1