From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.20; helo=mga02.intel.com; envelope-from=eric.dong@intel.com; receiver=edk2-devel@lists.01.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 64A382194D3B9 for ; Mon, 24 Sep 2018 19:13:49 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Sep 2018 19:13:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,300,1534834800"; d="scan'208";a="93410469" Received: from ydong10-win10.ccr.corp.intel.com ([10.239.9.125]) by orsmga001.jf.intel.com with ESMTP; 24 Sep 2018 19:09:07 -0700 From: Eric Dong To: edk2-devel@lists.01.org Cc: Michael D Kinney , Ruiyu Ni , Laszlo Ersek Date: Tue, 25 Sep 2018 10:08:48 +0800 Message-Id: <20180925020853.25804-10-eric.dong@intel.com> X-Mailer: git-send-email 2.15.0.windows.1 In-Reply-To: <20180925020853.25804-1-eric.dong@intel.com> References: <20180925020853.25804-1-eric.dong@intel.com> Subject: [Patch v3 09/14] UefiCpuPkg/Include/Register/Msr/Core2Msr.h: Remove old MSR. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 25 Sep 2018 02:13:49 -0000 Changes includes: 1. Remove old MSR which not existed in 2018-05 version spec: 1. MSR_CORE2_BBL_CR_CTL3 Cc: Michael D Kinney Cc: Ruiyu Ni Cc: Laszlo Ersek Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong --- UefiCpuPkg/Include/Register/Msr/Core2Msr.h | 60 ------------------------------ 1 file changed, 60 deletions(-) diff --git a/UefiCpuPkg/Include/Register/Msr/Core2Msr.h b/UefiCpuPkg/Include/Register/Msr/Core2Msr.h index 22317fa1de..f01f7c5c97 100644 --- a/UefiCpuPkg/Include/Register/Msr/Core2Msr.h +++ b/UefiCpuPkg/Include/Register/Msr/Core2Msr.h @@ -471,66 +471,6 @@ typedef union { UINT64 Uint64; } MSR_CORE2_FSB_FREQ_REGISTER; - -/** - Shared. - - @param ECX MSR_CORE2_BBL_CR_CTL3 (0x0000011E) - @param EAX Lower 32-bits of MSR value. - Described by the type MSR_CORE2_BBL_CR_CTL3_REGISTER. - @param EDX Upper 32-bits of MSR value. - Described by the type MSR_CORE2_BBL_CR_CTL3_REGISTER. - - Example usage - @code - MSR_CORE2_BBL_CR_CTL3_REGISTER Msr; - - Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_BBL_CR_CTL3); - AsmWriteMsr64 (MSR_CORE2_BBL_CR_CTL3, Msr.Uint64); - @endcode - @note MSR_CORE2_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM. -**/ -#define MSR_CORE2_BBL_CR_CTL3 0x0000011E - -/** - MSR information returned for MSR index #MSR_CORE2_BBL_CR_CTL3 -**/ -typedef union { - /// - /// Individual bit fields - /// - struct { - /// - /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 = - /// Indicates if the L2 is hardware-disabled. - /// - UINT32 L2HardwareEnabled:1; - UINT32 Reserved1:7; - /// - /// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 = - /// Disabled (default) Until this bit is set the processor will not - /// respond to the WBINVD instruction or the assertion of the FLUSH# input. - /// - UINT32 L2Enabled:1; - UINT32 Reserved2:14; - /// - /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present. - /// - UINT32 L2NotPresent:1; - UINT32 Reserved3:8; - UINT32 Reserved4:32; - } Bits; - /// - /// All bit fields as a 32-bit value - /// - UINT32 Uint32; - /// - /// All bit fields as a 64-bit value - /// - UINT64 Uint64; -} MSR_CORE2_BBL_CR_CTL3_REGISTER; - - /** Shared. -- 2.15.0.windows.1