* [Patch v3 00/14] Update MSR definitions
@ 2018-09-25 2:08 Eric Dong
2018-09-25 2:08 ` [Patch v3 01/14] UefiCpuPkg/Include/Register/Msr: Update reference spec info Eric Dong
` (15 more replies)
0 siblings, 16 replies; 17+ messages in thread
From: Eric Dong @ 2018-09-25 2:08 UTC (permalink / raw)
To: edk2-devel; +Cc: Michael D Kinney, Ruiyu Ni, Laszlo Ersek
Current MSR definition are follow the SDM 2016-09 version. The latest SDM is 2018-05. This patch serial update the MSR related definition to follow the latest SDM 2018-05 version. MSR related defintion are saved at UefiCpuPkg\Include\Register\.
V3 changes includes:
1. Only change Patch 8 and 14 which changed MSR data structures.
2. Keep ReservedX not change if bit info not changed for this field.
V2 changes include:
1. Only change Patch 8 and 14 which changed MSR data structures.
2. Use X in ReservedX fields from totally new value if MSR structure definition changed.
For example, if in current structure, the max reserved variable is Reserved2, in new
definition, reserved variable is begin with Reserved3.
V1 Changes include:
The changes for this serial includes:
1. Add new MSR definition and file.
2. Remove old MSR definition which not defined in new SDM.
3. Change MSR name to follow new SDM, keep old one for compatibility.
4. Change MSR data structure definition to follow new SDM.
5. Update comments to follow the new SDM, mainly related to chapter info.
Below changes are incompatible changes:
2. Remove old MSR definition which not defined in new SDM.
For this one, i search edk2 codebase, not found any code uses it. so no impact for edk2 codebase. Detail changes see patch 9 ~ 11.
4. Change MSR data structure definition to follow new SDM.
For this one, new data structure just change the original reserved bits to valid bits, should have no impact for the current code. Detail see patch 8 and patch 14
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong <eric.dong@intel.com>
Eric Dong (14):
UefiCpuPkg/Include/Register/Msr: Update reference spec info.
UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h: Add new MSR file
for goldmont plus microarchitecture.
UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h: Add new MSR.
UefiCpuPkg/Include/Register/Msr/*.h: Add new MSR.
UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h: Add new MSR.
UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h: Add new MSRs.
UefiCpuPkg/Include/Register/ArchitecturalMsr.h: Add new MSR.
UefiCpuPkg/Include/Register/ArchitecturalMsr.h: Change structure
definition.
UefiCpuPkg/Include/Register/Msr/Core2Msr.h: Remove old MSR.
UefiCpuPkg/Include/Register/Msr/P6Msr.h: Remove old MSR.
UefiCpuPkg/Include/Register/Msr/CoreMsr.h: Remove old MSR.
UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h: Add new MSR name and
keep old one.
UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h: Add new MSR name and
keep old one.
UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h: Change structure
definition.
UefiCpuPkg/Include/Register/ArchitecturalMsr.h | 130 +-
UefiCpuPkg/Include/Register/Msr.h | 7 +-
UefiCpuPkg/Include/Register/Msr/AtomMsr.h | 28 +-
UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h | 62 +-
UefiCpuPkg/Include/Register/Msr/Core2Msr.h | 102 +-
UefiCpuPkg/Include/Register/Msr/CoreMsr.h | 74 +-
UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h | 88 +-
UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h | 272 ++++
UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h | 62 +-
UefiCpuPkg/Include/Register/Msr/HaswellMsr.h | 34 +-
UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h | 8 +-
UefiCpuPkg/Include/Register/Msr/NehalemMsr.h | 52 +-
UefiCpuPkg/Include/Register/Msr/P6Msr.h | 60 +-
UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h | 202 +--
UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h | 22 +-
UefiCpuPkg/Include/Register/Msr/PentiumMsr.h | 12 +-
UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h | 49 +-
UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h | 100 +-
UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h | 1602 ++++++++++++++++++++-
UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h | 8 +-
UefiCpuPkg/Include/Register/Msr/XeonDMsr.h | 84 +-
UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h | 6 +-
UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h | 332 ++++-
23 files changed, 2816 insertions(+), 580 deletions(-)
create mode 100644 UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h
--
2.15.0.windows.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Patch v3 01/14] UefiCpuPkg/Include/Register/Msr: Update reference spec info.
2018-09-25 2:08 [Patch v3 00/14] Update MSR definitions Eric Dong
@ 2018-09-25 2:08 ` Eric Dong
2018-09-25 2:08 ` [Patch v3 02/14] UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h: Add new MSR file for goldmont plus microarchitecture Eric Dong
` (14 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Eric Dong @ 2018-09-25 2:08 UTC (permalink / raw)
To: edk2-devel; +Cc: Michael D Kinney, Ruiyu Ni, Laszlo Ersek
Latest SDM has moved MSR related content from volume 3 chapter 35 to volume 4
chapter 2. Current MSR's comments need to be updated to reference the new
chapter info.
Changes includes:
1. Update referenced chapter info from some MSRs.
2. Update referenced SDM version info.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong <eric.dong@intel.com>
---
UefiCpuPkg/Include/Register/ArchitecturalMsr.h | 44 ++---
UefiCpuPkg/Include/Register/Msr/AtomMsr.h | 28 ++--
UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h | 8 +-
UefiCpuPkg/Include/Register/Msr/Core2Msr.h | 42 ++---
UefiCpuPkg/Include/Register/Msr/CoreMsr.h | 26 +--
UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h | 54 +++---
UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h | 6 +-
UefiCpuPkg/Include/Register/Msr/HaswellMsr.h | 34 ++--
UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h | 8 +-
UefiCpuPkg/Include/Register/Msr/NehalemMsr.h | 52 +++---
UefiCpuPkg/Include/Register/Msr/P6Msr.h | 12 +-
UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h | 202 +++++++++++------------
UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h | 22 +--
UefiCpuPkg/Include/Register/Msr/PentiumMsr.h | 12 +-
UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h | 49 +++---
UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h | 52 +++---
UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h | 14 +-
UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h | 8 +-
UefiCpuPkg/Include/Register/Msr/XeonDMsr.h | 28 ++--
UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h | 6 +-
UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h | 24 +--
21 files changed, 359 insertions(+), 372 deletions(-)
diff --git a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
index 34fdf5be3a..5d2242aa80 100644
--- a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
+++ b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
@@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
- Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -16,16 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.1.
-
- @par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- September 2016, Appendix A VMX Capability Reporting Facility, Section A.1.
-
- @par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- September 2016, Appendix A VMX Capability Reporting Facility, Section A.6.
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+ May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@@ -33,7 +25,7 @@
#define __ARCHITECTURAL_MSR_H__
/**
- See Section 35.22, "MSRs in Pentium Processors.". Pentium Processor (05_01H).
+ See Section 2.22, "MSRs in Pentium Processors.". Pentium Processor (05_01H).
@param ECX MSR_IA32_P5_MC_ADDR (0x00000000)
@param EAX Lower 32-bits of MSR value.
@@ -52,7 +44,7 @@
/**
- See Section 35.22, "MSRs in Pentium Processors.". DF_DM = 05_01H.
+ See Section 2.22, "MSRs in Pentium Processors.". DF_DM = 05_01H.
@param ECX MSR_IA32_P5_MC_TYPE (0x00000001)
@param EAX Lower 32-bits of MSR value.
@@ -91,7 +83,7 @@
/**
- See Section 17.15, "Time-Stamp Counter.". Introduced at Display Family /
+ See Section 17.17, "Time-Stamp Counter.". Introduced at Display Family /
Display Model 05_01H.
@param ECX MSR_IA32_TIME_STAMP_COUNTER (0x00000010)
@@ -493,9 +485,8 @@ typedef union {
UINT32 Valid:1;
UINT32 Reserved1:1;
///
- /// [Bit 2] Determines whether executions of VMXOFF unblock SMIs under the
- /// default treatment of SMIs and SMM. Executions of VMXOFF unblock SMIs
- /// unless bit 2 is 1 (the value of bit 0 is irrelevant).
+ /// [Bit 2] Controls SMI unblocking by VMXOFF (see Section 34.14.4). If
+ /// IA32_VMX_MISC[28].
///
UINT32 BlockSmi:1;
UINT32 Reserved2:9;
@@ -1953,7 +1944,7 @@ typedef union {
/**
- SMRR Range Mask. (Writeable only in SMM) Range Mask of SMM memory range. If
+ SMRR Range Mask (Writeable only in SMM) Range Mask of SMM memory range. If
IA32_MTRRCAP[SMRR] = 1.
@param ECX MSR_IA32_SMRR_PHYSMASK (0x000001F3)
@@ -4417,13 +4408,13 @@ typedef union {
///
struct {
///
- /// [Bit 0] Lock. See Section 42.11.3, "Interactions with Authenticated
+ /// [Bit 0] Lock. See Section 41.11.3, "Interactions with Authenticated
/// Code Modules (ACMs)".
///
UINT32 Lock:1;
UINT32 Reserved1:15;
///
- /// [Bits 23:16] SGX_SVN_SINIT. See Section 42.11.3, "Interactions with
+ /// [Bits 23:16] SGX_SVN_SINIT. See Section 41.11.3, "Interactions with
/// Authenticated Code Modules (ACMs)".
///
UINT32 SGX_SVN_SINIT:8;
@@ -4925,16 +4916,11 @@ typedef union {
/**
- DS Save Area (R/W) Points to the linear address of the first byte of the DS
+ DS Save Area (R/W) Points to the linear address of the first byte of the DS
buffer management area, which is used to manage the BTS and PEBS buffers.
- See Section 18.15.4, "Debug Store (DS) Mechanism.". If( CPUID.01H:EDX.DS[21]
- = 1.
-
- [Bits 31..0] The linear address of the first byte of the DS buffer
- management area, if not in IA-32e mode.
-
- [Bits 63..0] The linear address of the first byte of the DS buffer
- management area, if IA-32e mode is active.
+ See Section 18.6.3.4, "Debug Store (DS) Mechanism.". If(
+ CPUID.01H:EDX.DS[21] = 1. The linear address of the first byte of the DS
+ buffer management area, if IA-32e mode is active.
@param ECX MSR_IA32_DS_AREA (0x00000600)
@param EAX Lower 32-bits of MSR value.
diff --git a/UefiCpuPkg/Include/Register/Msr/AtomMsr.h b/UefiCpuPkg/Include/Register/Msr/AtomMsr.h
index b2764690f5..2025b65293 100644
--- a/UefiCpuPkg/Include/Register/Msr/AtomMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/AtomMsr.h
@@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
- Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.3.
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+ May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@@ -518,18 +518,18 @@ typedef union {
///
struct {
///
- /// [Bit 0] Fast-Strings Enable See Table 35-2.
+ /// [Bit 0] Fast-Strings Enable See Table 2-2.
///
UINT32 FastStrings:1;
UINT32 Reserved1:2;
///
/// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See
- /// Table 35-2. Default value is 0.
+ /// Table 2-2. Default value is 0.
///
UINT32 AutomaticThermalControlCircuit:1;
UINT32 Reserved2:3;
///
- /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 35-2.
+ /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.
///
UINT32 PerformanceMonitoring:1;
UINT32 Reserved3:1;
@@ -542,12 +542,12 @@ typedef union {
///
UINT32 FERR:1;
///
- /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 35-2.
+ /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.
///
UINT32 BTS:1;
///
/// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See
- /// Table 35-2.
+ /// Table 2-2.
///
UINT32 PEBS:1;
///
@@ -568,12 +568,12 @@ typedef union {
UINT32 Reserved5:2;
///
/// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See
- /// Table 35-2.
+ /// Table 2-2.
///
UINT32 EIST:1;
UINT32 Reserved6:1;
///
- /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 35-2.
+ /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.
///
UINT32 MONITOR:1;
UINT32 Reserved7:1;
@@ -588,17 +588,17 @@ typedef union {
UINT32 EISTLock:1;
UINT32 Reserved8:1;
///
- /// [Bit 22] Unique. Limit CPUID Maxval (R/W) See Table 35-2.
+ /// [Bit 22] Unique. Limit CPUID Maxval (R/W) See Table 2-2.
///
UINT32 LimitCpuidMaxval:1;
///
- /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 35-2.
+ /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.
///
UINT32 xTPR_Message_Disable:1;
UINT32 Reserved9:8;
UINT32 Reserved10:2;
///
- /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 35-2.
+ /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.
///
UINT32 XD:1;
UINT32 Reserved11:29;
@@ -673,7 +673,7 @@ typedef union {
/**
- Unique. See Table 35-2. See Section 18.4.4, "Processor Event Based Sampling
+ Unique. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling
(PEBS).".
@param ECX MSR_ATOM_PEBS_ENABLE (0x000003F1)
diff --git a/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h b/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
index 90bd523c99..4e50f72008 100644
--- a/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
@@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
- Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.13.
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+ May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@@ -46,7 +46,7 @@
)
/**
- Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control
+ Thread. See Table 2-2. See Section 18.6.2.2, "Global Counter Control
Facilities.".
@param ECX MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS (0x0000038E)
diff --git a/UefiCpuPkg/Include/Register/Msr/Core2Msr.h b/UefiCpuPkg/Include/Register/Msr/Core2Msr.h
index 9ebca5e9b5..22317fa1de 100644
--- a/UefiCpuPkg/Include/Register/Msr/Core2Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/Core2Msr.h
@@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
- Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.2.
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+ May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@@ -78,7 +78,7 @@ typedef union {
UINT32 Reserved2:19;
UINT32 Reserved3:18;
///
- /// [Bits 52:50] See Table 35-2.
+ /// [Bits 52:50] See Table 2-2.
///
UINT32 PlatformId:3;
UINT32 Reserved4:11;
@@ -206,7 +206,7 @@ typedef union {
/**
- Unique. Control Features in Intel 64Processor (R/W) See Table 35-2.
+ Unique. Control Features in Intel 64 Processor (R/W) See Table 2-2.
@param ECX MSR_CORE2_FEATURE_CONTROL (0x0000003A)
@param EAX Lower 32-bits of MSR value.
@@ -672,18 +672,18 @@ typedef union {
///
struct {
///
- /// [Bit 0] Fast-Strings Enable See Table 35-2.
+ /// [Bit 0] Fast-Strings Enable See Table 2-2.
///
UINT32 FastStrings:1;
UINT32 Reserved1:2;
///
/// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See
- /// Table 35-2.
+ /// Table 2-2.
///
UINT32 AutomaticThermalControlCircuit:1;
UINT32 Reserved2:3;
///
- /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 35-2.
+ /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.
///
UINT32 PerformanceMonitoring:1;
UINT32 Reserved3:1;
@@ -702,12 +702,12 @@ typedef union {
///
UINT32 FERR:1;
///
- /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 35-2.
+ /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.
///
UINT32 BTS:1;
///
/// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See
- /// Table 35-2.
+ /// Table 2-2.
///
UINT32 PEBS:1;
///
@@ -728,12 +728,12 @@ typedef union {
UINT32 Reserved4:2;
///
/// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See
- /// Table 35-2.
+ /// Table 2-2.
///
UINT32 EIST:1;
UINT32 Reserved5:1;
///
- /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 35-2.
+ /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.
///
UINT32 MONITOR:1;
///
@@ -758,17 +758,17 @@ typedef union {
UINT32 EISTLock:1;
UINT32 Reserved6:1;
///
- /// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 35-2.
+ /// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 2-2.
///
UINT32 LimitCpuidMaxval:1;
///
- /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 35-2.
+ /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.
///
UINT32 xTPR_Message_Disable:1;
UINT32 Reserved7:8;
UINT32 Reserved8:2;
///
- /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 35-2.
+ /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.
///
UINT32 XD:1;
UINT32 Reserved9:2;
@@ -928,7 +928,7 @@ typedef union {
///
struct {
///
- /// [Bits 5:0] LBR Format. See Table 35-2.
+ /// [Bits 5:0] LBR Format. See Table 2-2.
///
UINT32 LBR_FMT:6;
///
@@ -936,7 +936,7 @@ typedef union {
///
UINT32 PEBS_FMT:1;
///
- /// [Bit 7] PEBSSaveArchRegs. See Table 35-2.
+ /// [Bit 7] PEBSSaveArchRegs. See Table 2-2.
///
UINT32 PEBS_ARCH_REG:1;
UINT32 Reserved1:24;
@@ -973,7 +973,7 @@ typedef union {
/**
- Unique. See Section 18.4.2, "Global Counter Control Facilities.".
+ Unique. See Section 18.6.2.2, "Global Counter Control Facilities.".
@param ECX MSR_CORE2_PERF_GLOBAL_STATUS (0x0000038E)
@param EAX Lower 32-bits of MSR value.
@@ -992,7 +992,7 @@ typedef union {
/**
- Unique. See Section 18.4.2, "Global Counter Control Facilities.".
+ Unique. See Section 18.6.2.2, "Global Counter Control Facilities.".
@param ECX MSR_CORE2_PERF_GLOBAL_CTRL (0x0000038F)
@param EAX Lower 32-bits of MSR value.
@@ -1011,7 +1011,7 @@ typedef union {
/**
- Unique. See Section 18.4.2, "Global Counter Control Facilities.".
+ Unique. See Section 18.6.2.2, "Global Counter Control Facilities.".
@param ECX MSR_CORE2_PERF_GLOBAL_OVF_CTRL (0x00000390)
@param EAX Lower 32-bits of MSR value.
@@ -1030,7 +1030,7 @@ typedef union {
/**
- Unique. See Table 35-2. See Section 18.4.4, "Processor Event Based Sampling
+ Unique. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling
(PEBS).".
@param ECX MSR_CORE2_PEBS_ENABLE (0x000003F1)
diff --git a/UefiCpuPkg/Include/Register/Msr/CoreMsr.h b/UefiCpuPkg/Include/Register/Msr/CoreMsr.h
index 4897c74d5a..bb2bdd2ca1 100644
--- a/UefiCpuPkg/Include/Register/Msr/CoreMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/CoreMsr.h
@@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
- Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.19.
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+ May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@@ -43,7 +43,7 @@
)
/**
- Unique. See Section 35.22, "MSRs in Pentium Processors," and see Table 35-2.
+ Unique. See Section 2.22, "MSRs in Pentium Processors," and see Table 2-2.
@param ECX MSR_CORE_P5_MC_ADDR (0x00000000)
@param EAX Lower 32-bits of MSR value.
@@ -62,7 +62,7 @@
/**
- Unique. See Section 35.22, "MSRs in Pentium Processors," and see Table 35-2.
+ Unique. See Section 2.22, "MSRs in Pentium Processors," and see Table 2-2.
@param ECX MSR_CORE_P5_MC_TYPE (0x00000001)
@param EAX Lower 32-bits of MSR value.
@@ -194,7 +194,7 @@ typedef union {
Unique. Last Branch Record n (R/W) One of 8 last branch record registers on
the last branch record stack: bits 31-0 hold the 'from' address and bits
63-32 hold the 'to' address. See also: - Last Branch Record Stack TOS at
- 1C9H - Section 17.13, "Last Branch, Interrupt, and Exception Recording
+ 1C9H - Section 17.15, "Last Branch, Interrupt, and Exception Recording
(Pentium M Processors).".
@param ECX MSR_CORE_LASTBRANCH_n
@@ -424,12 +424,12 @@ typedef union {
UINT32 Reserved1:3;
///
/// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See
- /// Table 35-2.
+ /// Table 2-2.
///
UINT32 AutomaticThermalControlCircuit:1;
UINT32 Reserved2:3;
///
- /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 35-2.
+ /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.
///
UINT32 PerformanceMonitoring:1;
UINT32 Reserved3:2;
@@ -441,7 +441,7 @@ typedef union {
///
UINT32 FERR:1;
///
- /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 35-2.
+ /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.
///
UINT32 BTS:1;
UINT32 Reserved4:1;
@@ -468,13 +468,13 @@ typedef union {
UINT32 EIST:1;
UINT32 Reserved6:1;
///
- /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 35-2.
+ /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.
///
UINT32 MONITOR:1;
UINT32 Reserved7:1;
UINT32 Reserved8:2;
///
- /// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 35-2. Setting this
+ /// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 2-2. Setting this
/// bit may cause behavior in software that depends on the availability of
/// CPUID leaves greater than 2.
///
@@ -482,7 +482,7 @@ typedef union {
UINT32 Reserved9:9;
UINT32 Reserved10:2;
///
- /// [Bit 34] Shared. XD Bit Disable (R/W) See Table 35-2.
+ /// [Bit 34] Shared. XD Bit Disable (R/W) See Table 2-2.
///
UINT32 XD:1;
UINT32 Reserved11:29;
@@ -1062,7 +1062,7 @@ typedef union {
/**
- Unique. See Table 35-2.
+ Unique. See Table 2-2.
@param ECX MSR_CORE_IA32_EFER (0xC0000080)
@param EAX Lower 32-bits of MSR value.
diff --git a/UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h b/UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
index 5730918ec6..a9061133c9 100644
--- a/UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
@@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
- Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.5.
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+ May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@@ -333,54 +333,54 @@ typedef union {
///
struct {
///
- /// [Bit 0] Core. Fast-Strings Enable See Table 35-2.
+ /// [Bit 0] Core. Fast-Strings Enable See Table 2-2.
///
UINT32 FastStrings:1;
UINT32 Reserved1:2;
///
/// [Bit 3] Package. Automatic Thermal Control Circuit Enable (R/W) See
- /// Table 35-2. Default value is 1.
+ /// Table 2-2. Default value is 1.
///
UINT32 AutomaticThermalControlCircuit:1;
UINT32 Reserved2:3;
///
- /// [Bit 7] Core. Performance Monitoring Available (R) See Table 35-2.
+ /// [Bit 7] Core. Performance Monitoring Available (R) See Table 2-2.
///
UINT32 PerformanceMonitoring:1;
UINT32 Reserved3:3;
///
- /// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 35-2.
+ /// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 2-2.
///
UINT32 BTS:1;
///
/// [Bit 12] Core. Processor Event Based Sampling Unavailable (RO) See
- /// Table 35-2.
+ /// Table 2-2.
///
UINT32 PEBS:1;
UINT32 Reserved4:3;
///
/// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See
- /// Table 35-2.
+ /// Table 2-2.
///
UINT32 EIST:1;
UINT32 Reserved5:1;
///
- /// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 35-2.
+ /// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 2-2.
///
UINT32 MONITOR:1;
UINT32 Reserved6:3;
///
- /// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 35-2.
+ /// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 2-2.
///
UINT32 LimitCpuidMaxval:1;
///
- /// [Bit 23] Package. xTPR Message Disable (R/W) See Table 35-2.
+ /// [Bit 23] Package. xTPR Message Disable (R/W) See Table 2-2.
///
UINT32 xTPR_Message_Disable:1;
UINT32 Reserved7:8;
UINT32 Reserved8:2;
///
- /// [Bit 34] Core. XD Bit Disable (R/W) See Table 35-2.
+ /// [Bit 34] Core. XD Bit Disable (R/W) See Table 2-2.
///
UINT32 XD:1;
UINT32 Reserved9:3;
@@ -690,8 +690,8 @@ typedef union {
/**
- Core. Last Branch Record Filtering Select Register (R/W) See Section
- 17.7.2, "Filtering of Last Branch Records.".
+ Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2,
+ "Filtering of Last Branch Records.".
@param ECX MSR_GOLDMONT_LBR_SELECT (0x000001C8)
@param EAX Lower 32-bits of MSR value.
@@ -881,7 +881,7 @@ typedef union {
/**
- Core. See Table 35-2. See Section 18.2.4, "Architectural Performance
+ Core. See Table 2-2. See Section 18.2.4, "Architectural Performance
Monitoring Version 4.".
@param ECX MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)
@@ -978,7 +978,7 @@ typedef union {
/**
- Core. See Table 35-2. See Section 18.2.4, "Architectural Performance
+ Core. See Table 2-2. See Section 18.2.4, "Architectural Performance
Monitoring Version 4.".
@param ECX MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)
@@ -1072,7 +1072,7 @@ typedef union {
/**
- Core. See Table 35-2. See Section 18.4.4, "Processor Event Based Sampling
+ Core. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling
(PEBS).".
@param ECX MSR_GOLDMONT_PEBS_ENABLE (0x000003F1)
@@ -1492,9 +1492,9 @@ typedef union {
///
UINT32 InterruptResponseTimeLimit:10;
///
- /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time
- /// unit of the interrupt response time limit. See Table 35-18 for
- /// supported time unit encodings.
+ /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit
+ /// of the interrupt response time limit. See Table 2-19 for supported
+ /// time unit encodings.
///
UINT32 TimeUnit:3;
UINT32 Reserved1:2;
@@ -1556,9 +1556,9 @@ typedef union {
///
UINT32 InterruptResponseTimeLimit:10;
///
- /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time
- /// unit of the interrupt response time limit. See Table 35-18 for
- /// supported time unit encodings.
+ /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit
+ /// of the interrupt response time limit. See Table 2-19 for supported
+ /// time unit encodings.
///
UINT32 TimeUnit:3;
UINT32 Reserved1:2;
@@ -1619,9 +1619,9 @@ typedef union {
///
UINT32 InterruptResponseTimeLimit:10;
///
- /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time
- /// unit of the interrupt response time limit. See Table 35-18 for
- /// supported time unit encodings.
+ /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit
+ /// of the interrupt response time limit. See Table 2-19 for supported
+ /// time unit encodings.
///
UINT32 TimeUnit:3;
UINT32 Reserved1:2;
diff --git a/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h b/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
index b737a9e4b8..a75bdb2e13 100644
--- a/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
@@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
- Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.12.
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+ May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
diff --git a/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h b/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
index 3cd15846b4..3e748a1669 100644
--- a/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
@@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
- Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.11.
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+ May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@@ -129,8 +129,8 @@ typedef union {
/**
- THREAD. Performance Event Select for Counter n (R/W) Supports all fields
- described inTable 35-2 and the fields below.
+ Thread. Performance Event Select for Counter n (R/W) Supports all fields
+ described inTable 2-2 and the fields below.
@param ECX MSR_HASWELL_IA32_PERFEVTSELn
@param EAX Lower 32-bits of MSR value.
@@ -218,7 +218,7 @@ typedef union {
UINT32 CMASK:8;
UINT32 Reserved:32;
///
- /// [Bit 32] IN_TX: see Section 18.11.5.1 When IN_TX (bit 32) is set,
+ /// [Bit 32] IN_TX: see Section 18.3.6.5.1 When IN_TX (bit 32) is set,
/// AnyThread (bit 21) should be cleared to prevent incorrect results.
///
UINT32 IN_TX:1;
@@ -232,8 +232,8 @@ typedef union {
/**
- THREAD. Performance Event Select for Counter 2 (R/W) Supports all fields
- described inTable 35-2 and the fields below.
+ Thread. Performance Event Select for Counter 2 (R/W) Supports all fields
+ described inTable 2-2 and the fields below.
@param ECX MSR_HASWELL_IA32_PERFEVTSEL2 (0x00000188)
@param EAX Lower 32-bits of MSR value.
@@ -314,12 +314,12 @@ typedef union {
UINT32 CMASK:8;
UINT32 Reserved:32;
///
- /// [Bit 32] IN_TX: see Section 18.11.5.1 When IN_TX (bit 32) is set,
+ /// [Bit 32] IN_TX: see Section 18.3.6.5.1 When IN_TX (bit 32) is set,
/// AnyThread (bit 21) should be cleared to prevent incorrect results.
///
UINT32 IN_TX:1;
///
- /// [Bit 33] IN_TXCP: see Section 18.11.5.1 When IN_TXCP=1 & IN_TX=1 and
+ /// [Bit 33] IN_TXCP: see Section 18.3.6.5.1 When IN_TXCP=1 & IN_TX=1 and
/// in sampling, spurious PMI may occur and transactions may continuously
/// abort near overflow conditions. Software should favor using IN_TXCP
/// for counting over sampling. If sampling, software should use large
@@ -459,9 +459,9 @@ typedef union {
///
UINT32 InterruptResponseTimeLimit:10;
///
- /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time
- /// unit of the interrupt response time limit. See Table 35-18 for
- /// supported time unit encodings.
+ /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit
+ /// of the interrupt response time limit. See Table 2-19 for supported
+ /// time unit encodings.
///
UINT32 TimeUnit:3;
UINT32 Reserved1:2;
@@ -518,15 +518,15 @@ typedef union {
///
struct {
///
- /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
+ /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
/// that should be used to decide if the package should be put into a
/// package C6 or C7 state.
///
UINT32 InterruptResponseTimeLimit:10;
///
- /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time
- /// unit of the interrupt response time limit. See Table 35-18 for
- /// supported time unit encodings.
+ /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit
+ /// of the interrupt response time limit. See Table 2-19 for supported
+ /// time unit encodings.
///
UINT32 TimeUnit:3;
UINT32 Reserved1:2;
diff --git a/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h b/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
index 39b0d1af12..f45b538ea7 100644
--- a/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
@@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
- Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.10.
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+ May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@@ -1112,7 +1112,7 @@ typedef union {
/**
- Thread. See Section 18.8.1.1, "Precise Event Based Sampling (PEBS).".
+ Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).".
@param ECX MSR_IVY_BRIDGE_PEBS_ENABLE (0x000003F1)
@param EAX Lower 32-bits of MSR value.
diff --git a/UefiCpuPkg/Include/Register/Msr/NehalemMsr.h b/UefiCpuPkg/Include/Register/Msr/NehalemMsr.h
index 94aebba4d1..c6c3d3db22 100644
--- a/UefiCpuPkg/Include/Register/Msr/NehalemMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/NehalemMsr.h
@@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
- Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.6.
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+ May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@@ -75,7 +75,7 @@ typedef union {
UINT32 Reserved1:32;
UINT32 Reserved2:18;
///
- /// [Bits 52:50] See Table 35-2.
+ /// [Bits 52:50] See Table 2-2.
///
UINT32 PlatformId:3;
UINT32 Reserved3:11;
@@ -393,54 +393,54 @@ typedef union {
///
struct {
///
- /// [Bit 0] Thread. Fast-Strings Enable See Table 35-2.
+ /// [Bit 0] Thread. Fast-Strings Enable See Table 2-2.
///
UINT32 FastStrings:1;
UINT32 Reserved1:2;
///
/// [Bit 3] Thread. Automatic Thermal Control Circuit Enable (R/W) See
- /// Table 35-2. Default value is 1.
+ /// Table 2-2. Default value is 1.
///
UINT32 AutomaticThermalControlCircuit:1;
UINT32 Reserved2:3;
///
- /// [Bit 7] Thread. Performance Monitoring Available (R) See Table 35-2.
+ /// [Bit 7] Thread. Performance Monitoring Available (R) See Table 2-2.
///
UINT32 PerformanceMonitoring:1;
UINT32 Reserved3:3;
///
- /// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 35-2.
+ /// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 2-2.
///
UINT32 BTS:1;
///
/// [Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See
- /// Table 35-2.
+ /// Table 2-2.
///
UINT32 PEBS:1;
UINT32 Reserved4:3;
///
/// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See
- /// Table 35-2.
+ /// Table 2-2.
///
UINT32 EIST:1;
UINT32 Reserved5:1;
///
- /// [Bit 18] Thread. ENABLE MONITOR FSM. (R/W) See Table 35-2.
+ /// [Bit 18] Thread. ENABLE MONITOR FSM. (R/W) See Table 2-2.
///
UINT32 MONITOR:1;
UINT32 Reserved6:3;
///
- /// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 35-2.
+ /// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 2-2.
///
UINT32 LimitCpuidMaxval:1;
///
- /// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 35-2.
+ /// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 2-2.
///
UINT32 xTPR_Message_Disable:1;
UINT32 Reserved7:8;
UINT32 Reserved8:2;
///
- /// [Bit 34] Thread. XD Bit Disable (R/W) See Table 35-2.
+ /// [Bit 34] Thread. XD Bit Disable (R/W) See Table 2-2.
///
UINT32 XD:1;
UINT32 Reserved9:3;
@@ -778,8 +778,8 @@ typedef union {
/**
- Core. Last Branch Record Filtering Select Register (R/W) See Section
- 17.7.2, "Filtering of Last Branch Records.".
+ Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2,
+ "Filtering of Last Branch Records.".
@param ECX MSR_NEHALEM_LBR_SELECT (0x000001C8)
@param EAX Lower 32-bits of MSR value.
@@ -1053,7 +1053,7 @@ typedef union {
/**
- Thread. See Section 18.8.1.1, "Processor Event Based Sampling (PEBS).".
+ Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).".
@param ECX MSR_NEHALEM_PEBS_ENABLE (0x000003F1)
@param EAX Lower 32-bits of MSR value.
@@ -1123,7 +1123,7 @@ typedef union {
/**
- Thread. See Section 18.8.1.2, "Load Latency Performance Monitoring
+ Thread. See Section 18.3.1.1.2, "Load Latency Performance Monitoring
Facility.".
@param ECX MSR_NEHALEM_PEBS_LD_LAT (0x000003F6)
@@ -1463,7 +1463,7 @@ typedef union {
/**
- Package. See Section 18.8.2.1, "Uncore Performance Monitoring Management
+ Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management
Facility.".
@param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL (0x00000391)
@@ -1483,7 +1483,7 @@ typedef union {
/**
- Package. See Section 18.8.2.1, "Uncore Performance Monitoring Management
+ Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management
Facility.".
@param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS (0x00000392)
@@ -1503,7 +1503,7 @@ typedef union {
/**
- Package. See Section 18.8.2.1, "Uncore Performance Monitoring Management
+ Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management
Facility.".
@param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL (0x00000393)
@@ -1523,7 +1523,7 @@ typedef union {
/**
- Package. See Section 18.8.2.1, "Uncore Performance Monitoring Management
+ Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management
Facility.".
@param ECX MSR_NEHALEM_UNCORE_FIXED_CTR0 (0x00000394)
@@ -1543,7 +1543,7 @@ typedef union {
/**
- Package. See Section 18.8.2.1, "Uncore Performance Monitoring Management
+ Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management
Facility.".
@param ECX MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL (0x00000395)
@@ -1563,7 +1563,7 @@ typedef union {
/**
- Package. See Section 18.8.2.3, "Uncore Address/Opcode Match MSR.".
+ Package. See Section 18.3.1.2.3, "Uncore Address/Opcode Match MSR.".
@param ECX MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH (0x00000396)
@param EAX Lower 32-bits of MSR value.
@@ -1582,7 +1582,7 @@ typedef union {
/**
- Package. See Section 18.8.2.2, "Uncore Performance Event Configuration
+ Package. See Section 18.3.1.2.2, "Uncore Performance Event Configuration
Facility.".
@param ECX MSR_NEHALEM_UNCORE_PMCi
@@ -1617,7 +1617,7 @@ typedef union {
/// @}
/**
- Package. See Section 18.8.2.2, "Uncore Performance Event Configuration
+ Package. See Section 18.3.1.2.2, "Uncore Performance Event Configuration
Facility.".
@param ECX MSR_NEHALEM_UNCORE_PERFEVTSELi
diff --git a/UefiCpuPkg/Include/Register/Msr/P6Msr.h b/UefiCpuPkg/Include/Register/Msr/P6Msr.h
index aec2e2c868..d8af2db3da 100644
--- a/UefiCpuPkg/Include/Register/Msr/P6Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/P6Msr.h
@@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
- Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.21.
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+ May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@@ -48,7 +48,7 @@
)
/**
- See Section 35.22, "MSRs in Pentium Processors.".
+ See Section 2.22, "MSRs in Pentium Processors.".
@param ECX MSR_P6_P5_MC_ADDR (0x00000000)
@param EAX Lower 32-bits of MSR value.
@@ -67,7 +67,7 @@
/**
- See Section 35.22, "MSRs in Pentium Processors.".
+ See Section 2.22, "MSRs in Pentium Processors.".
@param ECX MSR_P6_P5_MC_TYPE (0x00000001)
@param EAX Lower 32-bits of MSR value.
@@ -86,7 +86,7 @@
/**
- See Section 17.14, "Time-Stamp Counter.".
+ See Section 17.17, "Time-Stamp Counter.".
@param ECX MSR_P6_TSC (0x00000010)
@param EAX Lower 32-bits of MSR value.
diff --git a/UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h b/UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h
index 8922d56e2f..ed828af33b 100644
--- a/UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h
@@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
- Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.18.
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+ May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@@ -872,7 +872,7 @@ typedef union {
///
struct {
///
- /// [Bit 0] Fast-Strings Enable. See Table 35-2.
+ /// [Bit 0] Fast-Strings Enable. See Table 2-2.
///
UINT32 FastStrings:1;
UINT32 Reserved1:1;
@@ -882,7 +882,7 @@ typedef union {
UINT32 FPU:1;
///
/// [Bit 3] Thermal Monitor 1 Enable See Section 14.7.2, "Thermal
- /// Monitor," and see Table 35-2.
+ /// Monitor," and see Table 2-2.
///
UINT32 TM1:1;
///
@@ -906,7 +906,7 @@ typedef union {
///
UINT32 ThirdLevelCacheDisable:1;
///
- /// [Bit 7] Performance Monitoring Available (R) See Table 35-2.
+ /// [Bit 7] Performance Monitoring Available (R) See Table 2-2.
///
UINT32 PerformanceMonitoring:1;
///
@@ -935,13 +935,13 @@ typedef union {
UINT32 FERR:1;
///
/// [Bit 11] Branch Trace Storage Unavailable (BTS_UNAVILABLE) (R) See
- /// Table 35-2. When set, the processor does not support branch trace
+ /// Table 2-2. When set, the processor does not support branch trace
/// storage (BTS); when clear, BTS is supported.
///
UINT32 BTS:1;
///
/// [Bit 12] PEBS_UNAVILABLE: Processor Event Based Sampling Unavailable
- /// (R) See Table 35-2. When set, the processor does not support processor
+ /// (R) See Table 2-2. When set, the processor does not support processor
/// event-based sampling (PEBS); when clear, PEBS is supported.
///
UINT32 PEBS:1;
@@ -961,7 +961,7 @@ typedef union {
UINT32 TM2:1;
UINT32 Reserved3:4;
///
- /// [Bit 18] 3, 4, 6. ENABLE MONITOR FSM (R/W) See Table 35-2.
+ /// [Bit 18] 3, 4, 6. ENABLE MONITOR FSM (R/W) See Table 2-2.
///
UINT32 MONITOR:1;
///
@@ -977,13 +977,13 @@ typedef union {
UINT32 AdjacentCacheLinePrefetchDisable:1;
UINT32 Reserved4:2;
///
- /// [Bit 22] 3, 4, 6. Limit CPUID MAXVAL (R/W) See Table 35-2. Setting
- /// this can cause unexpected behavior to software that depends on the
+ /// [Bit 22] 3, 4, 6. Limit CPUID MAXVAL (R/W) See Table 2-2. Setting this
+ /// can cause unexpected behavior to software that depends on the
/// availability of CPUID leaves greater than 3.
///
UINT32 LimitCpuidMaxval:1;
///
- /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 35-2.
+ /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.
///
UINT32 xTPR_Message_Disable:1;
///
@@ -1002,7 +1002,7 @@ typedef union {
UINT32 Reserved5:7;
UINT32 Reserved6:2;
///
- /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 35-2.
+ /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.
///
UINT32 XD:1;
UINT32 Reserved7:29;
@@ -1066,8 +1066,8 @@ typedef union {
0, 1, 2, 3, 4, 6. Unique. Last Exception Record From Linear IP (R) Contains
a pointer to the last branch instruction that the processor executed prior
to the last exception that was generated or the last interrupt that was
- handled. See Section 17.11.3, "Last Exception Records.". Unique. From Linear
- IP Linear address of the last branch instruction (If IA32e mode is active).
+ handled. See Section 17.13.3, "Last Exception Records.". Unique. From Linear
+ IP Linear address of the last branch instruction (If IA-32e mode is active).
From Linear IP Linear address of the last branch instruction. Reserved.
@param ECX MSR_PENTIUM_4_LER_FROM_LIP (0x000001D7)
@@ -1089,7 +1089,7 @@ typedef union {
0, 1, 2, 3, 4, 6. Unique. Last Exception Record To Linear IP (R) This area
contains a pointer to the target of the last branch instruction that the
processor executed prior to the last exception that was generated or the
- last interrupt that was handled. See Section 17.11.3, "Last Exception
+ last interrupt that was handled. See Section 17.13.3, "Last Exception
Records.". Unique. From Linear IP Linear address of the target of the last
branch instruction (If IA-32e mode is active). From Linear IP Linear address
of the target of the last branch instruction. Reserved.
@@ -1112,7 +1112,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Unique. Debug Control (R/W) Controls how several debug
features are used. Bit definitions are discussed in the referenced section.
- See Section 17.11.1, "MSR_DEBUGCTLA MSR.".
+ See Section 17.13.1, "MSR_DEBUGCTLA MSR.".
@param ECX MSR_PENTIUM_4_DEBUGCTLA (0x000001D9)
@param EAX Lower 32-bits of MSR value.
@@ -1134,7 +1134,7 @@ typedef union {
0, 1, 2, 3, 4, 6. Unique. Last Branch Record Stack TOS (R/W) Contains an
index (0-3 or 0-15) that points to the top of the last branch record stack
(that is, that points the index of the MSR containing the most recent branch
- record). See Section 17.11.2, "LBR Stack for Processors Based on Intel
+ record). See Section 17.13.2, "LBR Stack for Processors Based on Intel
NetBurst(R) Microarchitecture"; and addresses 1DBH-1DEH and 680H-68FH.
@param ECX MSR_PENTIUM_4_LASTBRANCH_TOS (0x000001DA)
@@ -1160,7 +1160,7 @@ typedef union {
exceptions, or interrupts that the processor took. MSR_LASTBRANCH_0 through
MSR_LASTBRANCH_3 at 1DBH-1DEH are available only on family 0FH, models
0H-02H. They have been replaced by the MSRs at 680H68FH and 6C0H-6CFH. See
- Section 17.10, "Last Branch, Call Stack, Interrupt, and Exception Recording
+ Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording
for Processors based on Skylake Microarchitecture.".
@param ECX MSR_PENTIUM_4_LASTBRANCH_n
@@ -1188,7 +1188,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.2, "Performance Counters.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".
@param ECX MSR_PENTIUM_4_BPU_COUNTERn
@param EAX Lower 32-bits of MSR value.
@@ -1215,7 +1215,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.2, "Performance Counters.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".
@param ECX MSR_PENTIUM_4_MS_COUNTERn
@param EAX Lower 32-bits of MSR value.
@@ -1242,7 +1242,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.2, "Performance Counters.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".
@param ECX MSR_PENTIUM_4_FLAME_COUNTERn (0x00000308)
@param EAX Lower 32-bits of MSR value.
@@ -1269,7 +1269,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.2, "Performance Counters.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".
@param ECX MSR_PENTIUM_4_IQ_COUNTERn
@param EAX Lower 32-bits of MSR value.
@@ -1300,7 +1300,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.3, "CCCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".
@param ECX MSR_PENTIUM_4_BPU_CCCRn
@param EAX Lower 32-bits of MSR value.
@@ -1327,7 +1327,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.3, "CCCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".
@param ECX MSR_PENTIUM_4_MS_CCCRn
@param EAX Lower 32-bits of MSR value.
@@ -1354,7 +1354,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.3, "CCCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".
@param ECX MSR_PENTIUM_4_FLAME_CCCRn
@param EAX Lower 32-bits of MSR value.
@@ -1381,7 +1381,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.3, "CCCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".
@param ECX MSR_PENTIUM_4_IQ_CCCRn
@param EAX Lower 32-bits of MSR value.
@@ -1412,7 +1412,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_BSU_ESCR0 (0x000003A0)
@param EAX Lower 32-bits of MSR value.
@@ -1431,7 +1431,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_BSU_ESCR1 (0x000003A1)
@param EAX Lower 32-bits of MSR value.
@@ -1450,7 +1450,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_FSB_ESCR0 (0x000003A2)
@param EAX Lower 32-bits of MSR value.
@@ -1469,7 +1469,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_FSB_ESCR1 (0x000003A3)
@param EAX Lower 32-bits of MSR value.
@@ -1488,7 +1488,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_FIRM_ESCR0 (0x000003A4)
@param EAX Lower 32-bits of MSR value.
@@ -1507,7 +1507,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_FIRM_ESCR1 (0x000003A5)
@param EAX Lower 32-bits of MSR value.
@@ -1526,7 +1526,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_FLAME_ESCR0 (0x000003A6)
@param EAX Lower 32-bits of MSR value.
@@ -1545,7 +1545,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_FLAME_ESCR1 (0x000003A7)
@param EAX Lower 32-bits of MSR value.
@@ -1564,7 +1564,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_DAC_ESCR0 (0x000003A8)
@param EAX Lower 32-bits of MSR value.
@@ -1583,7 +1583,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_DAC_ESCR1 (0x000003A9)
@param EAX Lower 32-bits of MSR value.
@@ -1602,7 +1602,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_MOB_ESCR0 (0x000003AA)
@param EAX Lower 32-bits of MSR value.
@@ -1621,7 +1621,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_MOB_ESCR1 (0x000003AB)
@param EAX Lower 32-bits of MSR value.
@@ -1640,7 +1640,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_PMH_ESCR0 (0x000003AC)
@param EAX Lower 32-bits of MSR value.
@@ -1659,7 +1659,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_PMH_ESCR1 (0x000003AD)
@param EAX Lower 32-bits of MSR value.
@@ -1678,7 +1678,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_SAAT_ESCR0 (0x000003AE)
@param EAX Lower 32-bits of MSR value.
@@ -1697,7 +1697,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_SAAT_ESCR1 (0x000003AF)
@param EAX Lower 32-bits of MSR value.
@@ -1716,7 +1716,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_U2L_ESCR0 (0x000003B0)
@param EAX Lower 32-bits of MSR value.
@@ -1735,7 +1735,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_U2L_ESCR1 (0x000003B1)
@param EAX Lower 32-bits of MSR value.
@@ -1754,7 +1754,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_BPU_ESCR0 (0x000003B2)
@param EAX Lower 32-bits of MSR value.
@@ -1773,7 +1773,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_BPU_ESCR1 (0x000003B3)
@param EAX Lower 32-bits of MSR value.
@@ -1792,7 +1792,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_IS_ESCR0 (0x000003B4)
@param EAX Lower 32-bits of MSR value.
@@ -1811,7 +1811,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_IS_ESCR1 (0x000003B5)
@param EAX Lower 32-bits of MSR value.
@@ -1830,7 +1830,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_ITLB_ESCR0 (0x000003B6)
@param EAX Lower 32-bits of MSR value.
@@ -1849,7 +1849,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_ITLB_ESCR1 (0x000003B7)
@param EAX Lower 32-bits of MSR value.
@@ -1868,7 +1868,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_CRU_ESCR0 (0x000003B8)
@param EAX Lower 32-bits of MSR value.
@@ -1887,7 +1887,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_CRU_ESCR1 (0x000003B9)
@param EAX Lower 32-bits of MSR value.
@@ -1906,9 +1906,9 @@ typedef union {
/**
- 0, 1, 2. Shared. See Section 18.15.1, "ESCR MSRs." This MSR is not available
- on later processors. It is only available on processor family 0FH, models
- 01H-02H.
+ 0, 1, 2. Shared. See Section 18.6.3.1, "ESCR MSRs." This MSR is not
+ available on later processors. It is only available on processor family 0FH,
+ models 01H-02H.
@param ECX MSR_PENTIUM_4_IQ_ESCR0 (0x000003BA)
@param EAX Lower 32-bits of MSR value.
@@ -1927,9 +1927,9 @@ typedef union {
/**
- 0, 1, 2. Shared. See Section 18.15.1, "ESCR MSRs." This MSR is not available
- on later processors. It is only available on processor family 0FH, models
- 01H-02H.
+ 0, 1, 2. Shared. See Section 18.6.3.1, "ESCR MSRs." This MSR is not
+ available on later processors. It is only available on processor family 0FH,
+ models 01H-02H.
@param ECX MSR_PENTIUM_4_IQ_ESCR1 (0x000003BB)
@param EAX Lower 32-bits of MSR value.
@@ -1948,7 +1948,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_RAT_ESCR0 (0x000003BC)
@param EAX Lower 32-bits of MSR value.
@@ -1967,7 +1967,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_RAT_ESCR1 (0x000003BD)
@param EAX Lower 32-bits of MSR value.
@@ -1986,7 +1986,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_SSU_ESCR0 (0x000003BE)
@param EAX Lower 32-bits of MSR value.
@@ -2005,7 +2005,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_MS_ESCR0 (0x000003C0)
@param EAX Lower 32-bits of MSR value.
@@ -2024,7 +2024,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_MS_ESCR1 (0x000003C1)
@param EAX Lower 32-bits of MSR value.
@@ -2043,7 +2043,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_TBPU_ESCR0 (0x000003C2)
@param EAX Lower 32-bits of MSR value.
@@ -2062,7 +2062,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_TBPU_ESCR1 (0x000003C3)
@param EAX Lower 32-bits of MSR value.
@@ -2081,7 +2081,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_TC_ESCR0 (0x000003C4)
@param EAX Lower 32-bits of MSR value.
@@ -2100,7 +2100,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_TC_ESCR1 (0x000003C5)
@param EAX Lower 32-bits of MSR value.
@@ -2119,7 +2119,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_IX_ESCR0 (0x000003C8)
@param EAX Lower 32-bits of MSR value.
@@ -2138,7 +2138,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_IX_ESCR1 (0x000003C9)
@param EAX Lower 32-bits of MSR value.
@@ -2157,7 +2157,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_ALF_ESCRn
@param EAX Lower 32-bits of MSR value.
@@ -2188,7 +2188,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_TC_PRECISE_EVENT (0x000003F0)
@param EAX Lower 32-bits of MSR value.
@@ -2236,7 +2236,7 @@ typedef union {
///
struct {
///
- /// [Bits 12:0] See Table 19-33.
+ /// [Bits 12:0] See Table 19-36.
///
UINT32 EventNum:13;
UINT32 Reserved1:11;
@@ -2247,7 +2247,7 @@ typedef union {
///
/// [Bit 25] ENABLE_PEBS_MY_THR (R/W) Enables PEBS for the target logical
/// processor when set; disables PEBS when clear (default). See Section
- /// 18.16.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target
+ /// 18.6.4.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target
/// logical processor. This bit is called ENABLE_PEBS in IA-32 processors
/// that do not support Intel HyperThreading Technology.
///
@@ -2255,7 +2255,7 @@ typedef union {
///
/// [Bit 26] ENABLE_PEBS_OTH_THR (R/W) Enables PEBS for the target logical
/// processor when set; disables PEBS when clear (default). See Section
- /// 18.16.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target
+ /// 18.6.4.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target
/// logical processor. This bit is reserved for IA-32 processors that do
/// not support Intel Hyper-Threading Technology.
///
@@ -2275,7 +2275,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Table 19-33.
+ 0, 1, 2, 3, 4, 6. Shared. See Table 19-36.
@param ECX MSR_PENTIUM_4_PEBS_MATRIX_VERT (0x000003F2)
@param EAX Lower 32-bits of MSR value.
@@ -2301,7 +2301,7 @@ typedef union {
680H-68FH, 6C0H-6CfH are not available in processor releases before family
0FH, model 03H. These MSRs replace MSRs previously located at
1DBH-1DEH.which performed the same function for early releases. See Section
- 17.10, "Last Branch, Call Stack, Interrupt, and Exception Recording for
+ 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for
Processors based on Skylake Microarchitecture.".
@param ECX MSR_PENTIUM_4_LASTBRANCH_n_FROM_IP
@@ -2357,7 +2357,7 @@ typedef union {
record registers on the last branch record stack (6C0H-6CFH). This part of
the stack contains pointers to the destination instruction for one of the
last 16 branches, exceptions, or interrupts that the processor took. See
- Section 17.10, "Last Branch, Call Stack, Interrupt, and Exception Recording
+ Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording
for Processors based on Skylake Microarchitecture.".
@param ECX MSR_PENTIUM_4_LASTBRANCH_n_TO_IP
@@ -2409,9 +2409,9 @@ typedef union {
/**
- 3, 4. Shared. IFSB BUSQ Event Control and Counter Register (R/W) See
- Section 18.21, "Performance Monitoring on 64-bit Intel Xeon Processor MP
- with Up to 8-MByte L3 Cache.".
+ 3, 4. Shared. IFSB BUSQ Event Control and Counter Register (R/W) See Section
+ 18.6.6, "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to
+ 8-MByte L3 Cache.".
@param ECX MSR_PENTIUM_4_IFSB_BUSQ0 (0x000107CC)
@param EAX Lower 32-bits of MSR value.
@@ -2449,9 +2449,9 @@ typedef union {
/**
- 3, 4. Shared. IFSB SNPQ Event Control and Counter Register (R/W) See
- Section 18.21, "Performance Monitoring on 64-bit Intel Xeon Processor MP
- with Up to 8-MByte L3 Cache.".
+ 3, 4. Shared. IFSB SNPQ Event Control and Counter Register (R/W) See Section
+ 18.6.6, "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to
+ 8-MByte L3 Cache.".
@param ECX MSR_PENTIUM_4_IFSB_SNPQ0 (0x000107CE)
@param EAX Lower 32-bits of MSR value.
@@ -2489,9 +2489,9 @@ typedef union {
/**
- 3, 4. Shared. EFSB DRDY Event Control and Counter Register (R/W) See
- Section 18.21, "Performance Monitoring on 64-bit Intel Xeon Processor MP
- with Up to 8-MByte L3 Cache" for details.
+ 3, 4. Shared. EFSB DRDY Event Control and Counter Register (R/W) See Section
+ 18.6.6, "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to
+ 8-MByte L3 Cache.".
@param ECX MSR_PENTIUM_4_EFSB_DRDY0 (0x000107D0)
@param EAX Lower 32-bits of MSR value.
@@ -2529,9 +2529,9 @@ typedef union {
/**
- 3, 4. Shared. IFSB Latency Event Control Register (R/W) See Section 18.21,
- "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte
- L3 Cache" for details.
+ 3, 4. Shared. IFSB Latency Event Control Register (R/W) See Section 18.6.6,
+ "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to 8-MByte
+ L3 Cache.".
@param ECX MSR_PENTIUM_4_IFSB_CTL6 (0x000107D2)
@param EAX Lower 32-bits of MSR value.
@@ -2550,8 +2550,8 @@ typedef union {
/**
- 3, 4. Shared. IFSB Latency Event Counter Register (R/W) See Section 18.21,
- "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte
+ 3, 4. Shared. IFSB Latency Event Counter Register (R/W) See Section 18.6.6,
+ "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to 8-MByte
L3 Cache.".
@param ECX MSR_PENTIUM_4_IFSB_CNTR7 (0x000107D3)
@@ -2571,9 +2571,9 @@ typedef union {
/**
- 6. Shared. GBUSQ Event Control and Counter Register (R/W) See Section 18.21,
- "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte
- L3 Cache.".
+ 6. Shared. GBUSQ Event Control and Counter Register (R/W) See Section
+ 18.6.6, "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to
+ 8MByte L3 Cache.".
@param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL0 (0x000107CC)
@param EAX Lower 32-bits of MSR value.
@@ -2611,9 +2611,9 @@ typedef union {
/**
- 6. Shared. GSNPQ Event Control and Counter Register (R/W) See Section
- 18.21, "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to
- 8-MByte L3 Cache.".
+ 6. Shared. GSNPQ Event Control and Counter Register (R/W) See Section
+ 18.6.6, "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to
+ 8MByte L3 Cache.".
@param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL2 (0x000107CE)
@param EAX Lower 32-bits of MSR value.
@@ -2651,9 +2651,9 @@ typedef union {
/**
- 6. Shared. FSB Event Control and Counter Register (R/W) See Section 18.21,
- "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte
- L3 Cache" for details.
+ 6. Shared. FSB Event Control and Counter Register (R/W) See Section 18.6.6,
+ "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8MByte
+ L3 Cache.".
@param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL4 (0x000107D0)
@param EAX Lower 32-bits of MSR value.
diff --git a/UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h b/UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h
index 70d54c81ee..7d7a1cebcf 100644
--- a/UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h
@@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
- Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.20.
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+ May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@@ -43,7 +43,7 @@
)
/**
- See Section 35.22, "MSRs in Pentium Processors.".
+ See Section 2.22, "MSRs in Pentium Processors.".
@param ECX MSR_PENTIUM_M_P5_MC_ADDR (0x00000000)
@param EAX Lower 32-bits of MSR value.
@@ -62,7 +62,7 @@
/**
- See Section 35.22, "MSRs in Pentium Processors.".
+ See Section 2.22, "MSRs in Pentium Processors.".
@param ECX MSR_PENTIUM_M_P5_MC_TYPE (0x00000001)
@param EAX Lower 32-bits of MSR value.
@@ -200,7 +200,7 @@ typedef union {
Last Branch Record n (R/W) One of 8 last branch record registers on the last
branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold
the to address. See also: - Last Branch Record Stack TOS at 1C9H - Section
- 17.13, "Last Branch, Interrupt, and Exception Recording (Pentium M
+ 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M
Processors)".
@param ECX MSR_PENTIUM_M_LASTBRANCH_n
@@ -498,7 +498,7 @@ typedef union {
/**
Debug Control (R/W) Controls how several debug features are used. Bit
- definitions are discussed in the referenced section. See Section 17.13,
+ definitions are discussed in the referenced section. See Section 17.15,
"Last Branch, Interrupt, and Exception Recording (Pentium M Processors).".
@param ECX MSR_PENTIUM_M_DEBUGCTLB (0x000001D9)
@@ -521,8 +521,8 @@ typedef union {
Last Exception Record To Linear IP (R) This area contains a pointer to the
target of the last branch instruction that the processor executed prior to
the last exception that was generated or the last interrupt that was
- handled. See Section 17.13, "Last Branch, Interrupt, and Exception Recording
- (Pentium M Processors)" and Section 17.14.2, "Last Branch and Last Exception
+ handled. See Section 17.15, "Last Branch, Interrupt, and Exception Recording
+ (Pentium M Processors)" and Section 17.16.2, "Last Branch and Last Exception
MSRs.".
@param ECX MSR_PENTIUM_M_LER_TO_LIP (0x000001DD)
@@ -544,8 +544,8 @@ typedef union {
Last Exception Record From Linear IP (R) Contains a pointer to the last
branch instruction that the processor executed prior to the last exception
that was generated or the last interrupt that was handled. See Section
- 17.13, "Last Branch, Interrupt, and Exception Recording (Pentium M
- Processors)" and Section 17.14.2, "Last Branch and Last Exception MSRs.".
+ 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M
+ Processors)" and Section 17.16.2, "Last Branch and Last Exception MSRs.".
@param ECX MSR_PENTIUM_M_LER_FROM_LIP (0x000001DE)
@param EAX Lower 32-bits of MSR value.
diff --git a/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h b/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h
index 9b2578bac8..e348dba8e2 100644
--- a/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h
@@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
- Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.22.
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+ May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@@ -83,7 +83,7 @@
/**
- See Section 17.15, "Time-Stamp Counter.".
+ See Section 17.17, "Time-Stamp Counter.".
@param ECX MSR_PENTIUM_TSC (0x00000010)
@param EAX Lower 32-bits of MSR value.
@@ -102,7 +102,7 @@
/**
- See Section 18.24.1, "Control and Event Select Register (CESR).".
+ See Section 18.6.9.1, "Control and Event Select Register (CESR).".
@param ECX MSR_PENTIUM_CESR (0x00000011)
@param EAX Lower 32-bits of MSR value.
@@ -121,7 +121,7 @@
/**
- Section 18.24.3, "Events Counted.".
+ Section 18.6.9.3, "Events Counted.".
@param ECX MSR_PENTIUM_CTRn
@param EAX Lower 32-bits of MSR value.
diff --git a/UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h b/UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
index c8a0b971d3..69dfac6034 100644
--- a/UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
@@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
- Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.9.
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+ May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@@ -88,7 +88,8 @@ typedef union {
/**
- Package. See http://biosbits.org.
+ Package. Platform Information Contains power management and other model
+ specific features enumeration. See http://biosbits.org.
@param ECX MSR_SANDY_BRIDGE_PLATFORM_INFO (0x000000CE)
@param EAX Lower 32-bits of MSR value.
@@ -359,7 +360,7 @@ typedef union {
/**
- Core. See Table 35-2; If CPUID.0AH:EAX[15:8] = 8.
+ Core. See Table 2-2. If CPUID.0AH:EAX[15:8] = 8.
@param ECX MSR_SANDY_BRIDGE_IA32_PERFEVTSELn
@param EAX Lower 32-bits of MSR value.
@@ -429,7 +430,7 @@ typedef union {
/**
- Thread. Clock Modulation (R/W) See Table 35-2 IA32_CLOCK_MODULATION MSR was
+ Thread. Clock Modulation (R/W) See Table 2-2. IA32_CLOCK_MODULATION MSR was
originally named IA32_THERM_CONTROL MSR.
@param ECX MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION (0x0000019A)
@@ -511,48 +512,48 @@ typedef union {
///
struct {
///
- /// [Bit 0] Thread. Fast-Strings Enable See Table 35-2.
+ /// [Bit 0] Thread. Fast-Strings Enable See Table 2-2.
///
UINT32 FastStrings:1;
UINT32 Reserved1:6;
///
- /// [Bit 7] Thread. Performance Monitoring Available (R) See Table 35-2.
+ /// [Bit 7] Thread. Performance Monitoring Available (R) See Table 2-2.
///
UINT32 PerformanceMonitoring:1;
UINT32 Reserved2:3;
///
- /// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 35-2.
+ /// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 2-2.
///
UINT32 BTS:1;
///
/// [Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See
- /// Table 35-2.
+ /// Table 2-2.
///
UINT32 PEBS:1;
UINT32 Reserved3:3;
///
/// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See
- /// Table 35-2.
+ /// Table 2-2.
///
UINT32 EIST:1;
UINT32 Reserved4:1;
///
- /// [Bit 18] Thread. ENABLE MONITOR FSM. (R/W) See Table 35-2.
+ /// [Bit 18] Thread. ENABLE MONITOR FSM (R/W) See Table 2-2.
///
UINT32 MONITOR:1;
UINT32 Reserved5:3;
///
- /// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 35-2.
+ /// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 2-2.
///
UINT32 LimitCpuidMaxval:1;
///
- /// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 35-2.
+ /// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 2-2.
///
UINT32 xTPR_Message_Disable:1;
UINT32 Reserved6:8;
UINT32 Reserved7:2;
///
- /// [Bit 34] Thread. XD Bit Disable (R/W) See Table 35-2.
+ /// [Bit 34] Thread. XD Bit Disable (R/W) See Table 2-2.
///
UINT32 XD:1;
UINT32 Reserved8:3;
@@ -750,8 +751,8 @@ typedef union {
/**
- Thread. Last Branch Record Filtering Select Register (R/W) See Section
- 17.7.2, "Filtering of Last Branch Records.".
+ Thread. Last Branch Record Filtering Select Register (R/W) See Section
+ 17.9.2, "Filtering of Last Branch Records.".
@param ECX MSR_SANDY_BRIDGE_LBR_SELECT (0x000001C8)
@param EAX Lower 32-bits of MSR value.
@@ -929,7 +930,7 @@ typedef union {
/**
- See Table 35-2. See Section 18.4.2, "Global Counter Control Facilities.".
+ See Table 2-2. See Section 18.6.2.2, "Global Counter Control Facilities.".
@param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS (0x0000038E)
@param EAX Lower 32-bits of MSR value.
@@ -1024,7 +1025,7 @@ typedef union {
/**
- Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control
+ Thread. See Table 2-2. See Section 18.6.2.2, "Global Counter Control
Facilities.".
@param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL (0x0000038F)
@@ -1112,7 +1113,7 @@ typedef union {
/**
- See Table 35-2. See Section 18.4.2, "Global Counter Control Facilities.".
+ See Table 2-2. See Section 18.6.2.2, "Global Counter Control Facilities.".
@param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390)
@param EAX Lower 32-bits of MSR value.
@@ -1207,7 +1208,7 @@ typedef union {
/**
- Thread. See Section 18.8.1.1, "Processor Event Based Sampling (PEBS).".
+ Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).".
@param ECX MSR_SANDY_BRIDGE_PEBS_ENABLE (0x000003F1)
@param EAX Lower 32-bits of MSR value.
@@ -1281,7 +1282,7 @@ typedef union {
/**
- Thread. see See Section 18.8.1.2, "Load Latency Performance Monitoring
+ Thread. See Section 18.3.1.1.2, "Load Latency Performance Monitoring
Facility.".
@param ECX MSR_SANDY_BRIDGE_PEBS_LD_LAT (0x000003F6)
@@ -1518,7 +1519,7 @@ typedef union {
/**
- Thread. Capability Reporting Register of EPT and VPID (R/O) See Table 35-2.
+ Thread. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2.
@param ECX MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM (0x0000048C)
@param EAX Lower 32-bits of MSR value.
@@ -2859,7 +2860,7 @@ typedef union {
///
/// [Bit 0] ENABLE_PEBS_NUM_ALT (RW) Write 1 to enable alternate PEBS
/// counting logic for specific events requiring additional configuration,
- /// see Table 19-15.
+ /// see Table 19-17.
///
UINT32 ENABLE_PEBS_NUM_ALT:1;
UINT32 Reserved1:31;
diff --git a/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h b/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
index ec09bf3c13..03bbd0af7c 100644
--- a/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
@@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
- Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.4.
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+ May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@@ -81,7 +81,7 @@ typedef union {
UINT32 Reserved2:19;
UINT32 Reserved3:18;
///
- /// [Bits 52:50] See Table 35-2.
+ /// [Bits 52:50] See Table 2-2.
///
UINT32 PlatformId:3;
UINT32 Reserved4:11;
@@ -181,7 +181,7 @@ typedef union {
/**
- Core. Control Features in Intel 64 Processor (R/W). See Table 35-2.
+ Core. Control Features in Intel 64 Processor (R/W). See Table 2-2.
@param ECX MSR_IA32_SILVERMONT_FEATURE_CONTROL (0x0000003A)
@param EAX Lower 32-bits of MSR value.
@@ -643,54 +643,54 @@ typedef union {
///
struct {
///
- /// [Bit 0] Core. Fast-Strings Enable See Table 35-2.
+ /// [Bit 0] Core. Fast-Strings Enable See Table 2-2.
///
UINT32 FastStrings:1;
UINT32 Reserved1:2;
///
/// [Bit 3] Module. Automatic Thermal Control Circuit Enable (R/W) See
- /// Table 35-2. Default value is 0.
+ /// Table 2-2. Default value is 0.
///
UINT32 AutomaticThermalControlCircuit:1;
UINT32 Reserved2:3;
///
- /// [Bit 7] Core. Performance Monitoring Available (R) See Table 35-2.
+ /// [Bit 7] Core. Performance Monitoring Available (R) See Table 2-2.
///
UINT32 PerformanceMonitoring:1;
UINT32 Reserved3:3;
///
- /// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 35-2.
+ /// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 2-2.
///
UINT32 BTS:1;
///
/// [Bit 12] Core. Processor Event Based Sampling Unavailable (RO) See
- /// Table 35-2.
+ /// Table 2-2.
///
UINT32 PEBS:1;
UINT32 Reserved4:3;
///
/// [Bit 16] Module. Enhanced Intel SpeedStep Technology Enable (R/W) See
- /// Table 35-2.
+ /// Table 2-2.
///
UINT32 EIST:1;
UINT32 Reserved5:1;
///
- /// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 35-2.
+ /// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 2-2.
///
UINT32 MONITOR:1;
UINT32 Reserved6:3;
///
- /// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 35-2.
+ /// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 2-2.
///
UINT32 LimitCpuidMaxval:1;
///
- /// [Bit 23] Module. xTPR Message Disable (R/W) See Table 35-2.
+ /// [Bit 23] Module. xTPR Message Disable (R/W) See Table 2-2.
///
UINT32 xTPR_Message_Disable:1;
UINT32 Reserved7:8;
UINT32 Reserved8:2;
///
- /// [Bit 34] Core. XD Bit Disable (R/W) See Table 35-2.
+ /// [Bit 34] Core. XD Bit Disable (R/W) See Table 2-2.
///
UINT32 XD:1;
UINT32 Reserved9:3;
@@ -941,8 +941,8 @@ typedef union {
/**
- Core. Last Branch Record Filtering Select Register (R/W) See Section
- 17.7.2, "Filtering of Last Branch Records.".
+ Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2,
+ "Filtering of Last Branch Records.".
@param ECX MSR_SILVERMONT_LBR_SELECT (0x000001C8)
@param EAX Lower 32-bits of MSR value.
@@ -1082,7 +1082,7 @@ typedef union {
/**
- Core. See Table 35-2. See Section 18.4.4, "Processor Event Based Sampling
+ Core. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling
(PEBS).".
@param ECX MSR_SILVERMONT_PEBS_ENABLE (0x000003F1)
@@ -1173,7 +1173,7 @@ typedef union {
/**
- Core. Capability Reporting Register of EPT and VPID (R/O) See Table 35-2.
+ Core. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2.
@param ECX MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM (0x0000048C)
@param EAX Lower 32-bits of MSR value.
@@ -1191,8 +1191,8 @@ typedef union {
/**
- Core. Capability Reporting Register of VM-function Controls (R/O) See Table
- 35-2.
+ Core. Capability Reporting Register of VM-Function Controls (R/O) See Table
+ 2-2.
@param ECX MSR_SILVERMONT_IA32_VMX_FMFUNC (0x00000491)
@param EAX Lower 32-bits of MSR value.
@@ -1323,8 +1323,8 @@ typedef union {
///
struct {
///
- /// [Bits 14:0] Package Power Limit #1. (R/W) See Section 14.9.3, "Package
- /// RAPL Domain." and MSR_RAPL_POWER_UNIT in Table 35-8.
+ /// [Bits 14:0] Package Power Limit #1 (R/W) See Section 14.9.3, "Package
+ /// RAPL Domain." and MSR_RAPL_POWER_UNIT in Table 2-8.
///
UINT32 Limit:15;
///
@@ -1358,7 +1358,7 @@ typedef union {
/**
Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain."
- and MSR_RAPL_POWER_UNIT in Table 35-8.
+ and MSR_RAPL_POWER_UNIT in Table 2-8.
@param ECX MSR_SILVERMONT_PKG_ENERGY_STATUS (0x00000611)
@param EAX Lower 32-bits of MSR value.
@@ -1376,8 +1376,8 @@ typedef union {
/**
- Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
- Domains." and MSR_RAPL_POWER_UNIT in Table 35-8.
+ Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL Domains."
+ and MSR_RAPL_POWER_UNIT in Table 2-8.
@param ECX MSR_SILVERMONT_PP0_ENERGY_STATUS (0x00000639)
@param EAX Lower 32-bits of MSR value.
diff --git a/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h b/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
index 7166e5f9e0..866fe30f05 100644
--- a/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
@@ -1,12 +1,12 @@
/** @file
- MSR Definitions for Intel processors based on the Skylake microarchitecture.
+ MSR Defintions for Intel processors based on the Skylake/Kabylake/Coffeelake/Cannonlake microarchitecture.
Provides defines for Machine Specific Registers(MSR) indexes. Data structures
are provided for MSRs that contain one or more bit fields. If the MSR value
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
- Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.15.
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+ May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@@ -163,7 +163,7 @@ typedef union {
/**
- See Table 35-2. See Section 18.2.4, "Architectural Performance Monitoring
+ See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring
Version 4.".
@param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS (0x0000038E)
@@ -275,7 +275,7 @@ typedef union {
/**
- See Table 35-2. See Section 18.2.4, "Architectural Performance Monitoring
+ See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring
Version 4.".
@param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)
@@ -388,7 +388,7 @@ typedef union {
/**
- See Table 35-2. See Section 18.2.4, "Architectural Performance Monitoring
+ See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring
Version 4.".
@param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)
diff --git a/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h b/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h
index ad7128ae95..0951c0a5ea 100644
--- a/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h
@@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
- Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.7.
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+ May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@@ -183,7 +183,7 @@ typedef union {
/**
- Package. See Table 35-2.
+ Package. See Table 2-2.
@param ECX MSR_XEON_5600_IA32_ENERGY_PERF_BIAS (0x000001B0)
@param EAX Lower 32-bits of MSR value.
diff --git a/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h b/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
index 7b31288a35..cf013ea887 100644
--- a/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
@@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
- Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.14.
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+ May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@@ -72,11 +72,11 @@ typedef union {
///
struct {
///
- /// [Bit 0] LockOut (R/WO) See Table 35-24.
+ /// [Bit 0] LockOut (R/WO) See Table 2-25.
///
UINT32 LockOut:1;
///
- /// [Bit 1] Enable_PPIN (R/W) See Table 35-24.
+ /// [Bit 1] Enable_PPIN (R/W) See Table 2-25.
///
UINT32 Enable_PPIN:1;
UINT32 Reserved1:30;
@@ -95,7 +95,7 @@ typedef union {
/**
Package. Protected Processor Inventory Number (R/O). Protected Processor
- Inventory Number (R/O) See Table 35-24.
+ Inventory Number (R/O) See Table 2-25.
@param ECX MSR_XEON_D_PPIN (0x0000004F)
@param EAX Lower 32-bits of MSR value.
@@ -142,33 +142,33 @@ typedef union {
struct {
UINT32 Reserved1:8;
///
- /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 35-24.
+ /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 2-25.
///
UINT32 MaximumNonTurboRatio:8;
UINT32 Reserved2:7;
///
- /// [Bit 23] Package. PPIN_CAP (R/O) See Table 35-24.
+ /// [Bit 23] Package. PPIN_CAP (R/O) See Table 2-25.
///
UINT32 PPIN_CAP:1;
UINT32 Reserved3:4;
///
/// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See
- /// Table 35-24.
+ /// Table 2-25.
///
UINT32 RatioLimit:1;
///
/// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See
- /// Table 35-24.
+ /// Table 2-25.
///
UINT32 TDPLimit:1;
///
- /// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 35-24.
+ /// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 2-25.
///
UINT32 TJOFFSET:1;
UINT32 Reserved4:1;
UINT32 Reserved5:8;
///
- /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 35-24.
+ /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 2-25.
///
UINT32 MaximumEfficiencyRatio:8;
UINT32 Reserved6:16;
@@ -434,11 +434,11 @@ typedef union {
struct {
UINT32 Reserved1:16;
///
- /// [Bits 23:16] Temperature Target (RO) See Table 35-24.
+ /// [Bits 23:16] Temperature Target (RO) See Table 2-25.
///
UINT32 TemperatureTarget:8;
///
- /// [Bits 27:24] TCC Activation Offset (R/W) See Table 35-24.
+ /// [Bits 27:24] TCC Activation Offset (R/W) See Table 2-25.
///
UINT32 TCCActivationOffset:4;
UINT32 Reserved2:4;
diff --git a/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h b/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h
index d509660c52..c950bb620a 100644
--- a/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h
@@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
- Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.8.
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+ May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
diff --git a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
index 43354d15c9..d7aa3ae850 100644
--- a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
@@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
- Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.17.
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+ May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@@ -804,7 +804,7 @@ typedef union {
/**
- Thread. See Table 35-2.
+ Thread. See Table 2-2.
@param ECX MSR_XEON_PHI_PEBS_ENABLE (0x000003F1)
@param EAX Lower 32-bits of MSR value.
@@ -943,7 +943,7 @@ typedef union {
/**
- Core. Capability Reporting Register of EPT and VPID (R/O) See Table 35-2.
+ Core. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2.
@param ECX MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM (0x0000048C)
@param EAX Lower 32-bits of MSR value.
@@ -961,8 +961,8 @@ typedef union {
/**
- Core. Capability Reporting Register of VM-function Controls (R/O) See Table
- 35-2.
+ Core. Capability Reporting Register of VM-Function Controls (R/O) See Table
+ 2-2.
@param ECX MSR_XEON_PHI_IA32_VMX_FMFUNC (0x00000491)
@param EAX Lower 32-bits of MSR value.
@@ -1251,7 +1251,7 @@ typedef union {
/**
- Package. Base TDP Ratio (R/O) See Table 35-23.
+ Package. Base TDP Ratio (R/O) See Table 2-24.
@param ECX MSR_XEON_PHI_CONFIG_TDP_NOMINAL (0x00000648)
@param EAX Lower 32-bits of MSR value.
@@ -1269,7 +1269,7 @@ typedef union {
/**
- Package. ConfigTDP Level 1 ratio and power level (R/O). See Table 35-23.
+ Package. ConfigTDP Level 1 ratio and power level (R/O) See Table 2-24.
@param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL1 (0x00000649)
@param EAX Lower 32-bits of MSR value.
@@ -1287,7 +1287,7 @@ typedef union {
/**
- Package. ConfigTDP Level 2 ratio and power level (R/O). See Table 35-23.
+ Package. ConfigTDP Level 2 ratio and power level (R/O) See Table 2-24.
@param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL2 (0x0000064A)
@param EAX Lower 32-bits of MSR value.
@@ -1305,7 +1305,7 @@ typedef union {
/**
- Package. ConfigTDP Control (R/W) See Table 35-23.
+ Package. ConfigTDP Control (R/W) See Table 2-24.
@param ECX MSR_XEON_PHI_CONFIG_TDP_CONTROL (0x0000064B)
@param EAX Lower 32-bits of MSR value.
@@ -1324,7 +1324,7 @@ typedef union {
/**
- Package. ConfigTDP Control (R/W) See Table 35-23.
+ Package. ConfigTDP Control (R/W) See Table 2-24.
@param ECX MSR_XEON_PHI_TURBO_ACTIVATION_RATIO (0x0000064C)
@param EAX Lower 32-bits of MSR value.
--
2.15.0.windows.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Patch v3 02/14] UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h: Add new MSR file for goldmont plus microarchitecture.
2018-09-25 2:08 [Patch v3 00/14] Update MSR definitions Eric Dong
2018-09-25 2:08 ` [Patch v3 01/14] UefiCpuPkg/Include/Register/Msr: Update reference spec info Eric Dong
@ 2018-09-25 2:08 ` Eric Dong
2018-09-25 2:08 ` [Patch v3 03/14] UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h: Add new MSR Eric Dong
` (13 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Eric Dong @ 2018-09-25 2:08 UTC (permalink / raw)
To: edk2-devel; +Cc: Michael D Kinney, Ruiyu Ni, Laszlo Ersek
Changes includes:
1. Add new MSR file which used for goldmont plus microarchitecture.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong <eric.dong@intel.com>
---
UefiCpuPkg/Include/Register/Msr.h | 7 +-
UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h | 272 ++++++++++++++++++++++
2 files changed, 276 insertions(+), 3 deletions(-)
create mode 100644 UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h
diff --git a/UefiCpuPkg/Include/Register/Msr.h b/UefiCpuPkg/Include/Register/Msr.h
index 0ac8d5bdfd..abe0e136de 100644
--- a/UefiCpuPkg/Include/Register/Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr.h
@@ -6,7 +6,7 @@
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2016 ~ 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -16,8 +16,8 @@
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Specification Reference:
- Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- September 2016, Chapter 35 Model-Specific-Registers (MSR), Chapter 35.
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+ May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
@@ -29,6 +29,7 @@
#include <Register/Msr/AtomMsr.h>
#include <Register/Msr/SilvermontMsr.h>
#include <Register/Msr/GoldmontMsr.h>
+#include <Register/Msr/GoldmontPlusMsr.h>
#include <Register/Msr/NehalemMsr.h>
#include <Register/Msr/Xeon5600Msr.h>
#include <Register/Msr/XeonE7Msr.h>
diff --git a/UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h b/UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h
new file mode 100644
index 0000000000..d050464b7f
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h
@@ -0,0 +1,272 @@
+/** @file
+ MSR Defintions for Intel Atom processors based on the Goldmont Plus microarchitecture.
+
+ Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+ are provided for MSRs that contain one or more bit fields. If the MSR value
+ returned is a single 32-bit or 64-bit value, then a data structure is not
+ provided for that MSR.
+
+ Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ @par Specification Reference:
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+ May 2018, Volume 4: Model-Specific-Registers (MSR)
+
+**/
+
+#ifndef __GOLDMONT_PLUS_MSR_H__
+#define __GOLDMONT_PLUS_MSR_H__
+
+#include <Register/ArchitecturalMsr.h>
+
+/**
+ Is Intel Atom processors based on the Goldmont plus microarchitecture?
+
+ @param DisplayFamily Display Family ID
+ @param DisplayModel Display Model ID
+
+ @retval TRUE Yes, it is.
+ @retval FALSE No, it isn't.
+**/
+#define IS_GOLDMONT_PLUS_PROCESSOR(DisplayFamily, DisplayModel) \
+ (DisplayFamily == 0x06 && \
+ ( \
+ DisplayModel == 0x7A \
+ ) \
+ )
+
+/**
+ Core. (R/W) See Table 2-2. See Section 18.6.2.4, "Processor Event Based
+ Sampling (PEBS).".
+
+ @param ECX MSR_GOLDMONT_PLUS_PEBS_ENABLE (0x000003F1)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PLUS_PEBS_ENABLE);
+ AsmWriteMsr64 (MSR_GOLDMONT_PLUS_PEBS_ENABLE, Msr.Uint64);
+ @endcode
+**/
+#define MSR_GOLDMONT_PLUS_PEBS_ENABLE 0x000003F1
+
+/**
+ MSR information returned for MSR index #MSR_GOLDMONT_PLUS_PEBS_ENABLE
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 0] Enable PEBS trigger and recording for the programmed event
+ /// (precise or otherwise) on IA32_PMC0.
+ ///
+ UINT32 Fix_Me_1:1;
+ ///
+ /// [Bit 1] Enable PEBS trigger and recording for the programmed event
+ /// (precise or otherwise) on IA32_PMC1.
+ ///
+ UINT32 Fix_Me_2:1;
+ ///
+ /// [Bit 2] Enable PEBS trigger and recording for the programmed event
+ /// (precise or otherwise) on IA32_PMC2.
+ ///
+ UINT32 Fix_Me_3:1;
+ ///
+ /// [Bit 3] Enable PEBS trigger and recording for the programmed event
+ /// (precise or otherwise) on IA32_PMC3.
+ ///
+ UINT32 Fix_Me_4:1;
+ UINT32 Reserved1:28;
+ ///
+ /// [Bit 32] Enable PEBS trigger and recording for IA32_FIXED_CTR0.
+ ///
+ UINT32 Fix_Me_5:1;
+ ///
+ /// [Bit 33] Enable PEBS trigger and recording for IA32_FIXED_CTR1.
+ ///
+ UINT32 Fix_Me_6:1;
+ ///
+ /// [Bit 34] Enable PEBS trigger and recording for IA32_FIXED_CTR2.
+ ///
+ UINT32 Fix_Me_7:1;
+ UINT32 Reserved2:29;
+ } Bits;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER;
+
+
+/**
+ Core. Last Branch Record N From IP (R/W) One of the three MSRs that make up
+ the first entry of the 32-entry LBR stack. The From_IP part of the stack
+ contains pointers to the source instruction. See also: - Last Branch Record
+ Stack TOS at 1C9H. - Section 17.7, "Last Branch, Call Stack, Interrupt, and
+ .. Exception Recording for Processors based on Goldmont Plus
+ Microarchitecture.".
+
+ @param ECX MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP (0x0000068N)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP);
+ AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP, Msr);
+ @endcode
+**/
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_0_FROM_IP 0x00000680
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_1_FROM_IP 0x00000681
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_2_FROM_IP 0x00000682
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_3_FROM_IP 0x00000683
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_4_FROM_IP 0x00000684
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_5_FROM_IP 0x00000685
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_6_FROM_IP 0x00000686
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_7_FROM_IP 0x00000687
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_8_FROM_IP 0x00000688
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_9_FROM_IP 0x00000689
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_10_FROM_IP 0x0000068A
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_11_FROM_IP 0x0000068B
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_12_FROM_IP 0x0000068C
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_13_FROM_IP 0x0000068D
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_14_FROM_IP 0x0000068E
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_15_FROM_IP 0x0000068F
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_16_FROM_IP 0x00000690
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_17_FROM_IP 0x00000691
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_18_FROM_IP 0x00000692
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_19_FROM_IP 0x00000693
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_20_FROM_IP 0x00000694
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_21_FROM_IP 0x00000695
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_22_FROM_IP 0x00000696
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_23_FROM_IP 0x00000697
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_24_FROM_IP 0x00000698
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_25_FROM_IP 0x00000699
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_26_FROM_IP 0x0000069A
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_27_FROM_IP 0x0000069B
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_28_FROM_IP 0x0000069C
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_29_FROM_IP 0x0000069D
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_30_FROM_IP 0x0000069E
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_31_FROM_IP 0x0000069F
+
+/**
+ Core. Last Branch Record N To IP (R/W) One of the three MSRs that make up
+ the first entry of the 32-entry LBR stack. The To_IP part of the stack
+ contains pointers to the Destination instruction. See also: - Section 17.7,
+ "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors
+ based on Goldmont Plus Microarchitecture.".
+
+ @param ECX MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP (0x000006C0)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP);
+ AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP, Msr);
+ @endcode
+**/
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_0_TO_IP 0x000006C0
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_1_TO_IP 0x000006C1
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_2_TO_IP 0x000006C2
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_3_TO_IP 0x000006C3
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_4_TO_IP 0x000006C4
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_5_TO_IP 0x000006C5
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_6_TO_IP 0x000006C6
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_7_TO_IP 0x000006C7
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_8_TO_IP 0x000006C8
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_9_TO_IP 0x000006C9
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_10_TO_IP 0x000006CA
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_11_TO_IP 0x000006CB
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_12_TO_IP 0x000006CC
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_13_TO_IP 0x000006CD
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_14_TO_IP 0x000006CE
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_15_TO_IP 0x000006CF
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_16_TO_IP 0x000006D0
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_17_TO_IP 0x000006D1
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_18_TO_IP 0x000006D2
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_19_TO_IP 0x000006D3
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_20_TO_IP 0x000006D4
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_21_TO_IP 0x000006D5
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_22_TO_IP 0x000006D6
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_23_TO_IP 0x000006D7
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_24_TO_IP 0x000006D8
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_25_TO_IP 0x000006D9
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_26_TO_IP 0x000006DA
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_27_TO_IP 0x000006DB
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_28_TO_IP 0x000006DC
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_29_TO_IP 0x000006DD
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_30_TO_IP 0x000006DE
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_31_TO_IP 0x000006DF
+
+
+/**
+ Core. Last Branch Record N Additional Information (R/W) One of the three
+ MSRs that make up the first entry of the 32-entry LBR stack. This part of
+ the stack contains flag and elapsed cycle information. See also: - Last
+ Branch Record Stack TOS at 1C9H. - Section 17.9.1, "LBR Stack.".
+
+ @param ECX MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N (0x00000DCN)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N);
+ AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N, Msr);
+ @endcode
+**/
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_0 0x00000DC0
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_1 0x00000DC1
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_2 0x00000DC2
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_3 0x00000DC3
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_4 0x00000DC4
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_5 0x00000DC5
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_6 0x00000DC6
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_7 0x00000DC7
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_8 0x00000DC8
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_9 0x00000DC9
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_10 0x00000DCA
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_11 0x00000DCB
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_12 0x00000DCC
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_13 0x00000DCD
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_14 0x00000DCE
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_15 0x00000DCF
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_16 0x00000DD0
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_17 0x00000DD1
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_18 0x00000DD2
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_19 0x00000DD3
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_20 0x00000DD4
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_21 0x00000DD5
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_22 0x00000DD6
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_23 0x00000DD7
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_24 0x00000DD8
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_25 0x00000DD9
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_26 0x00000DDA
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_27 0x00000DDB
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_28 0x00000DDC
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_29 0x00000DDD
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_30 0x00000DDE
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_31 0x00000DDF
+
+#endif
--
2.15.0.windows.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Patch v3 03/14] UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h: Add new MSR.
2018-09-25 2:08 [Patch v3 00/14] Update MSR definitions Eric Dong
2018-09-25 2:08 ` [Patch v3 01/14] UefiCpuPkg/Include/Register/Msr: Update reference spec info Eric Dong
2018-09-25 2:08 ` [Patch v3 02/14] UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h: Add new MSR file for goldmont plus microarchitecture Eric Dong
@ 2018-09-25 2:08 ` Eric Dong
2018-09-25 2:08 ` [Patch v3 04/14] UefiCpuPkg/Include/Register/Msr/*.h: " Eric Dong
` (12 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Eric Dong @ 2018-09-25 2:08 UTC (permalink / raw)
To: edk2-devel; +Cc: Michael D Kinney, Ruiyu Ni, Laszlo Ersek
Changes includes:
1. Add new MSR: MSR_SILVERMONT_PLATFORM_INFO
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong <eric.dong@intel.com>
---
UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h | 48 +++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h b/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
index 03bbd0af7c..c3d0f8c208 100644
--- a/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
@@ -375,6 +375,54 @@ typedef union {
} MSR_SILVERMONT_FSB_FREQ_REGISTER;
+/**
+ Package. Platform Information: Contains power management and other model
+ specific features enumeration. See http://biosbits.org.
+
+ @param ECX MSR_SILVERMONT_PLATFORM_INFO (0x000000CE)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_SILVERMONT_PLATFORM_INFO_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_SILVERMONT_PLATFORM_INFO_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_SILVERMONT_PLATFORM_INFO_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PLATFORM_INFO);
+ AsmWriteMsr64 (MSR_SILVERMONT_PLATFORM_INFO, Msr.Uint64);
+ @endcode
+**/
+#define MSR_SILVERMONT_PLATFORM_INFO 0x000000CE
+
+/**
+ MSR information returned for MSR index #MSR_SILVERMONT_PLATFORM_INFO
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ UINT32 Reserved1:8;
+ ///
+ /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) This is the ratio
+ /// of the maximum frequency that does not require turbo. Frequency =
+ /// ratio * Scalable Bus Frequency.
+ ///
+ UINT32 MaximumNon_TurboRatio:8;
+ UINT32 Reserved2:16;
+ UINT32 Reserved3:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_SILVERMONT_PLATFORM_INFO_REGISTER;
+
/**
Module. C-State Configuration Control (R/W) Note: C-state values are
processor specific C-state code names, unrelated to MWAIT extension C-state
--
2.15.0.windows.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Patch v3 04/14] UefiCpuPkg/Include/Register/Msr/*.h: Add new MSR.
2018-09-25 2:08 [Patch v3 00/14] Update MSR definitions Eric Dong
` (2 preceding siblings ...)
2018-09-25 2:08 ` [Patch v3 03/14] UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h: Add new MSR Eric Dong
@ 2018-09-25 2:08 ` Eric Dong
2018-09-25 2:08 ` [Patch v3 05/14] UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h: " Eric Dong
` (11 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Eric Dong @ 2018-09-25 2:08 UTC (permalink / raw)
To: edk2-devel; +Cc: Michael D Kinney, Ruiyu Ni, Laszlo Ersek
Changes includes:
1. Add new MSR: MSR_*_MSRUNCORE_RATIO_LIMIT
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong <eric.dong@intel.com>
---
UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h | 54 +++++++++++++++++++++++++
UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h | 56 +++++++++++++++++++++++++-
UefiCpuPkg/Include/Register/Msr/XeonDMsr.h | 56 +++++++++++++++++++++++++-
3 files changed, 164 insertions(+), 2 deletions(-)
diff --git a/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h b/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
index 4e50f72008..a7a1967420 100644
--- a/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
@@ -285,6 +285,60 @@ typedef union {
} MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER;
+/**
+ Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
+ fields represent the widest possible range of uncore frequencies. Writing to
+ these fields allows software to control the minimum and the maximum
+ frequency that hardware will select.
+
+ @param ECX MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT (0x00000620)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT);
+ AsmWriteMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
+ @endcode
+**/
+#define MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT 0x00000620
+
+/**
+ MSR information returned for MSR index #MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
+ /// LLC/Ring.
+ ///
+ UINT32 MAX_RATIO:7;
+ UINT32 Reserved2:1;
+ ///
+ /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
+ /// possible ratio of the LLC/Ring.
+ ///
+ UINT32 MIN_RATIO:7;
+ UINT32 Reserved3:17;
+ UINT32 Reserved4:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER;
+
/**
Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
Domains.".
diff --git a/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h b/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
index a75bdb2e13..985183b320 100644
--- a/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
@@ -846,7 +846,61 @@ typedef union {
/**
- Package. Reserved (R/O) Reads return 0.
+ Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
+ fields represent the widest possible range of uncore frequencies. Writing to
+ these fields allows software to control the minimum and the maximum
+ frequency that hardware will select.
+
+ @param ECX MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT (0x00000620)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT);
+ AsmWriteMsr64 (MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
+ @endcode
+**/
+#define MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT 0x00000620
+
+/**
+ MSR information returned for MSR index #MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
+ /// LLC/Ring.
+ ///
+ UINT32 MAX_RATIO:7;
+ UINT32 Reserved1:1;
+ ///
+ /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
+ /// possible ratio of the LLC/Ring.
+ ///
+ UINT32 MIN_RATIO:7;
+ UINT32 Reserved2:17;
+ UINT32 Reserved3:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER;
+
+/**
+ Package. Reserved (R/O) Reads return 0.
@param ECX MSR_HASWELL_E_PP0_ENERGY_STATUS (0x00000639)
@param EAX Lower 32-bits of MSR value.
diff --git a/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h b/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
index cf013ea887..6dc4ee999e 100644
--- a/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
@@ -754,7 +754,61 @@ typedef union {
/**
- Package. Reserved (R/O) Reads return 0.
+ Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
+ fields represent the widest possible range of uncore frequencies. Writing to
+ these fields allows software to control the minimum and the maximum
+ frequency that hardware will select.
+
+ @param ECX MSR_XEON_D_MSRUNCORE_RATIO_LIMIT (0x00000620)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_MSRUNCORE_RATIO_LIMIT);
+ AsmWriteMsr64 (MSR_XEON_D_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
+ @endcode
+**/
+#define MSR_XEON_D_MSRUNCORE_RATIO_LIMIT 0x00000620
+
+/**
+ MSR information returned for MSR index #MSR_XEON_D_MSRUNCORE_RATIO_LIMIT
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
+ /// LLC/Ring.
+ ///
+ UINT32 MAX_RATIO:7;
+ UINT32 Reserved1:1;
+ ///
+ /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
+ /// possible ratio of the LLC/Ring.
+ ///
+ UINT32 MIN_RATIO:7;
+ UINT32 Reserved2:17;
+ UINT32 Reserved3:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER;
+
+/**
+ Package. Reserved (R/O) Reads return 0.
@param ECX MSR_XEON_D_PP0_ENERGY_STATUS (0x00000639)
@param EAX Lower 32-bits of MSR value.
--
2.15.0.windows.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Patch v3 05/14] UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h: Add new MSR.
2018-09-25 2:08 [Patch v3 00/14] Update MSR definitions Eric Dong
` (3 preceding siblings ...)
2018-09-25 2:08 ` [Patch v3 04/14] UefiCpuPkg/Include/Register/Msr/*.h: " Eric Dong
@ 2018-09-25 2:08 ` Eric Dong
2018-09-25 2:08 ` [Patch v3 06/14] UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h: Add new MSRs Eric Dong
` (10 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Eric Dong @ 2018-09-25 2:08 UTC (permalink / raw)
To: edk2-devel; +Cc: Michael D Kinney, Ruiyu Ni, Laszlo Ersek
Changes includes:
1. Add new MSR definition:
1. MSR_XEON_PHI_PPIN_CTL
2. MSR_XEON_PHI_PPIN
3. MSR_XEON_PHI_MISC_FEATURE_ENABLES
4. MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT
2. Add DisplayModule == 0x85 supports.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong <eric.dong@intel.com>
---
UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h | 249 ++++++++++++++++++++++++++-
1 file changed, 246 insertions(+), 3 deletions(-)
diff --git a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
index d7aa3ae850..da74c2402c 100644
--- a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
@@ -38,7 +38,8 @@
#define IS_XEON_PHI_PROCESSOR(DisplayFamily, DisplayModel) \
(DisplayFamily == 0x06 && \
( \
- DisplayModel == 0x57 \
+ DisplayModel == 0x57 || \
+ DisplayModel == 0x85 \
) \
)
@@ -85,9 +86,89 @@ typedef union {
UINT64 Uint64;
} MSR_XEON_PHI_SMI_COUNT_REGISTER;
+/**
+ Package. Protected Processor Inventory Number Enable Control (R/W).
+
+ @param ECX MSR_XEON_PHI_PPIN_CTL (0x0000004E)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_XEON_PHI_PPIN_CTL_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_XEON_PHI_PPIN_CTL_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_XEON_PHI_PPIN_CTL_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PPIN_CTL);
+ AsmWriteMsr64 (MSR_XEON_PHI_PPIN_CTL, Msr.Uint64);
+ @endcode
+**/
+#define MSR_XEON_PHI_PPIN_CTL 0x0000004E
/**
- Package. See http://biosbits.org.
+ MSR information returned for MSR index #MSR_XEON_PHI_PPIN_CTL
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 0] LockOut (R/WO) Set 1 to prevent further writes to
+ /// MSR_PPIN_CTL. Writing 1 to MSR_PPINCTL[bit 0] is permitted only if
+ /// MSR_PPIN_CTL[bit 1] is clear. Default is 0. BIOS should provide an
+ /// opt-in menu to enable the user to turn on MSR_PPIN_CTL[bit 1] for a
+ /// privileged inventory initialization agent to access MSR_PPIN. After
+ /// reading MSR_PPIN, the privileged inventory initialization agent should
+ /// write '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and
+ /// prevent unauthorized modification to MSR_PPIN_CTL.
+ ///
+ UINT32 LockOut:1;
+ ///
+ /// [Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible
+ /// using RDMSR. Once set, an attempt to write 1 to MSR_PPIN_CTL[bit 0]
+ /// will cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP.
+ /// Default is 0.
+ ///
+ UINT32 Enable_PPIN:1;
+ UINT32 Reserved1:30;
+ UINT32 Reserved2:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_XEON_PHI_PPIN_CTL_REGISTER;
+
+
+/**
+ Package. Protected Processor Inventory Number (R/O). Protected Processor
+ Inventory Number (R/O) A unique value within a given CPUID
+ family/model/stepping signature that a privileged inventory initialization
+ agent can access to identify each physical processor, when access to
+ MSR_PPIN is enabled. Access to MSR_PPIN is permitted only if
+ MSR_PPIN_CTL[bits 1:0] = '10b'.
+
+ @param ECX MSR_XEON_PHI_PPIN (0x0000004F)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_XEON_PHI_PPIN);
+ @endcode
+**/
+#define MSR_XEON_PHI_PPIN 0x0000004F
+
+/**
+ Package. Platform Information Contains power management and other model
+ specific features enumeration. See http://biosbits.org.
@param ECX MSR_XEON_PHI_PLATFORM_INFO (0x000000CE)
@param EAX Lower 32-bits of MSR value.
@@ -317,6 +398,56 @@ typedef union {
} MSR_XEON_PHI_FEATURE_CONFIG_REGISTER;
+/**
+ Thread. MISC_FEATURE_ENABLES.
+
+ @param ECX MSR_XEON_PHI_MISC_FEATURE_ENABLES (0x00000140)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MISC_FEATURE_ENABLES);
+ AsmWriteMsr64 (MSR_XEON_PHI_MISC_FEATURE_ENABLES, Msr.Uint64);
+ @endcode
+**/
+#define MSR_XEON_PHI_MISC_FEATURE_ENABLES 0x00000140
+
+/**
+ MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_ENABLES
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ UINT32 Reserved1:1;
+ ///
+ /// [Bit 1] User Mode MONITOR and MWAIT (R/W) If set to 1, the MONITOR and
+ /// MWAIT instructions do not cause invalid-opcode exceptions when
+ /// executed with CPL > 0 or in virtual-8086 mode. If MWAIT is executed
+ /// when CPL > 0 or in virtual-8086 mode, and if EAX indicates a C-state
+ /// other than C0 or C1, the instruction operates as if EAX indicated the
+ /// C-state C1.
+ ///
+ UINT32 UserModeMonitorAndMwait:1;
+ UINT32 Reserved2:30;
+ UINT32 Reserved3:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER;
+
/**
THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability
Enhancement. Accessible only while in SMM.
@@ -748,6 +879,63 @@ typedef union {
#define MSR_XEON_PHI_LBR_SELECT 0x000001C8
+/**
+ MSR information returned for MSR index #MSR_XEON_PHI_LBR_SELECT
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 0] CPL_EQ_0.
+ ///
+ UINT32 CPL_EQ_0:1;
+ ///
+ /// [Bit 1] CPL_NEQ_0.
+ ///
+ UINT32 CPL_NEQ_0:1;
+ ///
+ /// [Bit 2] JCC.
+ ///
+ UINT32 JCC:1;
+ ///
+ /// [Bit 3] NEAR_REL_CALL.
+ ///
+ UINT32 NEAR_REL_CALL:1;
+ ///
+ /// [Bit 4] NEAR_IND_CALL.
+ ///
+ UINT32 NEAR_IND_CALL:1;
+ ///
+ /// [Bit 5] NEAR_RET.
+ ///
+ UINT32 NEAR_RET:1;
+ ///
+ /// [Bit 6] NEAR_IND_JMP.
+ ///
+ UINT32 NEAR_IND_JMP:1;
+ ///
+ /// [Bit 7] NEAR_REL_JMP.
+ ///
+ UINT32 NEAR_REL_JMP:1;
+ ///
+ /// [Bit 8] FAR_BRANCH.
+ ///
+ UINT32 FAR_BRANCH:1;
+ UINT32 Reserved1:23;
+ UINT32 Reserved2:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_XEON_PHI_LBR_SELECT_REGISTER;
+
/**
Thread. Last Branch Record Stack TOS (R/W).
@@ -1212,7 +1400,62 @@ typedef union {
/**
- Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1
+ Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
+ fields represent the widest possible range of uncore frequencies. Writing to
+ these fields allows software to control the minimum and the maximum
+ frequency that hardware will select.
+
+ @param ECX MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT (0x00000620)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT);
+ AsmWriteMsr64 (MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
+ @endcode
+**/
+#define MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT 0x00000620
+
+/**
+ MSR information returned for MSR index #MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
+ /// LLC/Ring.
+ ///
+ UINT32 MAX_RATIO:7;
+ UINT32 Reserved1:1;
+ ///
+ /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
+ /// possible ratio of the LLC/Ring.
+ ///
+ UINT32 MIN_RATIO:7;
+ UINT32 Reserved2:17;
+ UINT32 Reserved3:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER;
+
+
+/**
+ Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1
RAPL Domains.".
@param ECX MSR_XEON_PHI_PP0_POWER_LIMIT (0x00000638)
--
2.15.0.windows.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Patch v3 06/14] UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h: Add new MSRs.
2018-09-25 2:08 [Patch v3 00/14] Update MSR definitions Eric Dong
` (4 preceding siblings ...)
2018-09-25 2:08 ` [Patch v3 05/14] UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h: " Eric Dong
@ 2018-09-25 2:08 ` Eric Dong
2018-09-25 2:08 ` [Patch v3 07/14] UefiCpuPkg/Include/Register/ArchitecturalMsr.h: Add new MSR Eric Dong
` (9 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Eric Dong @ 2018-09-25 2:08 UTC (permalink / raw)
To: edk2-devel; +Cc: Michael D Kinney, Ruiyu Ni, Laszlo Ersek
Changes includes:
1. Add new MSR definitions.
2. Add support platform info.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong <eric.dong@intel.com>
---
UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h | 1548 +++++++++++++++++++++++++-
1 file changed, 1547 insertions(+), 1 deletion(-)
diff --git a/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h b/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
index 866fe30f05..90cde86ccb 100644
--- a/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
@@ -39,7 +39,11 @@
(DisplayFamily == 0x06 && \
( \
DisplayModel == 0x4E || \
- DisplayModel == 0x5E \
+ DisplayModel == 0x5E || \
+ DisplayModel == 0x55 || \
+ DisplayModel == 0x8E || \
+ DisplayModel == 0x9E || \
+ DisplayModel == 0x66 \
) \
)
@@ -124,6 +128,74 @@ typedef union {
#define MSR_SKYLAKE_LASTBRANCH_TOS 0x000001C9
+/**
+ Core. Power Control Register See http://biosbits.org.
+
+ @param ECX MSR_SKYLAKE_POWER_CTL (0x000001FC)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_POWER_CTL_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_POWER_CTL_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_SKYLAKE_POWER_CTL_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_POWER_CTL);
+ AsmWriteMsr64 (MSR_SKYLAKE_POWER_CTL, Msr.Uint64);
+ @endcode
+**/
+#define MSR_SKYLAKE_POWER_CTL 0x000001FC
+
+/**
+ MSR information returned for MSR index #MSR_SKYLAKE_POWER_CTL
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ UINT32 Reserved1:1;
+ ///
+ /// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the CPU
+ /// to switch to the Minimum Enhanced Intel SpeedStep Technology operating
+ /// point when all execution cores enter MWAIT (C1).
+ ///
+ UINT32 C1EEnable:1;
+ UINT32 Reserved2:17;
+ ///
+ /// [Bit 19] Disable Race to Halt Optimization (R/W) Setting this bit
+ /// disables the Race to Halt optimization and avoids this optimization
+ /// limitation to execute below the most efficient frequency ratio.
+ /// Default value is 0 for processors that support Race to Halt
+ /// optimization. Default value is 1 for processors that do not support
+ /// Race to Halt optimization.
+ ///
+ UINT32 Fix_Me_1:1;
+ ///
+ /// [Bit 20] Disable Energy Efficiency Optimization (R/W) Setting this bit
+ /// disables the P-States energy efficiency optimization. Default value is
+ /// 0. Disable/enable the energy efficiency optimization in P-State legacy
+ /// mode (when IA32_PM_ENABLE[HWP_ENABLE] = 0), has an effect only in the
+ /// turbo range or into PERF_MIN_CTL value if it is not zero set. In HWP
+ /// mode (IA32_PM_ENABLE[HWP_ENABLE] == 1), has an effect between the OS
+ /// desired or OS maximize to the OS minimize performance setting.
+ ///
+ UINT32 DisableEnergyEfficiencyOptimization:1;
+ UINT32 Reserved3:11;
+ UINT32 Reserved4:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_SKYLAKE_POWER_CTL_REGISTER;
+
+
/**
Package. Lower 64 Bit OwnerEpoch Component of SGX Key (RO). Low 64 bits of
an 128-bit external entropy value for key derivation of an enclave.
@@ -2254,4 +2326,1478 @@ typedef union {
UINT64 Uint64;
} MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER;
+
+/**
+ Package. NPK Address Used by AET Messages (R/W).
+
+ @param ECX MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE (0x00000080)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE);
+ AsmWriteMsr64 (MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE, Msr.Uint64);
+ @endcode
+**/
+#define MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE 0x00000080
+
+/**
+ MSR information returned for MSR index
+ #MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 0] Lock Bit If set, this MSR cannot be re-written anymore. Lock
+ /// bit has to be set in order for the AET packets to be directed to NPK
+ /// MMIO.
+ ///
+ UINT32 Fix_Me_1:1;
+ UINT32 Reserved:17;
+ ///
+ /// [Bits 31:18] ACPIBAR_BASE_ADDRESS AET target address in NPK MMIO space.
+ ///
+ UINT32 ACPIBAR_BASE_ADDRESS:14;
+ ///
+ /// [Bits 63:32] ACPIBAR_BASE_ADDRESS AET target address in NPK MMIO space.
+ ///
+ UINT32 Fix_Me_2:32;
+ } Bits;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER;
+
+
+/**
+ Core. Processor Reserved Memory Range Register - Physical Base Control
+ Register (R/W).
+
+ @param ECX MSR_SKYLAKE_PRMRR_PHYS_BASE (0x000001F4)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PRMRR_PHYS_BASE);
+ AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_PHYS_BASE, Msr.Uint64);
+ @endcode
+**/
+#define MSR_SKYLAKE_PRMRR_PHYS_BASE 0x000001F4
+
+/**
+ MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_PHYS_BASE
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 2:0] MemType PRMRR BASE MemType.
+ ///
+ UINT32 MemTypePRMRRBASEMemType:3;
+ UINT32 Reserved1:9;
+ ///
+ /// [Bits 31:12] Base PRMRR Base Address.
+ ///
+ UINT32 BasePRMRRBaseAddress:20;
+ ///
+ /// [Bits 45:32] Base PRMRR Base Address.
+ ///
+ UINT32 Fix_Me_1:14;
+ UINT32 Reserved2:18;
+ } Bits;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER;
+
+
+/**
+ Core. Processor Reserved Memory Range Register - Physical Mask Control
+ Register (R/W).
+
+ @param ECX MSR_SKYLAKE_PRMRR_PHYS_MASK (0x000001F5)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PRMRR_PHYS_MASK);
+ AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_PHYS_MASK, Msr.Uint64);
+ @endcode
+**/
+#define MSR_SKYLAKE_PRMRR_PHYS_MASK 0x000001F5
+
+/**
+ MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_PHYS_MASK
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ UINT32 Reserved1:10;
+ ///
+ /// [Bit 10] Lock Lock bit for the PRMRR.
+ ///
+ UINT32 Fix_Me_1:1;
+ ///
+ /// [Bit 11] VLD Enable bit for the PRMRR.
+ ///
+ UINT32 VLD:1;
+ ///
+ /// [Bits 31:12] Mask PRMRR MASK bits.
+ ///
+ UINT32 Fix_Me_2:20;
+ ///
+ /// [Bits 45:32] Mask PRMRR MASK bits.
+ ///
+ UINT32 Fix_Me_3:14;
+ UINT32 Reserved2:18;
+ } Bits;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER;
+
+
+/**
+ Core. Valid PRMRR Configurations (R/W).
+
+ @param ECX MSR_SKYLAKE_PRMRR_VALID_CONFIG (0x000001FB)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PRMRR_VALID_CONFIG);
+ AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_VALID_CONFIG, Msr.Uint64);
+ @endcode
+**/
+#define MSR_SKYLAKE_PRMRR_VALID_CONFIG 0x000001FB
+
+/**
+ MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_VALID_CONFIG
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 0] 1M supported MEE size.
+ ///
+ UINT32 Fix_Me_1:1;
+ UINT32 Reserved1:4;
+ ///
+ /// [Bit 5] 32M supported MEE size.
+ ///
+ UINT32 Fix_Me_2:1;
+ ///
+ /// [Bit 6] 64M supported MEE size.
+ ///
+ UINT32 Fix_Me_3:1;
+ ///
+ /// [Bit 7] 128M supported MEE size.
+ ///
+ UINT32 Fix_Me_4:1;
+ UINT32 Reserved2:24;
+ UINT32 Reserved3:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER;
+
+
+/**
+ Package. (R/W) The PRMRR range is used to protect Xucode memory from
+ unauthorized reads and writes. Any IO access to this range is aborted. This
+ register controls the location of the PRMRR range by indicating its starting
+ address. It functions in tandem with the PRMRR mask register.
+
+ @param ECX MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE (0x000002F4)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE);
+ AsmWriteMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE, Msr.Uint64);
+ @endcode
+**/
+#define MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE 0x000002F4
+
+/**
+ MSR information returned for MSR index #MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ UINT32 Reserved1:12;
+ ///
+ /// [Bits 31:12] Range Base This field corresponds to bits 38:12 of the
+ /// base address memory range which is allocated to PRMRR memory.
+ ///
+ UINT32 Fix_Me_1:20;
+ ///
+ /// [Bits 38:32] Range Base This field corresponds to bits 38:12 of the
+ /// base address memory range which is allocated to PRMRR memory.
+ ///
+ UINT32 Fix_Me_2:7;
+ UINT32 Reserved2:25;
+ } Bits;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER;
+
+
+/**
+ Package. (R/W) This register controls the size of the PRMRR range by
+ indicating which address bits must match the PRMRR base register value.
+
+ @param ECX MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK (0x000002F5)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK);
+ AsmWriteMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK, Msr.Uint64);
+ @endcode
+**/
+#define MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK 0x000002F5
+
+/**
+ MSR information returned for MSR index #MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ UINT32 Reserved1:10;
+ ///
+ /// [Bit 10] Lock Setting this bit locks all writeable settings in this
+ /// register, including itself.
+ ///
+ UINT32 Fix_Me_1:1;
+ ///
+ /// [Bit 11] Range_En Indicates whether the PRMRR range is enabled and
+ /// valid.
+ ///
+ UINT32 Fix_Me_2:1;
+ UINT32 Reserved2:20;
+ UINT32 Reserved3:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER;
+
+/**
+ Package. Ring Ratio Limit (R/W) This register provides Min/Max Ratio Limits
+ for the LLC and Ring.
+
+ @param ECX MSR_SKYLAKE_RING_RATIO_LIMIT (0x00000620)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RING_RATIO_LIMIT);
+ AsmWriteMsr64 (MSR_SKYLAKE_RING_RATIO_LIMIT, Msr.Uint64);
+ @endcode
+**/
+#define MSR_SKYLAKE_RING_RATIO_LIMIT 0x00000620
+
+/**
+ MSR information returned for MSR index #MSR_SKYLAKE_RING_RATIO_LIMIT
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 6:0] MAX_Ratio This field is used to limit the max ratio of the
+ /// LLC/Ring.
+ ///
+ UINT32 Fix_Me_1:7;
+ UINT32 Reserved1:1;
+ ///
+ /// [Bits 14:8] MIN_Ratio Writing to this field controls the minimum
+ /// possible ratio of the LLC/Ring.
+ ///
+ UINT32 Fix_Me_2:7;
+ UINT32 Reserved2:17;
+ UINT32 Reserved3:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER;
+
+
+/**
+ Branch Monitoring Global Control (R/W).
+
+ @param ECX MSR_SKYLAKE_BR_DETECT_CTRL (0x00000350)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_BR_DETECT_CTRL);
+ AsmWriteMsr64 (MSR_SKYLAKE_BR_DETECT_CTRL, Msr.Uint64);
+ @endcode
+**/
+#define MSR_SKYLAKE_BR_DETECT_CTRL 0x00000350
+
+/**
+ MSR information returned for MSR index #MSR_SKYLAKE_BR_DETECT_CTRL
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 0] EnMonitoring Global enable for branch monitoring.
+ ///
+ UINT32 Fix_Me_1:1;
+ ///
+ /// [Bit 1] EnExcept Enable branch monitoring event signaling on threshold
+ /// trip. The branch monitoring event handler is signaled via the existing
+ /// PMI signaling mechanism as programmed from the corresponding local
+ /// APIC LVT entry.
+ ///
+ UINT32 Fix_Me_2:1;
+ ///
+ /// [Bit 2] EnLBRFrz Enable LBR freeze on threshold trip. This will cause
+ /// the LBR frozen bit 58 to be set in IA32_PERF_GLOBAL_STATUS when a
+ /// triggering condition occurs and this bit is enabled.
+ ///
+ UINT32 Fix_Me_3:1;
+ ///
+ /// [Bit 3] DisableInGuest When set to '1', branch monitoring, event
+ /// triggering and LBR freeze actions are disabled when operating at VMX
+ /// non-root operation.
+ ///
+ UINT32 Fix_Me_4:1;
+ UINT32 Reserved1:4;
+ ///
+ /// [Bits 17:8] WindowSize Window size defined by WindowCntSel. Values 0 -
+ /// 1023 are supported. Once the Window counter reaches the WindowSize
+ /// count both the Window Counter and all Branch Monitoring Counters are
+ /// cleared.
+ ///
+ UINT32 Fix_Me_5:10;
+ UINT32 Reserved2:6;
+ ///
+ /// [Bits 25:24] WindowCntSel Window event count select: '00 =
+ /// Instructions retired. '01 = Branch instructions retired '10 = Return
+ /// instructions retired. '11 = Indirect branch instructions retired.
+ ///
+ UINT32 Fix_Me_6:2;
+ ///
+ /// [Bit 26] CntAndMode When set to '1', the overall branch monitoring
+ /// event triggering condition is true only if all enabled counters'
+ /// threshold conditions are true. When '0', the threshold tripping
+ /// condition is true if any enabled counters' threshold is true.
+ ///
+ UINT32 Fix_Me_7:1;
+ UINT32 Reserved3:5;
+ UINT32 Reserved4:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER;
+
+
+/**
+ Branch Monitoring Global Status (R/W).
+
+ @param ECX MSR_SKYLAKE_BR_DETECT_STATUS (0x00000351)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_BR_DETECT_STATUS);
+ AsmWriteMsr64 (MSR_SKYLAKE_BR_DETECT_STATUS, Msr.Uint64);
+ @endcode
+**/
+#define MSR_SKYLAKE_BR_DETECT_STATUS 0x00000351
+
+/**
+ MSR information returned for MSR index #MSR_SKYLAKE_BR_DETECT_STATUS
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 0] Branch Monitoring Event Signaled When set to '1', Branch
+ /// Monitoring event signaling is blocked until this bit is cleared by
+ /// software.
+ ///
+ UINT32 BranchMonitoringEventSignaled:1;
+ ///
+ /// [Bit 1] LBRsValid This status bit is set to '1' if the LBR state is
+ /// considered valid for sampling by branch monitoring software.
+ ///
+ UINT32 LBRsValid:1;
+ UINT32 Reserved1:6;
+ ///
+ /// [Bit 8] CntrHit0 Branch monitoring counter #0 threshold hit. This
+ /// status bit is sticky and once set requires clearing by software.
+ /// Counter operation continues independent of the state of the bit.
+ ///
+ UINT32 CntrHit0:1;
+ ///
+ /// [Bit 9] CntrHit1 Branch monitoring counter #1 threshold hit. This
+ /// status bit is sticky and once set requires clearing by software.
+ /// Counter operation continues independent of the state of the bit.
+ ///
+ UINT32 CntrHit1:1;
+ UINT32 Reserved2:6;
+ ///
+ /// [Bits 25:16] CountWindow The current value of the window counter. The
+ /// count value is frozen on a valid branch monitoring triggering
+ /// condition. This is a 10-bit unsigned value.
+ ///
+ UINT32 CountWindow:10;
+ UINT32 Reserved3:6;
+ ///
+ /// [Bits 39:32] Count0 The current value of counter 0 updated after each
+ /// occurrence of the event being counted. The count value is frozen on a
+ /// valid branch monitoring triggering condition (in which case CntrHit0
+ /// will also be set). This is an 8-bit signed value (2's complement).
+ /// Heuristic events which only increment will saturate and freeze at
+ /// maximum value 0xFF (256). RET-CALL event counter saturate at maximum
+ /// value 0x7F (+127) and minimum value 0x80 (-128).
+ ///
+ UINT32 Count0:8;
+ ///
+ /// [Bits 47:40] Count1 The current value of counter 1 updated after each
+ /// occurrence of the event being counted. The count value is frozen on a
+ /// valid branch monitoring triggering condition (in which case CntrHit1
+ /// will also be set). This is an 8-bit signed value (2's complement).
+ /// Heuristic events which only increment will saturate and freeze at
+ /// maximum value 0xFF (256). RET-CALL event counter saturate at maximum
+ /// value 0x7F (+127) and minimum value 0x80 (-128).
+ ///
+ UINT32 Count1:8;
+ UINT32 Reserved4:16;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER;
+
+
+/**
+ Package. Package C3 Residency Counter (R/O). Note: C-state values are
+ processor specific C-state code names, unrelated to MWAIT extension C-state
+ parameters or ACPI C-states.
+
+ @param ECX MSR_SKYLAKE_PKG_C3_RESIDENCY (0x000003F8)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_C3_RESIDENCY);
+ @endcode
+**/
+#define MSR_SKYLAKE_PKG_C3_RESIDENCY 0x000003F8
+
+
+/**
+ Core. Core C1 Residency Counter (R/O). Value since last reset for the Core
+ C1 residency. Counter rate is the Max Non-Turbo frequency (same as TSC).
+ This counter counts in case both of the core's threads are in an idle state
+ and at least one of the core's thread residency is in a C1 state or in one
+ of its sub states. The counter is updated only after a core C state exit.
+ Note: Always reads 0 if core C1 is unsupported. A value of zero indicates
+ that this processor does not support core C1 or never entered core C1 level
+ state.
+
+ @param ECX MSR_SKYLAKE_CORE_C1_RESIDENCY (0x00000660)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_C1_RESIDENCY);
+ @endcode
+**/
+#define MSR_SKYLAKE_CORE_C1_RESIDENCY 0x00000660
+
+
+/**
+ Core. Core C3 Residency Counter (R/O). Will always return 0.
+
+ @param ECX MSR_SKYLAKE_CORE_C3_RESIDENCY (0x00000662)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_C3_RESIDENCY);
+ @endcode
+**/
+#define MSR_SKYLAKE_CORE_C3_RESIDENCY 0x00000662
+
+
+/**
+ Package. Protected Processor Inventory Number Enable Control (R/W).
+
+ @param ECX MSR_SKYLAKE_PPIN_CTL (0x0000004E)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_PPIN_CTL_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_PPIN_CTL_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_SKYLAKE_PPIN_CTL_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PPIN_CTL);
+ AsmWriteMsr64 (MSR_SKYLAKE_PPIN_CTL, Msr.Uint64);
+ @endcode
+**/
+#define MSR_SKYLAKE_PPIN_CTL 0x0000004E
+
+/**
+ MSR information returned for MSR index #MSR_SKYLAKE_PPIN_CTL
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 0] LockOut (R/WO) See Table 2-25.
+ ///
+ UINT32 LockOut:1;
+ ///
+ /// [Bit 1] Enable_PPIN (R/W) See Table 2-25.
+ ///
+ UINT32 Enable_PPIN:1;
+ UINT32 Reserved1:30;
+ UINT32 Reserved2:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_SKYLAKE_PPIN_CTL_REGISTER;
+
+
+/**
+ Package. Protected Processor Inventory Number (R/O). Protected Processor
+ Inventory Number (R/O) See Table 2-25.
+
+ @param ECX MSR_SKYLAKE_PPIN (0x0000004F)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_PPIN);
+ @endcode
+**/
+#define MSR_SKYLAKE_PPIN 0x0000004F
+
+
+/**
+ Package. Platform Information Contains power management and other model
+ specific features enumeration. See http://biosbits.org.
+
+ @param ECX MSR_SKYLAKE_PLATFORM_INFO (0x000000CE)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_PLATFORM_INFO_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_PLATFORM_INFO_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_SKYLAKE_PLATFORM_INFO_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_INFO);
+ AsmWriteMsr64 (MSR_SKYLAKE_PLATFORM_INFO, Msr.Uint64);
+ @endcode
+**/
+#define MSR_SKYLAKE_PLATFORM_INFO 0x000000CE
+
+/**
+ MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_INFO
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ UINT32 Reserved1:8;
+ ///
+ /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 2-25.
+ ///
+ UINT32 MaximumNon_TurboRatio:8;
+ UINT32 Reserved2:7;
+ ///
+ /// [Bit 23] Package. PPIN_CAP (R/O) See Table 2-25.
+ ///
+ UINT32 PPIN_CAP:1;
+ UINT32 Reserved3:4;
+ ///
+ /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See
+ /// Table 2-25.
+ ///
+ UINT32 ProgrammableRatioLimit:1;
+ ///
+ /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See
+ /// Table 2-25.
+ ///
+ UINT32 ProgrammableTDPLimit:1;
+ ///
+ /// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 2-25.
+ ///
+ UINT32 ProgrammableTJOFFSET:1;
+ UINT32 Reserved4:1;
+ UINT32 Reserved5:8;
+ ///
+ /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 2-25.
+ ///
+ UINT32 MaximumEfficiencyRatio:8;
+ UINT32 Reserved6:16;
+ } Bits;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_SKYLAKE_PLATFORM_INFO_REGISTER;
+
+
+/**
+ Core. C-State Configuration Control (R/W) Note: C-state values are processor
+ specific C-state code names, unrelated to MWAIT extension C-state parameters
+ or ACPI C-states. `See http://biosbits.org. <http://biosbits.org/>`__.
+
+ @param ECX MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL (0x000000E2)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL);
+ AsmWriteMsr64 (MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
+ @endcode
+**/
+#define MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL 0x000000E2
+
+/**
+ MSR information returned for MSR index #MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest
+ /// processor-specific C-state code name (consuming the least power) for
+ /// the package. The default is set as factory-configured package Cstate
+ /// limit. The following C-state code name encodings are supported: 000b:
+ /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention)
+ /// 011b: C6 (retention) 111b: No Package C state limits. All C states
+ /// supported by the processor are available.
+ ///
+ UINT32 C_StateLimit:3;
+ UINT32 Reserved1:7;
+ ///
+ /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
+ ///
+ UINT32 MWAITRedirectionEnable:1;
+ UINT32 Reserved2:4;
+ ///
+ /// [Bit 15] CFG Lock (R/WO).
+ ///
+ UINT32 CFGLock:1;
+ ///
+ /// [Bit 16] Automatic C-State Conversion Enable (R/W) If 1, the processor
+ /// will convert HALT or MWAT(C1) to MWAIT(C6).
+ ///
+ UINT32 AutomaticC_StateConversionEnable:1;
+ UINT32 Reserved3:8;
+ ///
+ /// [Bit 25] C3 State Auto Demotion Enable (R/W).
+ ///
+ UINT32 C3StateAutoDemotionEnable:1;
+ ///
+ /// [Bit 26] C1 State Auto Demotion Enable (R/W).
+ ///
+ UINT32 C1StateAutoDemotionEnable:1;
+ ///
+ /// [Bit 27] Enable C3 Undemotion (R/W).
+ ///
+ UINT32 EnableC3Undemotion:1;
+ ///
+ /// [Bit 28] Enable C1 Undemotion (R/W).
+ ///
+ UINT32 EnableC1Undemotion:1;
+ ///
+ /// [Bit 29] Package C State Demotion Enable (R/W).
+ ///
+ UINT32 CStateDemotionEnable:1;
+ ///
+ /// [Bit 30] Package C State UnDemotion Enable (R/W).
+ ///
+ UINT32 CStateUnDemotionEnable:1;
+ UINT32 Reserved4:1;
+ UINT32 Reserved5:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER;
+
+
+/**
+ Thread. Global Machine Check Capability (R/O).
+
+ @param ECX MSR_SKYLAKE_IA32_MCG_CAP (0x00000179)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_IA32_MCG_CAP_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_IA32_MCG_CAP_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_SKYLAKE_IA32_MCG_CAP_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_MCG_CAP);
+ @endcode
+**/
+#define MSR_SKYLAKE_IA32_MCG_CAP 0x00000179
+
+/**
+ MSR information returned for MSR index #MSR_SKYLAKE_IA32_MCG_CAP
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 7:0] Count.
+ ///
+ UINT32 Count:8;
+ ///
+ /// [Bit 8] MCG_CTL_P.
+ ///
+ UINT32 MCG_CTL_P:1;
+ ///
+ /// [Bit 9] MCG_EXT_P.
+ ///
+ UINT32 MCG_EXT_P:1;
+ ///
+ /// [Bit 10] MCP_CMCI_P.
+ ///
+ UINT32 MCP_CMCI_P:1;
+ ///
+ /// [Bit 11] MCG_TES_P.
+ ///
+ UINT32 MCG_TES_P:1;
+ UINT32 Reserved1:4;
+ ///
+ /// [Bits 23:16] MCG_EXT_CNT.
+ ///
+ UINT32 MCG_EXT_CNT:8;
+ ///
+ /// [Bit 24] MCG_SER_P.
+ ///
+ UINT32 MCG_SER_P:1;
+ ///
+ /// [Bit 25] MCG_EM_P.
+ ///
+ UINT32 MCG_EM_P:1;
+ ///
+ /// [Bit 26] MCG_ELOG_P.
+ ///
+ UINT32 MCG_ELOG_P:1;
+ UINT32 Reserved2:5;
+ UINT32 Reserved3:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_SKYLAKE_IA32_MCG_CAP_REGISTER;
+
+
+/**
+ THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability
+ Enhancement. Accessible only while in SMM.
+
+ @param ECX MSR_SKYLAKE_SMM_MCA_CAP (0x0000017D)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_SMM_MCA_CAP_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_SMM_MCA_CAP_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_SKYLAKE_SMM_MCA_CAP_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_SMM_MCA_CAP);
+ AsmWriteMsr64 (MSR_SKYLAKE_SMM_MCA_CAP, Msr.Uint64);
+ @endcode
+**/
+#define MSR_SKYLAKE_SMM_MCA_CAP 0x0000017D
+
+/**
+ MSR information returned for MSR index #MSR_SKYLAKE_SMM_MCA_CAP
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ UINT32 Reserved1:32;
+ UINT32 Reserved2:26;
+ ///
+ /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
+ /// SMM code access restriction is supported and a host-space interface is
+ /// available to SMM handler.
+ ///
+ UINT32 SMM_Code_Access_Chk:1;
+ ///
+ /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
+ /// SMM long flow indicator is supported and a host-space interface is
+ /// available to SMM handler.
+ ///
+ UINT32 Long_Flow_Indication:1;
+ UINT32 Reserved3:4;
+ } Bits;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_SKYLAKE_SMM_MCA_CAP_REGISTER;
+
+
+/**
+ Package. Temperature Target.
+
+ @param ECX MSR_SKYLAKE_TEMPERATURE_TARGET (0x000001A2)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TEMPERATURE_TARGET);
+ AsmWriteMsr64 (MSR_SKYLAKE_TEMPERATURE_TARGET, Msr.Uint64);
+ @endcode
+**/
+#define MSR_SKYLAKE_TEMPERATURE_TARGET 0x000001A2
+
+/**
+ MSR information returned for MSR index #MSR_SKYLAKE_TEMPERATURE_TARGET
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ UINT32 Reserved1:16;
+ ///
+ /// [Bits 23:16] Temperature Target (RO) See Table 2-25.
+ ///
+ UINT32 TemperatureTarget:8;
+ ///
+ /// [Bits 27:24] TCC Activation Offset (R/W) See Table 2-25.
+ ///
+ UINT32 TCCActivationOffset:4;
+ UINT32 Reserved2:4;
+ UINT32 Reserved3:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER;
+
+/**
+ Package. This register defines the active core ranges for each frequency
+ point. NUMCORE[0:7] must be populated in ascending order. NUMCORE[i+1] must
+ be greater than NUMCORE[i]. Entries with NUMCORE[i] == 0 will be ignored.
+ The last valid entry must have NUMCORE >= the number of cores in the SKU. If
+ any of the rules above are broken, the configuration is silently rejected.
+
+ @param ECX MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES (0x000001AE)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES);
+ AsmWriteMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES, Msr.Uint64);
+ @endcode
+**/
+#define MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES 0x000001AE
+
+/**
+ MSR information returned for MSR index #MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 7:0] NUMCORE_0 Defines the active core ranges for each frequency
+ /// point.
+ ///
+ UINT32 NUMCORE_0:8;
+ ///
+ /// [Bits 15:8] NUMCORE_1 Defines the active core ranges for each
+ /// frequency point.
+ ///
+ UINT32 NUMCORE_1:8;
+ ///
+ /// [Bits 23:16] NUMCORE_2 Defines the active core ranges for each
+ /// frequency point.
+ ///
+ UINT32 NUMCORE_2:8;
+ ///
+ /// [Bits 31:24] NUMCORE_3 Defines the active core ranges for each
+ /// frequency point.
+ ///
+ UINT32 NUMCORE_3:8;
+ ///
+ /// [Bits 39:32] NUMCORE_4 Defines the active core ranges for each
+ /// frequency point.
+ ///
+ UINT32 NUMCORE_4:8;
+ ///
+ /// [Bits 47:40] NUMCORE_5 Defines the active core ranges for each
+ /// frequency point.
+ ///
+ UINT32 NUMCORE_5:8;
+ ///
+ /// [Bits 55:48] NUMCORE_6 Defines the active core ranges for each
+ /// frequency point.
+ ///
+ UINT32 NUMCORE_6:8;
+ ///
+ /// [Bits 63:56] NUMCORE_7 Defines the active core ranges for each
+ /// frequency point.
+ ///
+ UINT32 NUMCORE_7:8;
+ } Bits;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER;
+
+
+/**
+ Package. Unit Multipliers Used in RAPL Interfaces (R/O).
+
+ @param ECX MSR_SKYLAKE_RAPL_POWER_UNIT (0x00000606)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RAPL_POWER_UNIT);
+ @endcode
+**/
+#define MSR_SKYLAKE_RAPL_POWER_UNIT 0x00000606
+
+/**
+ MSR information returned for MSR index #MSR_SKYLAKE_RAPL_POWER_UNIT
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".
+ ///
+ UINT32 PowerUnits:4;
+ UINT32 Reserved1:4;
+ ///
+ /// [Bits 12:8] Package. Energy Status Units Energy related information
+ /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an
+ /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61
+ /// micro-joules).
+ ///
+ UINT32 EnergyStatusUnits:5;
+ UINT32 Reserved2:3;
+ ///
+ /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL
+ /// Interfaces.".
+ ///
+ UINT32 TimeUnits:4;
+ UINT32 Reserved3:12;
+ UINT32 Reserved4:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER;
+
+
+/**
+ Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL
+ Domain.".
+
+ @param ECX MSR_SKYLAKE_DRAM_POWER_LIMIT (0x00000618)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_POWER_LIMIT);
+ AsmWriteMsr64 (MSR_SKYLAKE_DRAM_POWER_LIMIT, Msr);
+ @endcode
+**/
+#define MSR_SKYLAKE_DRAM_POWER_LIMIT 0x00000618
+
+
+/**
+ Package. DRAM Energy Status (R/O) Energy consumed by DRAM devices.
+
+ @param ECX MSR_SKYLAKE_DRAM_ENERGY_STATUS (0x00000619)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_DRAM_ENERGY_STATUS);
+ @endcode
+**/
+#define MSR_SKYLAKE_DRAM_ENERGY_STATUS 0x00000619
+
+/**
+ MSR information returned for MSR index #MSR_SKYLAKE_DRAM_ENERGY_STATUS
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration
+ /// to enable DRAM RAPL mode 0 (Direct VR).
+ ///
+ UINT32 Energy:32;
+ UINT32 Reserved:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER;
+
+
+/**
+ Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
+ RAPL Domain.".
+
+ @param ECX MSR_SKYLAKE_DRAM_PERF_STATUS (0x0000061B)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_PERF_STATUS);
+ @endcode
+**/
+#define MSR_SKYLAKE_DRAM_PERF_STATUS 0x0000061B
+
+
+/**
+ Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
+
+ @param ECX MSR_SKYLAKE_DRAM_POWER_INFO (0x0000061C)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_POWER_INFO);
+ AsmWriteMsr64 (MSR_SKYLAKE_DRAM_POWER_INFO, Msr);
+ @endcode
+**/
+#define MSR_SKYLAKE_DRAM_POWER_INFO 0x0000061C
+
+
+/**
+ Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
+ fields represent the widest possible range of uncore frequencies. Writing to
+ these fields allows software to control the minimum and the maximum
+ frequency that hardware will select.
+
+ @param ECX MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT (0x00000620)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT);
+ AsmWriteMsr64 (MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
+ @endcode
+**/
+#define MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT 0x00000620
+
+/**
+ MSR information returned for MSR index #MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
+ /// LLC/Ring.
+ ///
+ UINT32 MAX_RATIO:7;
+ UINT32 Reserved1:1;
+ ///
+ /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
+ /// possible ratio of the LLC/Ring.
+ ///
+ UINT32 MIN_RATIO:7;
+ UINT32 Reserved2:17;
+ UINT32 Reserved3:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER;
+
+
+/**
+ Package. Reserved (R/O) Reads return 0.
+
+ @param ECX MSR_SKYLAKE_PP0_ENERGY_STATUS (0x00000639)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_PP0_ENERGY_STATUS);
+ @endcode
+**/
+#define MSR_SKYLAKE_PP0_ENERGY_STATUS 0x00000639
+
+
+/**
+ THREAD. Monitoring Event Select Register (R/W) If CPUID.(EAX=07H,
+ ECX=0):EBX.RDT-M[bit 12] = 1.
+
+ @param ECX MSR_SKYLAKE_IA32_QM_EVTSEL (0x00000C8D)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_QM_EVTSEL);
+ AsmWriteMsr64 (MSR_SKYLAKE_IA32_QM_EVTSEL, Msr.Uint64);
+ @endcode
+**/
+#define MSR_SKYLAKE_IA32_QM_EVTSEL 0x00000C8D
+
+/**
+ MSR information returned for MSR index #MSR_SKYLAKE_IA32_QM_EVTSEL
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 7:0] EventID (RW) Event encoding: 0x00: No monitoring. 0x01: L3
+ /// occupancy monitoring. 0x02: Total memory bandwidth monitoring. 0x03:
+ /// Local memory bandwidth monitoring. All other encoding reserved.
+ ///
+ UINT32 EventID:8;
+ UINT32 Reserved1:24;
+ ///
+ /// [Bits 41:32] RMID (RW).
+ ///
+ UINT32 RMID:10;
+ UINT32 Reserved2:22;
+ } Bits;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER;
+
+
+/**
+ THREAD. Resource Association Register (R/W).
+
+ @param ECX MSR_SKYLAKE_IA32_PQR_ASSOC (0x00000C8F)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PQR_ASSOC);
+ AsmWriteMsr64 (MSR_SKYLAKE_IA32_PQR_ASSOC, Msr.Uint64);
+ @endcode
+**/
+#define MSR_SKYLAKE_IA32_PQR_ASSOC 0x00000C8F
+
+/**
+ MSR information returned for MSR index #MSR_SKYLAKE_IA32_PQR_ASSOC
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 9:0] RMID.
+ ///
+ UINT32 RMID:10;
+ UINT32 Reserved1:22;
+ ///
+ /// [Bits 51:32] COS (R/W).
+ ///
+ UINT32 COS:20;
+ UINT32 Reserved2:12;
+ } Bits;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER;
+
+
+/**
+ Package. L3 Class Of Service Mask - COS N (R/W) If CPUID.(EAX=10H,
+ ECX=1):EDX.COS_MAX[15:0] >=0.
+
+ @param ECX MSR_SKYLAKE_IA32_L3_QOS_MASK_N
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_L3_QOS_MASK_N);
+ AsmWriteMsr64 (MSR_SKYLAKE_IA32_L3_QOS_MASK_N, Msr.Uint64);
+ @endcode
+**/
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_0 0x00000C90
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_1 0x00000C91
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_2 0x00000C92
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_3 0x00000C93
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_4 0x00000C94
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_5 0x00000C95
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_6 0x00000C96
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_7 0x00000C97
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_8 0x00000C98
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_9 0x00000C99
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_10 0x00000C9A
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_11 0x00000C9B
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_12 0x00000C9C
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_13 0x00000C9D
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_14 0x00000C9E
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_15 0x00000C9F
+
+/**
+ MSR information returned for MSR index #MSR_SKYLAKE_IA32_L3_QOS_MASK_N
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 19:0] CBM: Bit vector of available L3 ways for COS N enforcement.
+ ///
+ UINT32 CBM:20;
+ UINT32 Reserved2:12;
+ UINT32 Reserved3:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER;
+
+
#endif
--
2.15.0.windows.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Patch v3 07/14] UefiCpuPkg/Include/Register/ArchitecturalMsr.h: Add new MSR.
2018-09-25 2:08 [Patch v3 00/14] Update MSR definitions Eric Dong
` (5 preceding siblings ...)
2018-09-25 2:08 ` [Patch v3 06/14] UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h: Add new MSRs Eric Dong
@ 2018-09-25 2:08 ` Eric Dong
2018-09-25 2:08 ` [Patch v3 08/14] UefiCpuPkg/Include/Register/ArchitecturalMsr.h: Change structure definition Eric Dong
` (8 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Eric Dong @ 2018-09-25 2:08 UTC (permalink / raw)
To: edk2-devel; +Cc: Michael D Kinney, Ruiyu Ni, Laszlo Ersek
Changes includes:
1. Add new MSRs: MSR_IA32_L2_QOS_CFG/MSR_IA32_CSTAR.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong <eric.dong@intel.com>
---
UefiCpuPkg/Include/Register/ArchitecturalMsr.h | 64 ++++++++++++++++++++++++++
1 file changed, 64 insertions(+)
diff --git a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
index 5d2242aa80..b467ffaf26 100644
--- a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
+++ b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
@@ -5908,6 +5908,51 @@ typedef union {
UINT64 Uint64;
} MSR_IA32_L3_QOS_CFG_REGISTER;
+/**
+ L2 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=2):ECX.[2] = 1 ).
+
+ @param ECX MSR_IA32_L2_QOS_CFG (0x00000C82)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_IA32_L2_QOS_CFG_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_IA32_L2_QOS_CFG_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_IA32_L2_QOS_CFG_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L2_QOS_CFG);
+ AsmWriteMsr64 (MSR_IA32_L2_QOS_CFG, Msr.Uint64);
+ @endcode
+ @note MSR_IA32_L2_QOS_CFG is defined as IA32_L2_QOS_CFG in SDM.
+**/
+#define MSR_IA32_L2_QOS_CFG 0x00000C82
+
+/**
+ MSR information returned for MSR index #MSR_IA32_L2_QOS_CFG
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 0] Enable (R/W) Set 1 to enable L2 CAT masks and COS to operate
+ /// in Code and Data Prioritization (CDP) mode.
+ ///
+ UINT32 Enable:1;
+ UINT32 Reserved1:31;
+ UINT32 Reserved2:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_IA32_L2_QOS_CFG_REGISTER;
/**
Monitoring Event Select Register (R/W). If ( CPUID.(EAX=07H, ECX=0):EBX.[12]
@@ -6380,6 +6425,25 @@ typedef union {
**/
#define MSR_IA32_LSTAR 0xC0000082
+/**
+ IA-32e Mode System Call Target Address (R/W) Not used, as the SYSCALL
+ instruction is not recognized in compatibility mode. If
+ CPUID.80000001:EDX.[29] = 1.
+
+ @param ECX MSR_IA32_CSTAR (0xC0000083)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_IA32_CSTAR);
+ AsmWriteMsr64 (MSR_IA32_CSTAR, Msr);
+ @endcode
+ @note MSR_IA32_CSTAR is defined as IA32_CSTAR in SDM.
+**/
+#define MSR_IA32_CSTAR 0xC0000083
/**
System Call Flag Mask (R/W). If CPUID.80000001:EDX.[29] = 1.
--
2.15.0.windows.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Patch v3 08/14] UefiCpuPkg/Include/Register/ArchitecturalMsr.h: Change structure definition.
2018-09-25 2:08 [Patch v3 00/14] Update MSR definitions Eric Dong
` (6 preceding siblings ...)
2018-09-25 2:08 ` [Patch v3 07/14] UefiCpuPkg/Include/Register/ArchitecturalMsr.h: Add new MSR Eric Dong
@ 2018-09-25 2:08 ` Eric Dong
2018-09-25 2:08 ` [Patch v3 09/14] UefiCpuPkg/Include/Register/Msr/Core2Msr.h: Remove old MSR Eric Dong
` (7 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Eric Dong @ 2018-09-25 2:08 UTC (permalink / raw)
To: edk2-devel; +Cc: Michael D Kinney, Ruiyu Ni, Laszlo Ersek
V3 changes include:
1. Keep ReservedX not change if bit info not changed for this field.
V2 changes include:
1. Use X in ReservedX fields from totally new value if MSR structure definition changed.
For example, if in current structure, the max reserved variable is Reserved2, in new
definition, reserved variable is begin with Reserved3.
V1 Changes includes:
1. Change fields which is reserved in old version: MSR_IA32_RTIT_CTL_REGISTER
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong <eric.dong@intel.com>
---
UefiCpuPkg/Include/Register/ArchitecturalMsr.h | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
index b467ffaf26..22d64e995b 100644
--- a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
+++ b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
@@ -4647,7 +4647,14 @@ typedef union {
/// [Bit 3] User.
///
UINT32 User:1;
- UINT32 Reserved1:2;
+ ///
+ /// [Bit 4] PwrEvtEn.
+ ///
+ UINT32 PwrEvtEn:1;
+ ///
+ /// [Bit 5] FUPonPTW.
+ ///
+ UINT32 FUPonPTW:1;
///
/// [Bit 6] FabricEn. If (CPUID.(EAX=07H, ECX=0):ECX[3] = 1).
///
@@ -4672,7 +4679,10 @@ typedef union {
/// [Bit 11] DisRETC.
///
UINT32 DisRETC:1;
- UINT32 Reserved2:1;
+ ///
+ /// [Bit 12] PTWEn.
+ ///
+ UINT32 PTWEn:1;
///
/// [Bit 13] BranchEn.
///
--
2.15.0.windows.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Patch v3 09/14] UefiCpuPkg/Include/Register/Msr/Core2Msr.h: Remove old MSR.
2018-09-25 2:08 [Patch v3 00/14] Update MSR definitions Eric Dong
` (7 preceding siblings ...)
2018-09-25 2:08 ` [Patch v3 08/14] UefiCpuPkg/Include/Register/ArchitecturalMsr.h: Change structure definition Eric Dong
@ 2018-09-25 2:08 ` Eric Dong
2018-09-25 2:08 ` [Patch v3 10/14] UefiCpuPkg/Include/Register/Msr/P6Msr.h: " Eric Dong
` (6 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Eric Dong @ 2018-09-25 2:08 UTC (permalink / raw)
To: edk2-devel; +Cc: Michael D Kinney, Ruiyu Ni, Laszlo Ersek
Changes includes:
1. Remove old MSR which not existed in 2018-05 version spec:
1. MSR_CORE2_BBL_CR_CTL3
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong <eric.dong@intel.com>
---
UefiCpuPkg/Include/Register/Msr/Core2Msr.h | 60 ------------------------------
1 file changed, 60 deletions(-)
diff --git a/UefiCpuPkg/Include/Register/Msr/Core2Msr.h b/UefiCpuPkg/Include/Register/Msr/Core2Msr.h
index 22317fa1de..f01f7c5c97 100644
--- a/UefiCpuPkg/Include/Register/Msr/Core2Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/Core2Msr.h
@@ -471,66 +471,6 @@ typedef union {
UINT64 Uint64;
} MSR_CORE2_FSB_FREQ_REGISTER;
-
-/**
- Shared.
-
- @param ECX MSR_CORE2_BBL_CR_CTL3 (0x0000011E)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_CORE2_BBL_CR_CTL3_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_CORE2_BBL_CR_CTL3_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_CORE2_BBL_CR_CTL3_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_BBL_CR_CTL3);
- AsmWriteMsr64 (MSR_CORE2_BBL_CR_CTL3, Msr.Uint64);
- @endcode
- @note MSR_CORE2_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
-**/
-#define MSR_CORE2_BBL_CR_CTL3 0x0000011E
-
-/**
- MSR information returned for MSR index #MSR_CORE2_BBL_CR_CTL3
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
- /// Indicates if the L2 is hardware-disabled.
- ///
- UINT32 L2HardwareEnabled:1;
- UINT32 Reserved1:7;
- ///
- /// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 =
- /// Disabled (default) Until this bit is set the processor will not
- /// respond to the WBINVD instruction or the assertion of the FLUSH# input.
- ///
- UINT32 L2Enabled:1;
- UINT32 Reserved2:14;
- ///
- /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.
- ///
- UINT32 L2NotPresent:1;
- UINT32 Reserved3:8;
- UINT32 Reserved4:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_CORE2_BBL_CR_CTL3_REGISTER;
-
-
/**
Shared.
--
2.15.0.windows.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Patch v3 10/14] UefiCpuPkg/Include/Register/Msr/P6Msr.h: Remove old MSR.
2018-09-25 2:08 [Patch v3 00/14] Update MSR definitions Eric Dong
` (8 preceding siblings ...)
2018-09-25 2:08 ` [Patch v3 09/14] UefiCpuPkg/Include/Register/Msr/Core2Msr.h: Remove old MSR Eric Dong
@ 2018-09-25 2:08 ` Eric Dong
2018-09-25 2:08 ` [Patch v3 11/14] UefiCpuPkg/Include/Register/Msr/CoreMsr.h: " Eric Dong
` (5 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Eric Dong @ 2018-09-25 2:08 UTC (permalink / raw)
To: edk2-devel; +Cc: Michael D Kinney, Ruiyu Ni, Laszlo Ersek
Changes includes:
1. Remove MSR which not existed in 2018-05 version spec: MSR_P6_ROB_CR_BKUPTMPDR6.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong <eric.dong@intel.com>
---
UefiCpuPkg/Include/Register/Msr/P6Msr.h | 48 ---------------------------------
1 file changed, 48 deletions(-)
diff --git a/UefiCpuPkg/Include/Register/Msr/P6Msr.h b/UefiCpuPkg/Include/Register/Msr/P6Msr.h
index d8af2db3da..9cef72b239 100644
--- a/UefiCpuPkg/Include/Register/Msr/P6Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/P6Msr.h
@@ -1153,54 +1153,6 @@ typedef union {
**/
#define MSR_P6_LASTINTTOIP 0x000001DE
-
-/**
-
-
- @param ECX MSR_P6_ROB_CR_BKUPTMPDR6 (0x000001E0)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_P6_ROB_CR_BKUPTMPDR6_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_P6_ROB_CR_BKUPTMPDR6_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_P6_ROB_CR_BKUPTMPDR6_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_P6_ROB_CR_BKUPTMPDR6);
- AsmWriteMsr64 (MSR_P6_ROB_CR_BKUPTMPDR6, Msr.Uint64);
- @endcode
- @note MSR_P6_ROB_CR_BKUPTMPDR6 is defined as ROB_CR_BKUPTMPDR6 in SDM.
-**/
-#define MSR_P6_ROB_CR_BKUPTMPDR6 0x000001E0
-
-/**
- MSR information returned for MSR index #MSR_P6_ROB_CR_BKUPTMPDR6
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:2;
- ///
- /// [Bit 2] Fast Strings Enable bit. Default is enabled.
- ///
- UINT32 FastStrings:1;
- UINT32 Reserved2:29;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_P6_ROB_CR_BKUPTMPDR6_REGISTER;
-
-
/**
--
2.15.0.windows.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Patch v3 11/14] UefiCpuPkg/Include/Register/Msr/CoreMsr.h: Remove old MSR.
2018-09-25 2:08 [Patch v3 00/14] Update MSR definitions Eric Dong
` (9 preceding siblings ...)
2018-09-25 2:08 ` [Patch v3 10/14] UefiCpuPkg/Include/Register/Msr/P6Msr.h: " Eric Dong
@ 2018-09-25 2:08 ` Eric Dong
2018-09-25 2:08 ` [Patch v3 12/14] UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h: Add new MSR name and keep old one Eric Dong
` (4 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Eric Dong @ 2018-09-25 2:08 UTC (permalink / raw)
To: edk2-devel; +Cc: Michael D Kinney, Ruiyu Ni, Laszlo Ersek
Changes includes:
1. Remove old MSR which not existed in 2018-05 version spec:
1. MSR_CORE_ROB_CR_BKUPTMPDR6
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong <eric.dong@intel.com>
---
UefiCpuPkg/Include/Register/Msr/CoreMsr.h | 48 -------------------------------
1 file changed, 48 deletions(-)
diff --git a/UefiCpuPkg/Include/Register/Msr/CoreMsr.h b/UefiCpuPkg/Include/Register/Msr/CoreMsr.h
index bb2bdd2ca1..a4315d6e56 100644
--- a/UefiCpuPkg/Include/Register/Msr/CoreMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/CoreMsr.h
@@ -555,54 +555,6 @@ typedef union {
**/
#define MSR_CORE_LER_TO_LIP 0x000001DE
-
-/**
- Unique.
-
- @param ECX MSR_CORE_ROB_CR_BKUPTMPDR6 (0x000001E0)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_CORE_ROB_CR_BKUPTMPDR6_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_CORE_ROB_CR_BKUPTMPDR6_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_CORE_ROB_CR_BKUPTMPDR6_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_CORE_ROB_CR_BKUPTMPDR6);
- AsmWriteMsr64 (MSR_CORE_ROB_CR_BKUPTMPDR6, Msr.Uint64);
- @endcode
- @note MSR_CORE_ROB_CR_BKUPTMPDR6 is defined as ROB_CR_BKUPTMPDR6 in SDM.
-**/
-#define MSR_CORE_ROB_CR_BKUPTMPDR6 0x000001E0
-
-/**
- MSR information returned for MSR index #MSR_CORE_ROB_CR_BKUPTMPDR6
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- UINT32 Reserved1:2;
- ///
- /// [Bit 2] Fast Strings Enable bit. (Default, enabled).
- ///
- UINT32 FastStrings:1;
- UINT32 Reserved2:29;
- UINT32 Reserved3:32;
- } Bits;
- ///
- /// All bit fields as a 32-bit value
- ///
- UINT32 Uint32;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_CORE_ROB_CR_BKUPTMPDR6_REGISTER;
-
-
/**
Unique.
--
2.15.0.windows.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Patch v3 12/14] UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h: Add new MSR name and keep old one.
2018-09-25 2:08 [Patch v3 00/14] Update MSR definitions Eric Dong
` (10 preceding siblings ...)
2018-09-25 2:08 ` [Patch v3 11/14] UefiCpuPkg/Include/Register/Msr/CoreMsr.h: " Eric Dong
@ 2018-09-25 2:08 ` Eric Dong
2018-09-25 2:08 ` [Patch v3 13/14] UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h: " Eric Dong
` (3 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Eric Dong @ 2018-09-25 2:08 UTC (permalink / raw)
To: edk2-devel; +Cc: Michael D Kinney, Ruiyu Ni, Laszlo Ersek
Changes includes:
1. Change MSR name:
1. MSR_SKYLAKE_SGXOWNER0 => MSR_SKYLAKE_SGXOWNEREPOCH0
2. MSR_SKYLAKE_SGXOWNER1 => MSR_SKYLAKE_SGXOWNEREPOCH1
2. Keep old MSR definition(MSR_SKYLAKE_SGXOWNER0/1) for compatibility
1. Use below coding style to define old MSR
#define MSR_SKYLAKE_SGXOWNER0 MSR_SKYLAKE_SGXOWNEREPOCH0
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong <eric.dong@intel.com>
---
UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h | 40 +++++++++++++++++++---------
1 file changed, 27 insertions(+), 13 deletions(-)
diff --git a/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h b/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
index 90cde86ccb..88f2c28eae 100644
--- a/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
@@ -197,10 +197,12 @@ typedef union {
/**
- Package. Lower 64 Bit OwnerEpoch Component of SGX Key (RO). Low 64 bits of
- an 128-bit external entropy value for key derivation of an enclave.
+ Package. Lower 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update
+ CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in
+ the package. Lower 64 bits of an 128-bit external entropy value for key
+ derivation of an enclave.
- @param ECX MSR_SKYLAKE_SGXOWNER0 (0x00000300)
+ @param ECX MSR_SKYLAKE_SGXOWNEREPOCH0 (0x00000300)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
@@ -208,18 +210,24 @@ typedef union {
@code
UINT64 Msr;
- Msr = AsmReadMsr64 (MSR_SKYLAKE_SGXOWNER0);
+ Msr = 0;
+ AsmWriteMsr64 (MSR_SKYLAKE_SGXOWNEREPOCH0, Msr);
@endcode
- @note MSR_SKYLAKE_SGXOWNER0 is defined as MSR_SGXOWNER0 in SDM.
+ @note MSR_SKYLAKE_SGXOWNEREPOCH0 is defined as MSR_SGXOWNER0 in SDM.
**/
-#define MSR_SKYLAKE_SGXOWNER0 0x00000300
-
+#define MSR_SKYLAKE_SGXOWNEREPOCH0 0x00000300
+//
+// Define MSR_SKYLAKE_SGXOWNER0 for compatibility due to name change in the SDM.
+//
+#define MSR_SKYLAKE_SGXOWNER0 MSR_SKYLAKE_SGXOWNEREPOCH0
/**
- Package. Upper 64 Bit OwnerEpoch Component of SGX Key (RO). Upper 64 bits of
- an 128-bit external entropy value for key derivation of an enclave.
+ Package. Upper 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update
+ CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in
+ the package. Upper 64 bits of an 128-bit external entropy value for key
+ derivation of an enclave.
- @param ECX MSR_SKYLAKE_SGXOWNER1 (0x00000301)
+ @param ECX MSR_SKYLAKE_SGXOWNEREPOCH1 (0x00000301)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
@@ -227,11 +235,17 @@ typedef union {
@code
UINT64 Msr;
- Msr = AsmReadMsr64 (MSR_SKYLAKE_SGXOWNER1);
+ Msr = 0;
+ AsmWriteMsr64 (MSR_SKYLAKE_SGXOWNEREPOCH1, Msr);
@endcode
- @note MSR_SKYLAKE_SGXOWNER1 is defined as MSR_SGXOWNER1 in SDM.
+ @note MSR_SKYLAKE_SGXOWNEREPOCH1 is defined as MSR_SGXOWNER1 in SDM.
**/
-#define MSR_SKYLAKE_SGXOWNER1 0x00000301
+#define MSR_SKYLAKE_SGXOWNEREPOCH1 0x00000301
+
+//
+// Define MSR_SKYLAKE_SGXOWNER1 for compatibility due to name change in the SDM.
+//
+#define MSR_SKYLAKE_SGXOWNER1 MSR_SKYLAKE_SGXOWNEREPOCH1
/**
--
2.15.0.windows.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Patch v3 13/14] UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h: Add new MSR name and keep old one.
2018-09-25 2:08 [Patch v3 00/14] Update MSR definitions Eric Dong
` (11 preceding siblings ...)
2018-09-25 2:08 ` [Patch v3 12/14] UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h: Add new MSR name and keep old one Eric Dong
@ 2018-09-25 2:08 ` Eric Dong
2018-09-25 2:08 ` [Patch v3 14/14] UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h: Change structure definition Eric Dong
` (2 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Eric Dong @ 2018-09-25 2:08 UTC (permalink / raw)
To: edk2-devel; +Cc: Michael D Kinney, Ruiyu Ni, Laszlo Ersek
Changes includes:
1. Change MSR name:
1. MSR_GOLDMONT_SGXOWNER0 => MSR_GOLDMONT_SGXOWNEREPOCH0
2. MSR_GOLDMONT_SGXOWNER1 => MSR_GOLDMONT_SGXOWNEREPOCH1
2. Keep old MSR definition (MSR_GOLDMONT_SGXOWNER0/1) for compatibility.
1. Define old MSR like below style:
#define MSR_GOLDMONT_SGXOWNER0 MSR_GOLDMONT_SGXOWNEREPOCH0
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong <eric.dong@intel.com>
---
UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h | 34 +++++++++++++++++++--------
1 file changed, 24 insertions(+), 10 deletions(-)
diff --git a/UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h b/UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
index a9061133c9..383f31ee55 100644
--- a/UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
@@ -843,10 +843,12 @@ typedef union {
/**
- Package. Lower 64 Bit OwnerEpoch Component of SGX Key (RO). Low 64 bits of
- an 128-bit external entropy value for key derivation of an enclave.
+ Package. Lower 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update
+ CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in
+ the package. Lower 64 bits of an 128-bit external entropy value for key
+ derivation of an enclave.
- @param ECX MSR_GOLDMONT_SGXOWNER0 (0x00000300)
+ @param ECX MSR_GOLDMONT_SGXOWNEREPOCH0 (0x00000300)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
@@ -854,18 +856,24 @@ typedef union {
@code
UINT64 Msr;
- Msr = AsmReadMsr64 (MSR_GOLDMONT_SGXOWNER0);
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_SGXOWNEREPOCH0);
@endcode
- @note MSR_GOLDMONT_SGXOWNER0 is defined as MSR_SGXOWNER0 in SDM.
+ @note MSR_GOLDMONT_SGXOWNEREPOCH0 is defined as MSR_SGXOWNEREPOCH0 in SDM.
**/
-#define MSR_GOLDMONT_SGXOWNER0 0x00000300
+#define MSR_GOLDMONT_SGXOWNEREPOCH0 0x00000300
+
+
+//
+// Define MSR_GOLDMONT_SGXOWNER0 for compatibility due to name change in the SDM.
+//
+#define MSR_GOLDMONT_SGXOWNER0 MSR_GOLDMONT_SGXOWNEREPOCH0
/**
Package. Upper 64 Bit OwnerEpoch Component of SGX Key (RO). Upper 64 bits of
an 128-bit external entropy value for key derivation of an enclave.
- @param ECX MSR_GOLDMONT_SGXOWNER1 (0x00000301)
+ @param ECX MSR_GOLDMONT_SGXOWNEREPOCH1 (0x00000301)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
@@ -873,11 +881,17 @@ typedef union {
@code
UINT64 Msr;
- Msr = AsmReadMsr64 (MSR_GOLDMONT_SGXOWNER1);
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_SGXOWNEREPOCH1);
@endcode
- @note MSR_GOLDMONT_SGXOWNER1 is defined as MSR_SGXOWNER1 in SDM.
+ @note MSR_GOLDMONT_SGXOWNEREPOCH1 is defined as MSR_SGXOWNEREPOCH1 in SDM.
**/
-#define MSR_GOLDMONT_SGXOWNER1 0x00000301
+#define MSR_GOLDMONT_SGXOWNEREPOCH1 0x00000301
+
+
+//
+// Define MSR_GOLDMONT_SGXOWNER1 for compatibility due to name change in the SDM.
+//
+#define MSR_GOLDMONT_SGXOWNER1 MSR_GOLDMONT_SGXOWNEREPOCH1
/**
--
2.15.0.windows.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Patch v3 14/14] UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h: Change structure definition.
2018-09-25 2:08 [Patch v3 00/14] Update MSR definitions Eric Dong
` (12 preceding siblings ...)
2018-09-25 2:08 ` [Patch v3 13/14] UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h: " Eric Dong
@ 2018-09-25 2:08 ` Eric Dong
2018-09-25 10:05 ` [Patch v3 00/14] Update MSR definitions Laszlo Ersek
2018-09-26 5:02 ` Ni, Ruiyu
15 siblings, 0 replies; 17+ messages in thread
From: Eric Dong @ 2018-09-25 2:08 UTC (permalink / raw)
To: edk2-devel; +Cc: Michael D Kinney, Ruiyu Ni, Laszlo Ersek
V3 changes include:
1. Keep the ReservedX not change if bit info not changed for this field.
V2 changes include:
1. Use X in ReservedX fields from totally new value if MSR structure definition changed.
For example, if in current structure, the max reserved variable is Reserved2, in new
definition, reserved variable is begin with Reserved3.
V1 Changes:
Changes includes:
1. Update MSR structure definition, change some reserved fields to useful fields:
1. MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER
2. MSR_XEON_PHI_SMM_MCA_CAP_REGISTER
2. For MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER structure, it expand the field range.
Old definition like below:
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 15:0] LVL_2 Base Address (R/W).
///
UINT32 Lvl2Base:16;
///
/// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the
/// maximum C-State code name to be included when IO read to MWAIT
/// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 100b - C4
/// is the max C-State to include 110b - C6 is the max C-State to include.
///
UINT32 CStateRange:3;
UINT32 Reserved1:13;
UINT32 Reserved2:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER;
This patch make below changes for this data structure, it expand "CStateRange" field width.
old one:
UINT32 CStateRange:3;
UINT32 Reserved1:13;
new one:
UINT32 CStateRange:7;
UINT32 Reserved1:9;
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong <eric.dong@intel.com>
---
UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h | 49 +++++++++++++++++++++++-----
1 file changed, 40 insertions(+), 9 deletions(-)
diff --git a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
index da74c2402c..1e22d98ad8 100644
--- a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
@@ -278,7 +278,25 @@ typedef union {
/// [Bit 15] CFG Lock (R/WO).
///
UINT32 CFGLock:1;
- UINT32 Reserved3:16;
+ UINT32 Reserved5:10;
+ ///
+ /// [Bit 26] C1 State Auto Demotion Enable (R/W) When set, the processor
+ /// will conditionally demote C3/C6/C7 requests to C1 based on uncore
+ /// auto-demote information.
+ ///
+ UINT32 C1StateAutoDemotionEnable:1;
+ UINT32 Reserved6:1;
+ ///
+ /// [Bit 28] C1 State Auto Undemotion Enable (R/W) When set, enables
+ /// Undemotion from Demoted C1.
+ ///
+ UINT32 C1StateAutoUndemotionEnable:1;
+ ///
+ /// [Bit 29] PKG C-State Auto Demotion Enable (R/W) When set, enables
+ /// Package C state demotion.
+ ///
+ UINT32 PKGC_StateAutoDemotionEnable:1;
+ UINT32 Reserved7:2;
UINT32 Reserved4:32;
} Bits;
///
@@ -325,13 +343,12 @@ typedef union {
///
UINT32 Lvl2Base:16;
///
- /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the
- /// maximum C-State code name to be included when IO read to MWAIT
- /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 100b - C4
- /// is the max C-State to include 110b - C6 is the max C-State to include.
+ /// [Bits 22:16] C-State Range (R/W) The IO-port block size in which
+ /// IO-redirection will be executed (0-127). Should be programmed based on
+ /// the number of LVLx registers existing in the chipset.
///
- UINT32 CStateRange:3;
- UINT32 Reserved1:13;
+ UINT32 CStateRange:7;
+ UINT32 Reserved3:9;
UINT32 Reserved2:32;
} Bits;
///
@@ -477,8 +494,22 @@ typedef union {
/// Individual bit fields
///
struct {
- UINT32 Reserved1:32;
- UINT32 Reserved2:26;
+ ///
+ /// [Bits 31:0] Bank Support (SMM-RO) One bit per MCA bank. If the bit is
+ /// set, that bank supports Enhanced MCA (Default all 0; does not support
+ /// EMCA).
+ ///
+ UINT32 BankSupport:32;
+ UINT32 Reserved4:24;
+ ///
+ /// [Bit 56] Targeted SMI (SMM-RO) Set if targeted SMI is supported.
+ ///
+ UINT32 TargetedSMI:1;
+ ///
+ /// [Bit 57] SMM_CPU_SVRSTR (SMM-RO) Set if SMM SRAM save/restore feature
+ /// is supported.
+ ///
+ UINT32 SMM_CPU_SVRSTR:1;
///
/// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
/// SMM code access restriction is supported and a host-space interface
--
2.15.0.windows.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [Patch v3 00/14] Update MSR definitions
2018-09-25 2:08 [Patch v3 00/14] Update MSR definitions Eric Dong
` (13 preceding siblings ...)
2018-09-25 2:08 ` [Patch v3 14/14] UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h: Change structure definition Eric Dong
@ 2018-09-25 10:05 ` Laszlo Ersek
2018-09-26 5:02 ` Ni, Ruiyu
15 siblings, 0 replies; 17+ messages in thread
From: Laszlo Ersek @ 2018-09-25 10:05 UTC (permalink / raw)
To: Eric Dong, edk2-devel; +Cc: Michael D Kinney, Ruiyu Ni
On 09/25/18 04:08, Eric Dong wrote:
> Current MSR definition are follow the SDM 2016-09 version. The latest SDM is 2018-05. This patch serial update the MSR related definition to follow the latest SDM 2018-05 version. MSR related defintion are saved at UefiCpuPkg\Include\Register\.
>
> V3 changes includes:
> 1. Only change Patch 8 and 14 which changed MSR data structures.
> 2. Keep ReservedX not change if bit info not changed for this field.
series
Acked-by: Laszlo Ersek <lersek@redhat.com>
Thanks!
Laszlo
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Patch v3 00/14] Update MSR definitions
2018-09-25 2:08 [Patch v3 00/14] Update MSR definitions Eric Dong
` (14 preceding siblings ...)
2018-09-25 10:05 ` [Patch v3 00/14] Update MSR definitions Laszlo Ersek
@ 2018-09-26 5:02 ` Ni, Ruiyu
15 siblings, 0 replies; 17+ messages in thread
From: Ni, Ruiyu @ 2018-09-26 5:02 UTC (permalink / raw)
To: Eric Dong, edk2-devel; +Cc: Michael D Kinney, Laszlo Ersek
On 9/25/2018 10:08 AM, Eric Dong wrote:
> Current MSR definition are follow the SDM 2016-09 version. The latest SDM is 2018-05. This patch serial update the MSR related definition to follow the latest SDM 2018-05 version. MSR related defintion are saved at UefiCpuPkg\Include\Register\.
>
> V3 changes includes:
> 1. Only change Patch 8 and 14 which changed MSR data structures.
> 2. Keep ReservedX not change if bit info not changed for this field.
>
> V2 changes include:
> 1. Only change Patch 8 and 14 which changed MSR data structures.
> 2. Use X in ReservedX fields from totally new value if MSR structure definition changed.
> For example, if in current structure, the max reserved variable is Reserved2, in new
> definition, reserved variable is begin with Reserved3.
>
> V1 Changes include:
> The changes for this serial includes:
> 1. Add new MSR definition and file.
> 2. Remove old MSR definition which not defined in new SDM.
> 3. Change MSR name to follow new SDM, keep old one for compatibility.
> 4. Change MSR data structure definition to follow new SDM.
> 5. Update comments to follow the new SDM, mainly related to chapter info.
>
> Below changes are incompatible changes:
> 2. Remove old MSR definition which not defined in new SDM.
> For this one, i search edk2 codebase, not found any code uses it. so no impact for edk2 codebase. Detail changes see patch 9 ~ 11.
>
> 4. Change MSR data structure definition to follow new SDM.
> For this one, new data structure just change the original reserved bits to valid bits, should have no impact for the current code. Detail see patch 8 and patch 14
>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Ruiyu Ni <ruiyu.ni@intel.com>
> Cc: Laszlo Ersek <lersek@redhat.com>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Eric Dong <eric.dong@intel.com>
>
>
> Eric Dong (14):
> UefiCpuPkg/Include/Register/Msr: Update reference spec info.
> UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h: Add new MSR file
> for goldmont plus microarchitecture.
> UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h: Add new MSR.
> UefiCpuPkg/Include/Register/Msr/*.h: Add new MSR.
> UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h: Add new MSR.
> UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h: Add new MSRs.
> UefiCpuPkg/Include/Register/ArchitecturalMsr.h: Add new MSR.
> UefiCpuPkg/Include/Register/ArchitecturalMsr.h: Change structure
> definition.
> UefiCpuPkg/Include/Register/Msr/Core2Msr.h: Remove old MSR.
> UefiCpuPkg/Include/Register/Msr/P6Msr.h: Remove old MSR.
> UefiCpuPkg/Include/Register/Msr/CoreMsr.h: Remove old MSR.
> UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h: Add new MSR name and
> keep old one.
> UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h: Add new MSR name and
> keep old one.
> UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h: Change structure
> definition.
>
> UefiCpuPkg/Include/Register/ArchitecturalMsr.h | 130 +-
> UefiCpuPkg/Include/Register/Msr.h | 7 +-
> UefiCpuPkg/Include/Register/Msr/AtomMsr.h | 28 +-
> UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h | 62 +-
> UefiCpuPkg/Include/Register/Msr/Core2Msr.h | 102 +-
> UefiCpuPkg/Include/Register/Msr/CoreMsr.h | 74 +-
> UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h | 88 +-
> UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h | 272 ++++
> UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h | 62 +-
> UefiCpuPkg/Include/Register/Msr/HaswellMsr.h | 34 +-
> UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h | 8 +-
> UefiCpuPkg/Include/Register/Msr/NehalemMsr.h | 52 +-
> UefiCpuPkg/Include/Register/Msr/P6Msr.h | 60 +-
> UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h | 202 +--
> UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h | 22 +-
> UefiCpuPkg/Include/Register/Msr/PentiumMsr.h | 12 +-
> UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h | 49 +-
> UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h | 100 +-
> UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h | 1602 ++++++++++++++++++++-
> UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h | 8 +-
> UefiCpuPkg/Include/Register/Msr/XeonDMsr.h | 84 +-
> UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h | 6 +-
> UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h | 332 ++++-
> 23 files changed, 2816 insertions(+), 580 deletions(-)
> create mode 100644 UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h
>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
--
Thanks,
Ray
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2018-09-26 5:01 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-09-25 2:08 [Patch v3 00/14] Update MSR definitions Eric Dong
2018-09-25 2:08 ` [Patch v3 01/14] UefiCpuPkg/Include/Register/Msr: Update reference spec info Eric Dong
2018-09-25 2:08 ` [Patch v3 02/14] UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h: Add new MSR file for goldmont plus microarchitecture Eric Dong
2018-09-25 2:08 ` [Patch v3 03/14] UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h: Add new MSR Eric Dong
2018-09-25 2:08 ` [Patch v3 04/14] UefiCpuPkg/Include/Register/Msr/*.h: " Eric Dong
2018-09-25 2:08 ` [Patch v3 05/14] UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h: " Eric Dong
2018-09-25 2:08 ` [Patch v3 06/14] UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h: Add new MSRs Eric Dong
2018-09-25 2:08 ` [Patch v3 07/14] UefiCpuPkg/Include/Register/ArchitecturalMsr.h: Add new MSR Eric Dong
2018-09-25 2:08 ` [Patch v3 08/14] UefiCpuPkg/Include/Register/ArchitecturalMsr.h: Change structure definition Eric Dong
2018-09-25 2:08 ` [Patch v3 09/14] UefiCpuPkg/Include/Register/Msr/Core2Msr.h: Remove old MSR Eric Dong
2018-09-25 2:08 ` [Patch v3 10/14] UefiCpuPkg/Include/Register/Msr/P6Msr.h: " Eric Dong
2018-09-25 2:08 ` [Patch v3 11/14] UefiCpuPkg/Include/Register/Msr/CoreMsr.h: " Eric Dong
2018-09-25 2:08 ` [Patch v3 12/14] UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h: Add new MSR name and keep old one Eric Dong
2018-09-25 2:08 ` [Patch v3 13/14] UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h: " Eric Dong
2018-09-25 2:08 ` [Patch v3 14/14] UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h: Change structure definition Eric Dong
2018-09-25 10:05 ` [Patch v3 00/14] Update MSR definitions Laszlo Ersek
2018-09-26 5:02 ` Ni, Ruiyu
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