From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.20; helo=mga02.intel.com; envelope-from=eric.dong@intel.com; receiver=edk2-devel@lists.01.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 0403021AE30DB for ; Mon, 24 Sep 2018 19:13:49 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Sep 2018 19:13:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,300,1534834800"; d="scan'208";a="93410454" Received: from ydong10-win10.ccr.corp.intel.com ([10.239.9.125]) by orsmga001.jf.intel.com with ESMTP; 24 Sep 2018 19:08:59 -0700 From: Eric Dong To: edk2-devel@lists.01.org Cc: Michael D Kinney , Ruiyu Ni , Laszlo Ersek Date: Tue, 25 Sep 2018 10:08:42 +0800 Message-Id: <20180925020853.25804-4-eric.dong@intel.com> X-Mailer: git-send-email 2.15.0.windows.1 In-Reply-To: <20180925020853.25804-1-eric.dong@intel.com> References: <20180925020853.25804-1-eric.dong@intel.com> Subject: [Patch v3 03/14] UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h: Add new MSR. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 25 Sep 2018 02:13:49 -0000 Changes includes: 1. Add new MSR: MSR_SILVERMONT_PLATFORM_INFO Cc: Michael D Kinney Cc: Ruiyu Ni Cc: Laszlo Ersek Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong --- UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h | 48 +++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h b/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h index 03bbd0af7c..c3d0f8c208 100644 --- a/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h +++ b/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h @@ -375,6 +375,54 @@ typedef union { } MSR_SILVERMONT_FSB_FREQ_REGISTER; +/** + Package. Platform Information: Contains power management and other model + specific features enumeration. See http://biosbits.org. + + @param ECX MSR_SILVERMONT_PLATFORM_INFO (0x000000CE) + @param EAX Lower 32-bits of MSR value. + Described by the type MSR_SILVERMONT_PLATFORM_INFO_REGISTER. + @param EDX Upper 32-bits of MSR value. + Described by the type MSR_SILVERMONT_PLATFORM_INFO_REGISTER. + + Example usage + @code + MSR_SILVERMONT_PLATFORM_INFO_REGISTER Msr; + + Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PLATFORM_INFO); + AsmWriteMsr64 (MSR_SILVERMONT_PLATFORM_INFO, Msr.Uint64); + @endcode +**/ +#define MSR_SILVERMONT_PLATFORM_INFO 0x000000CE + +/** + MSR information returned for MSR index #MSR_SILVERMONT_PLATFORM_INFO +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + UINT32 Reserved1:8; + /// + /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) This is the ratio + /// of the maximum frequency that does not require turbo. Frequency = + /// ratio * Scalable Bus Frequency. + /// + UINT32 MaximumNon_TurboRatio:8; + UINT32 Reserved2:16; + UINT32 Reserved3:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SILVERMONT_PLATFORM_INFO_REGISTER; + /** Module. C-State Configuration Control (R/W) Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state -- 2.15.0.windows.1