From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.151; helo=mga17.intel.com; envelope-from=ruiyu.ni@intel.com; receiver=edk2-devel@lists.01.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 02E062194D3AE for ; Mon, 24 Sep 2018 22:21:19 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Sep 2018 22:21:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,300,1534834800"; d="scan'208";a="235667708" Received: from ray-dev.ccr.corp.intel.com ([10.239.9.8]) by orsmga004.jf.intel.com with ESMTP; 24 Sep 2018 22:21:17 -0700 From: Ruiyu Ni To: edk2-devel@lists.01.org Cc: Michael D Kinney , Eric Dong , Sean Brogan Date: Tue, 25 Sep 2018 13:22:13 +0800 Message-Id: <20180925052213.12764-1-ruiyu.ni@intel.com> X-Mailer: git-send-email 2.16.1.windows.1 Subject: [PATCH] UefiCpuPkg/MtrrLib: Revert "Skip MSR access when the pair is invalid" X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 25 Sep 2018 05:21:20 -0000 REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1187 The patch reverts 9c8c4478cfcacaf5fd60b75ff78d26732d93a5b8 "UefiCpuPkg/MtrrLib: Skip Base MSR access when the pair is invalid". Microsoft Windows will report an error in event manager if MTRR usage is different across hibernate even when the difference is in an non valid MTRR pair. This seems like a bug in Windows but for compatibility and servicing reasons we think a change in UEFI would wise. A Windows change has already been submitted for the next iteration (2019 time frame). Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni Cc: Michael D Kinney Cc: Eric Dong Cc: Sean Brogan --- UefiCpuPkg/Library/MtrrLib/MtrrLib.c | 29 +++++++++++++---------------- 1 file changed, 13 insertions(+), 16 deletions(-) diff --git a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c b/UefiCpuPkg/Library/MtrrLib/MtrrLib.c index dfce9a996b..086f7ad8f0 100644 --- a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c +++ b/UefiCpuPkg/Library/MtrrLib/MtrrLib.c @@ -449,13 +449,10 @@ MtrrGetVariableMtrrWorker ( for (Index = 0; Index < VariableMtrrCount; Index++) { if (MtrrSetting == NULL) { - VariableSettings->Mtrr[Index].Mask = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1)); - // - // Skip to read the Base MSR when the Mask.V is not set. - // - if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *)&VariableSettings->Mtrr[Index].Mask)->Bits.V != 0) { - VariableSettings->Mtrr[Index].Base = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1)); - } + VariableSettings->Mtrr[Index].Base = + AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1)); + VariableSettings->Mtrr[Index].Mask = + AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1)); } else { VariableSettings->Mtrr[Index].Base = MtrrSetting->Variables.Mtrr[Index].Base; VariableSettings->Mtrr[Index].Mask = MtrrSetting->Variables.Mtrr[Index].Mask; @@ -2604,14 +2601,14 @@ MtrrSetVariableMtrrWorker ( ASSERT (VariableMtrrCount <= ARRAY_SIZE (VariableSettings->Mtrr)); for (Index = 0; Index < VariableMtrrCount; Index++) { - // - // Mask MSR is always updated since caller might need to invalidate the MSR pair. - // Base MSR is skipped when Mask.V is not set. - // - AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1), VariableSettings->Mtrr[Index].Mask); - if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *)&VariableSettings->Mtrr[Index].Mask)->Bits.V != 0) { - AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1), VariableSettings->Mtrr[Index].Base); - } + AsmWriteMsr64 ( + MSR_IA32_MTRR_PHYSBASE0 + (Index << 1), + VariableSettings->Mtrr[Index].Base + ); + AsmWriteMsr64 ( + MSR_IA32_MTRR_PHYSMASK0 + (Index << 1), + VariableSettings->Mtrr[Index].Mask + ); } } @@ -2868,7 +2865,7 @@ MtrrDebugPrintAllMtrrsWorker ( } ContainVariableMtrr = FALSE; for (Index = 0; Index < VariableMtrrCount; Index++) { - if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *)&Mtrrs->Variables.Mtrr[Index].Mask)->Bits.V == 0) { + if ((Mtrrs->Variables.Mtrr[Index].Mask & BIT11) == 0) { // // If mask is not valid, then do not display range // -- 2.16.1.windows.1