From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=hao.a.wu@intel.com; receiver=edk2-devel@lists.01.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 128E721A02937 for ; Mon, 24 Sep 2018 23:13:08 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Sep 2018 23:13:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,300,1534834800"; d="scan'208";a="265457326" Received: from shwdeopenpsi014.ccr.corp.intel.com ([10.239.9.19]) by fmsmga005.fm.intel.com with ESMTP; 24 Sep 2018 23:13:04 -0700 From: Hao Wu To: edk2-devel@lists.01.org Cc: Hao Wu , Ard Biesheuvel , Leif Lindholm , Laszlo Ersek , Jiewen Yao , Michael D Kinney , Liming Gao Date: Tue, 25 Sep 2018 14:12:55 +0800 Message-Id: <20180925061259.31680-2-hao.a.wu@intel.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20180925061259.31680-1-hao.a.wu@intel.com> References: <20180925061259.31680-1-hao.a.wu@intel.com> Subject: [PATCH v2 1/5] MdePkg/BaseLib: Add new AsmLfence API X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 25 Sep 2018 06:13:08 -0000 REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1193 This commit will add a new BaseLib API AsmLfence(). This API will perform a serializing operation on all load-from-memory instructions that were issued prior to the call of this function. Please note that this API is only available on IA-32 and x64. The purpose of adding this API is to mitigate of the [CVE-2017-5753] Bounds Check Bypass issue when untrusted data are being processed within SMM. More details can be referred at the 'Bounds check bypass mitigation' section at the below link: https://software.intel.com/security-software-guidance/insights/host-firmware-speculative-execution-side-channel-mitigation Cc: Ard Biesheuvel Cc: Leif Lindholm Cc: Laszlo Ersek Cc: Jiewen Yao Cc: Michael D Kinney Cc: Liming Gao Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu --- MdePkg/Include/Library/BaseLib.h | 13 +++++++ MdePkg/Library/BaseLib/BaseLib.inf | 2 ++ MdePkg/Library/BaseLib/Ia32/Lfence.nasm | 37 +++++++++++++++++++ MdePkg/Library/BaseLib/X64/Lfence.nasm | 38 ++++++++++++++++++++ 4 files changed, 90 insertions(+) diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h index 123ae19dc2..656b7736b1 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -9139,6 +9139,19 @@ AsmWriteTr ( ); /** + Performs a serializing operation on all load-from-memory instructions that + were issued prior the AsmLfence function. + + Executes a LFENCE instruction. This function is only available on IA-32 and x64. + +**/ +VOID +EFIAPI +AsmLfence ( + VOID + ); + +/** Patch the immediate operand of an IA32 or X64 instruction such that the byte, word, dword or qword operand is encoded at the end of the instruction's binary representation. diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf index a1b5ec4b75..ed15c025f9 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -68,6 +68,7 @@ [Sources.Ia32] Ia32/WriteTr.nasm + Ia32/Lfence.nasm Ia32/Wbinvd.c | MSFT Ia32/WriteMm7.c | MSFT @@ -346,6 +347,7 @@ X64/EnableCache.nasm X64/DisableCache.nasm X64/WriteTr.nasm + X64/Lfence.nasm X64/CpuBreakpoint.c | MSFT X64/WriteMsr64.c | MSFT diff --git a/MdePkg/Library/BaseLib/Ia32/Lfence.nasm b/MdePkg/Library/BaseLib/Ia32/Lfence.nasm new file mode 100644 index 0000000000..f8b2550ef8 --- /dev/null +++ b/MdePkg/Library/BaseLib/Ia32/Lfence.nasm @@ -0,0 +1,37 @@ +;------------------------------------------------------------------------------ ; +; Copyright (c) 2018, Intel Corporation. All rights reserved.
+; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +; Module Name: +; +; Lfence.nasm +; +; Abstract: +; +; Performs a serializing operation on all load-from-memory instructions that +; were issued prior to the call of this function. +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; AsmLfence ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmLfence) +ASM_PFX(AsmLfence): + lfence + ret + diff --git a/MdePkg/Library/BaseLib/X64/Lfence.nasm b/MdePkg/Library/BaseLib/X64/Lfence.nasm new file mode 100644 index 0000000000..e81c77964b --- /dev/null +++ b/MdePkg/Library/BaseLib/X64/Lfence.nasm @@ -0,0 +1,38 @@ +;------------------------------------------------------------------------------ ; +; Copyright (c) 2018, Intel Corporation. All rights reserved.
+; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +; Module Name: +; +; Lfence.nasm +; +; Abstract: +; +; Performs a serializing operation on all load-from-memory instructions that +; were issued prior to the call of this function. +; +; Notes: +; +;------------------------------------------------------------------------------ + + DEFAULT REL + SECTION .text + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; AsmLfence ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmLfence) +ASM_PFX(AsmLfence): + lfence + ret + -- 2.12.0.windows.1