From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.151; helo=mga17.intel.com; envelope-from=ruiyu.ni@intel.com; receiver=edk2-devel@lists.01.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3268421155D3C for ; Mon, 24 Sep 2018 23:22:21 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Sep 2018 23:22:20 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,301,1534834800"; d="scan'208";a="91651462" Received: from ray-dev.ccr.corp.intel.com ([10.239.9.8]) by fmsmga004.fm.intel.com with ESMTP; 24 Sep 2018 23:20:23 -0700 From: Ruiyu Ni To: edk2-devel@lists.01.org Cc: Star Zeng Date: Tue, 25 Sep 2018 14:21:15 +0800 Message-Id: <20180925062117.34772-3-ruiyu.ni@intel.com> X-Mailer: git-send-email 2.16.1.windows.1 In-Reply-To: <20180925062117.34772-1-ruiyu.ni@intel.com> References: <20180925062117.34772-1-ruiyu.ni@intel.com> Subject: [PATCH v2 2/4] MdeModulePkg/PciHostBridge: Fix a bug that prevents PMEM access X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 25 Sep 2018 06:22:21 -0000 REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1196 RootBridgeIoCheckParameter() verifies that the requested MMIO access can fit in any of the MEM/PMEM 32/64 ranges. But today's logic somehow only checks the requested access against MEM 32/64 ranges. It should also check the requested access against PMEM 32/64 ranges. The patch fixes this issue. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni Cc: Star Zeng Reviewed-by: Laszlo Ersek Reviewed-by: Garrett Kirkendall --- MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c index 2c373e41de..87385aa172 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c @@ -413,12 +413,18 @@ RootBridgeIoCheckParameter ( // By comparing the Address against Limit we know which range to be used // for checking // - if (Address + Length <= RootBridge->Mem.Limit + 1) { - Base = RootBridge->Mem.Base; + if ((Address >= RootBridge->Mem.Base) && (Address + Length <= RootBridge->Mem.Limit + 1)) { + Base = RootBridge->Mem.Base; Limit = RootBridge->Mem.Limit; - } else { - Base = RootBridge->MemAbove4G.Base; + } else if ((Address >= RootBridge->PMem.Base) && (Address + Length <= RootBridge->PMem.Limit + 1)) { + Base = RootBridge->PMem.Base; + Limit = RootBridge->PMem.Limit; + } else if ((Address >= RootBridge->MemAbove4G.Base) && (Address + Length <= RootBridge->MemAbove4G.Limit + 1)) { + Base = RootBridge->MemAbove4G.Base; Limit = RootBridge->MemAbove4G.Limit; + } else { + Base = RootBridge->PMemAbove4G.Base; + Limit = RootBridge->PMemAbove4G.Limit; } } else { PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &Address; -- 2.16.1.windows.1