From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.88; helo=mga01.intel.com; envelope-from=eric.dong@intel.com; receiver=edk2-devel@lists.01.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C9F0B21165245 for ; Thu, 11 Oct 2018 00:05:57 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Oct 2018 00:05:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,367,1534834800"; d="scan'208";a="98424559" Received: from ydong10-win10.ccr.corp.intel.com ([10.239.9.125]) by orsmga001.jf.intel.com with ESMTP; 11 Oct 2018 00:05:55 -0700 From: Eric Dong To: edk2-devel@lists.01.org Cc: Ruiyu Ni , Laszlo Ersek , Jian J Wang Date: Thu, 11 Oct 2018 15:05:53 +0800 Message-Id: <20181011070553.6996-1-eric.dong@intel.com> X-Mailer: git-send-email 2.15.0.windows.1 Subject: [Patch v5] UefiCpuPkg/S3Resume2Pei: disable paging before creating new page table. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 11 Oct 2018 07:05:58 -0000 V5: 1. Add ASSERT to indicate this assumption that environment is 32 bit mode. 2. Add description in INF about this driver's expected result in different environment. V4: Only disable paging when it is enabled. V3 changes: No need to change inf file. V2 changes: Only disable paging in 32 bit mode, no matter it is enable or not. V1 changes: PEI Stack Guard needs to enable paging. This might cause #GP if code trying to write CR3 register with PML4 page table while the processor is enabled with PAE paging. Simply disabling paging before updating CR3 can solve this conflict. It's an regression caused by change: 0a0d5296e448fc350de1594c49b9c0deff7fad60 BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1232 Cc: Ruiyu Ni Cc: Laszlo Ersek Cc: Jian J Wang Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong --- UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c | 17 +++++++++++++++++ UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf | 10 ++++++++++ 2 files changed, 27 insertions(+) diff --git a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c index f164c1713b..8415ab1583 100644 --- a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c +++ b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c @@ -964,6 +964,7 @@ S3RestoreConfig2 ( VOID *GuidHob; BOOLEAN Build4GPageTableOnly; BOOLEAN InterruptStatus; + IA32_CR0 CR0Reg; TempAcpiS3Context = 0; TempEfiBootScriptExecutorVariable = 0; @@ -1045,6 +1046,13 @@ S3RestoreConfig2 ( // GuidHob = GetFirstGuidHob (&gEfiAcpiVariableGuid); if (GuidHob != NULL) { + // + // Below SwitchStack/AsmEnablePaging64 function has + // assumption that it's in 32 bits mode now. + // Add ASSERT code to indicate this assumption. + // + ASSERT(sizeof (UINTN) == sizeof (UINT32)); + Status = PeiServicesLocatePpi ( &gPeiSmmAccessPpiGuid, 0, @@ -1105,6 +1113,15 @@ S3RestoreConfig2 ( // SetInterruptState (InterruptStatus); + CR0Reg.UintN = AsmReadCr0 (); + if (CR0Reg.Bits.PG != 0) { + // + // We're in 32-bit mode, with paging enabled. We can't set CR3 to + // the 64-bit page tables without first disabling paging. + // + CR0Reg.Bits.PG = 0; + AsmWriteCr0 (CR0Reg.UintN); + } AsmWriteCr3 ((UINTN)SmmS3ResumeState->SmmS3Cr3); // diff --git a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf index 6ce1bf944c..1d0740526f 100644 --- a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf +++ b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf @@ -33,6 +33,16 @@ # VALID_ARCHITECTURES = IA32 X64 # +# +# This module is not always workable in IA32 and X64 mode. It has below result: +# when it works with SMM mode: +# =============================== +# SMM:used SMM:unused +# PEI:IA32 works works +# PEI:X64 fails works +# =============================== +# + [Sources] S3Resume.c -- 2.15.0.windows.1