From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.31; helo=mga06.intel.com; envelope-from=eric.dong@intel.com; receiver=edk2-devel@lists.01.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9F20321164EE8 for ; Sun, 14 Oct 2018 19:50:07 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Oct 2018 19:50:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,383,1534834800"; d="scan'208";a="241323796" Received: from ydong10-win10.ccr.corp.intel.com ([10.239.9.125]) by orsmga004.jf.intel.com with ESMTP; 14 Oct 2018 19:50:06 -0700 From: Eric Dong To: edk2-devel@lists.01.org Cc: Ruiyu Ni , Laszlo Ersek Date: Mon, 15 Oct 2018 10:49:44 +0800 Message-Id: <20181015024948.228-1-eric.dong@intel.com> X-Mailer: git-send-email 2.15.0.windows.1 Subject: [Patch 0/4] Fix performance issue caused by Set MSR task. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 15 Oct 2018 02:50:07 -0000 In a system which has multiple cores, current set register value task costs huge times. After investigation, current set MSR task costs most of the times. Current logic uses SpinLock to let set MSR task as an single thread task for all cores. Because MSR has scope attribute which may cause GP fault if multiple APs set MSR at the same time, current logic use an easiest solution (use SpinLock) to avoid this issue, but it will cost huge times. In order to fix this performance issue, new solution will set MSRs base on their scope attribute. After this, the SpinLock will not needed. Without SpinLock, new issue raised which is caused by MSR dependence. For example, MSR A depends on MSR B which means MSR A must been set after MSR B has been set. Also MSR B is package scope level and MSR A is thread scope level. If system has multiple threads, Thread 1 needs to set the thread level MSRs and thread 2 needs to set thread and package level MSRs. Set MSRs task for thread 1 and thread 2 like below: Thread 1 Thread 2 MSR B N Y MSR A Y Y If driver don't control execute MSR order, for thread 1, it will execute MSR A first, but at this time, MSR B not been executed yet by thread 2. system may trig exception at this time. In order to fix the above issue, driver introduces semaphore logic to control the MSR execute sequence. For the above case, a semaphore will be add between MSR A and B for all threads. Semaphore has scope info for it. The possible scope value is core or package. For each thread, when it meets a semaphore during it set registers, it will 1) release semaphore (+1) for each threads in this core or package(based on the scope info for this semaphore) 2) acquire semaphore (-1) for all the threads in this core or package(based on the scope info for this semaphore). With these two steps, driver can control MSR sequence. Sample code logic like below: // // First increase semaphore count by 1 for processors in this package. // for (ProcessorIndex = 0; ProcessorIndex < PackageThreadsCount ; ProcessorIndex ++) { LibReleaseSemaphore ((UINT32 *) &SemaphorePtr[PackageOffset + ProcessorIndex]); } // // Second, check whether the count has reach the check number. // for (ProcessorIndex = 0; ProcessorIndex < ValidApCount; ProcessorIndex ++) { LibWaitForSemaphore (&SemaphorePtr[ApOffset]); } Platform Requirement: 1. This change requires register MSR setting base on MSR scope info. If still register MSR for all threads, exception may raised. Known limitation: 1. Current CpuFeatures driver supports DXE instance and PEI instance. But semaphore logic requires Aps execute in async mode which is not supported by PEI driver. So CpuFeature PEI instance not works after this change. We plan to support async mode for PEI in phase 2 for this task. 2. Current execute MSR task code in duplicated in PiSmmCpuDxeSmm driver and RegisterCpuFeaturesLib library because the schedule limitation. Will merge the code to RegisterCpuFeaturesLib and export as an API in phase 2 for this task. Extra Notes: I will send the other patch to set MSR base on scope info and check in it before check in this serial. Cc: Ruiyu Ni Cc: Laszlo Ersek Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong Eric Dong (4): UefiCpuPkg/Include/AcpiCpuData.h: Add Semaphore related Information. UefiCpuPkg/RegisterCpuFeaturesLib.h: Add new dependence types. UefiCpuPkg/RegisterCpuFeaturesLib: Add logic to support semaphore type. UefiCpuPkg/PiSmmCpuDxeSmm: Add logic to support semaphore type. UefiCpuPkg/Include/AcpiCpuData.h | 23 +- .../Include/Library/RegisterCpuFeaturesLib.h | 25 +- .../RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 324 ++++++++++++--- .../DxeRegisterCpuFeaturesLib.c | 71 +++- .../DxeRegisterCpuFeaturesLib.inf | 3 + .../PeiRegisterCpuFeaturesLib.c | 55 ++- .../PeiRegisterCpuFeaturesLib.inf | 1 + .../RegisterCpuFeaturesLib/RegisterCpuFeatures.h | 51 ++- .../RegisterCpuFeaturesLib.c | 452 ++++++++++++++++++--- UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 316 +++++++------- UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 3 - UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 3 +- 12 files changed, 1063 insertions(+), 264 deletions(-) -- 2.15.0.windows.1