From: Ming Huang <ming.huang@linaro.org>
To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org,
edk2-devel@lists.01.org, graeme.gregory@linaro.org
Cc: ard.biesheuvel@linaro.org, michael.d.kinney@intel.com,
lersek@redhat.com, wanghuiqiang@huawei.com,
huangming23@huawei.com, zhangjinsong2@huawei.com,
huangdaode@hisilicon.com, john.garry@huawei.com,
xinliang.liu@linaro.org, zhangfeng56@huawei.com,
Ming Huang <ming.huang@linaro.org>
Subject: [PATCH edk2/ArmPkg v1 1/1] ArmPkg: Fix Gic interrupt routing modes bug
Date: Mon, 29 Oct 2018 12:57:08 +0800 [thread overview]
Message-ID: <20181029045708.6292-2-ming.huang@linaro.org> (raw)
In-Reply-To: <20181029045708.6292-1-ming.huang@linaro.org>
As GicV3 Spec, Interrupt Routing Modes should be 0 for
routing the SPIs to the primary CPU.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <ming.huang@linaro.org>
---
ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
index 01154848f443..1558db31713a 100644
--- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
+++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
@@ -469,7 +469,7 @@ GicV3DxeInitialize (
for (Index = 0; Index < (mGicNumInterrupts - 32); Index++) {
MmioWrite32 (
mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8),
- CpuTarget | ARM_GICD_IROUTER_IRM
+ CpuTarget
);
}
}
--
2.18.0
next prev parent reply other threads:[~2018-10-29 4:57 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-29 4:57 [PATCH edk2/ArmPkg v1 0/1] Fix Gic interrupt routing modes bug Ming Huang
2018-10-29 4:57 ` Ming Huang [this message]
2018-11-07 14:48 ` [PATCH edk2/ArmPkg v1 1/1] ArmPkg: " Ard Biesheuvel
[not found] ` <9c5536f3-29c1-9cd5-3078-1596e2ce25ba@arm.com>
2018-11-07 15:23 ` Ard Biesheuvel
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