From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::444; helo=mail-pf1-x444.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf1-x444.google.com (mail-pf1-x444.google.com [IPv6:2607:f8b0:4864:20::444]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B18ED2117CE98 for ; Sun, 28 Oct 2018 21:57:18 -0700 (PDT) Received: by mail-pf1-x444.google.com with SMTP id c25-v6so3387575pfe.6 for ; Sun, 28 Oct 2018 21:57:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=iu2NA7uMpSMZgzwQfxkKQ/+DQ5Y6tdymCZT1FqqjEFU=; b=DhsWFW4fioNVXc9wKdi36qbTuqcOJhpk+kRFxtWQO3vpjts7htCymxJL9AzCzTJ5yt ppARhC//fUul++3z2Ztsm305BhoxhuEzJxS45ldb6wQM4d+K9U4KxwqOf3icPsxBFUom k2UWG2g791sIbU4RRBO+ePdWx299eY2+u0Tck= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=iu2NA7uMpSMZgzwQfxkKQ/+DQ5Y6tdymCZT1FqqjEFU=; b=jpG0pfaka3mmBuP+kRvlLWKhFnAefhN2ZqfR0nNBjrvFd2BLwS/we0c4oaz4Be6H5s n7ypfMvQlcMY2W0t9GCordYAYf/0pfHLUW0IfLOjnXL6oZcGzUAwuDWk6AooQYn9OwLR bbgICRXYaKAHxqvbNoDBvrCF+SOeAWbbgq4t+Qt81U1Gd0kr/CHW7tcIeINXA3yO6AS+ sFYC2VqNRpzuJqco0PrLiTT6oodfMwvPmT7eS1KwUsciD0bsp7NvlvQfRG/zkgPLqhnB NL7A2p2Q7FMRG7ML284v/EA07B/Z1hi7iYV/2yLk+PPjmi5I6sf+ehLadlo8R1NkWLSM c8zA== X-Gm-Message-State: AGRZ1gKJZtGaEEWe6+zKdEaMIE4qjKiiNY98enXWMPeZV4JgMnYVy5DL sYm2qKOGpScn7G8RvincP4facg== X-Google-Smtp-Source: AJdET5ciWTHStw/y8jyVk1c37XpotEHBICLG5lBxqK+/VB2uqNfQk3jpb7ahLtH/QKqN/jwISP3DAg== X-Received: by 2002:a62:2f44:: with SMTP id v65-v6mr13527863pfv.235.1540789038338; Sun, 28 Oct 2018 21:57:18 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id c2-v6sm20287231pfn.95.2018.10.28.21.57.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 28 Oct 2018 21:57:17 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Cc: ard.biesheuvel@linaro.org, michael.d.kinney@intel.com, lersek@redhat.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, john.garry@huawei.com, xinliang.liu@linaro.org, zhangfeng56@huawei.com, Ming Huang Date: Mon, 29 Oct 2018 12:57:08 +0800 Message-Id: <20181029045708.6292-2-ming.huang@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20181029045708.6292-1-ming.huang@linaro.org> References: <20181029045708.6292-1-ming.huang@linaro.org> Subject: [PATCH edk2/ArmPkg v1 1/1] ArmPkg: Fix Gic interrupt routing modes bug X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 29 Oct 2018 04:57:18 -0000 As GicV3 Spec, Interrupt Routing Modes should be 0 for routing the SPIs to the primary CPU. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang --- ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c index 01154848f443..1558db31713a 100644 --- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c +++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c @@ -469,7 +469,7 @@ GicV3DxeInitialize ( for (Index = 0; Index < (mGicNumInterrupts - 32); Index++) { MmioWrite32 ( mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8), - CpuTarget | ARM_GICD_IROUTER_IRM + CpuTarget ); } } -- 2.18.0