From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.151; helo=mga17.intel.com; envelope-from=ruiyu.ni@intel.com; receiver=edk2-devel@lists.01.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E2EDC2117B552 for ; Mon, 29 Oct 2018 19:50:12 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Oct 2018 19:50:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,442,1534834800"; d="scan'208";a="85225461" Received: from ray-dev.ccr.corp.intel.com ([10.239.9.11]) by orsmga007.jf.intel.com with ESMTP; 29 Oct 2018 19:50:11 -0700 From: Ruiyu Ni To: edk2-devel@lists.01.org Cc: Jiewen Yao , Michael Kinney Date: Tue, 30 Oct 2018 10:51:28 +0800 Message-Id: <20181030025128.60448-1-ruiyu.ni@intel.com> X-Mailer: git-send-email 2.16.1.windows.1 Subject: [PATCH v3] MdeModulePkg/PiSmmIpl: Do not reset SMRAM to UC when CPU driver runs X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 30 Oct 2018 02:50:13 -0000 Today's PiSmmIpl implementation initially sets SMRAM to WB to speed up the SMM core/modules loading before SMM CPU driver runs. When SMM CPU driver runs, PiSmmIpl resets the SMRAM to UC. It's done in SmmIplDxeDispatchEventNotify(). COMM_BUFFER_SMM_DISPATCH_RESTART is returned from SMM core that SMM CPU driver is just dispatched. Since now the SMRR is widely used to control the SMRAM cache setting. It's not needed to reset the SMRAM to UC anymore. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni Cc: Jiewen Yao Cc: Michael Kinney --- MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) diff --git a/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c b/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c index f8cbe1704b..2fb877127b 100644 --- a/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c +++ b/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c @@ -672,21 +672,10 @@ SmmIplDxeDispatchEventNotify ( return; } - // - // Attempt to reset SMRAM cacheability to UC - // Assume CPU AP is available at this time - // - Status = gDS->SetMemorySpaceAttributes( - mSmramCacheBase, - mSmramCacheSize, - EFI_MEMORY_UC - ); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_WARN, "SMM IPL failed to reset SMRAM window to EFI_MEMORY_UC\n")); - } - // // Close all SMRAM ranges to protect SMRAM + // NOTE: SMRR is enabled by CPU SMM driver by calling SmmCpuFeaturesInitializeProcessor() from SmmCpuFeaturesLib + // so no need to reset the SMRAM to UC in MTRR. // Status = mSmmAccess->Close (mSmmAccess); ASSERT_EFI_ERROR (Status); -- 2.16.1.windows.1