From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::444; helo=mail-wr1-x444.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1F91D21189FBA for ; Thu, 1 Nov 2018 11:26:02 -0700 (PDT) Received: by mail-wr1-x444.google.com with SMTP id z3-v6so2162863wru.4 for ; Thu, 01 Nov 2018 11:26:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=VfY/V88I0yP8kpdk0q7L+qw3Qp19LKSoWlGUPJNeFQ4=; b=VsYJmlFot+VeCYr2VqEoBipzq4y2wB5lFn3mXasLz/0XGv/JYOB+WlI1IWlO8hz4Sv BEB6eagN68Pljw+OzimRn1Ez3JnwTN/i+OtQ0VuGuxuXXJ8gZ43dHGhxgMVIm9LCiwjT DkAtbt3QdDZWJHFu2z/zzoCmIjlOSbz99Msow= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=VfY/V88I0yP8kpdk0q7L+qw3Qp19LKSoWlGUPJNeFQ4=; b=EOKbAT3vnzqYe+JX8ct0KZIIcEnbXtn1AV46jBoPqB2Av4VAVf640DbBqhRtEG+LU/ PMEZdZQRvUWAWYuTgw569OJqXysswDf3+yM+fILSGJuxBnxqzwJoWCLZZSx7XJMevkJr LnYq1/UUz6lO6ZR5BZrfSEFwJc9H3gB0A0tFJUvw9qb32UcM4CTZ573WLZ6wjgeSh5xS Zh0O1LwJE+wthbqgUjCt4AIZS1yfPvShTiL/P3xYM5k5kITpthWDoOwqbLmMiFGB47/X KV/1h6HG534dW6iproKBf+i5zysg73c7CzzozCA5xkz6ZfA6zCXmQ0S1ISfSF3lHdbsV 6+7g== X-Gm-Message-State: AGRZ1gIU2d1gDMxpMfmC/QgL7vtfYBghz2nnq70IdpFfcDUfJ2Itv1h0 0V8q9fKrlP+txPjM1R/Sz0CVOg== X-Google-Smtp-Source: AJdET5dbEb3x8FIjTFvoAIuDoALhOMbt72a4rtY5xBSOeHyfoueWGTKh9GWKSNOg5pIcoGWK1dXceg== X-Received: by 2002:a5d:5086:: with SMTP id a6-v6mr7466094wrt.31.1541096761408; Thu, 01 Nov 2018 11:26:01 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id j72-v6sm21025813wrj.7.2018.11.01.11.26.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 01 Nov 2018 11:26:00 -0700 (PDT) Date: Thu, 1 Nov 2018 18:25:58 +0000 From: Leif Lindholm To: Chris Co Cc: "edk2-devel@lists.01.org" , Ard Biesheuvel , Michael D Kinney Message-ID: <20181101182558.i3czrpn2xgk57ura@bivouac.eciton.net> References: <20180921082542.35768-1-christopher.co@microsoft.com> <20180921082542.35768-11-christopher.co@microsoft.com> MIME-Version: 1.0 In-Reply-To: <20180921082542.35768-11-christopher.co@microsoft.com> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms 10/27] Silicon/NXP: Add iMX6Pkg dec X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 01 Nov 2018 18:26:03 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Sep 21, 2018 at 08:26:00AM +0000, Chris Co wrote: > This adds PCD declarations common across NXP i.MX6 SoCs > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Christopher Co > Cc: Ard Biesheuvel > Cc: Leif Lindholm > Cc: Michael D Kinney > --- > Silicon/NXP/iMX6Pkg/iMX6Pkg.dec | 143 ++++++++++++++++++++ > 1 file changed, 143 insertions(+) > > diff --git a/Silicon/NXP/iMX6Pkg/iMX6Pkg.dec b/Silicon/NXP/iMX6Pkg/iMX6Pkg.dec > new file mode 100644 > index 000000000000..99e1c7e6a4b8 > --- /dev/null > +++ b/Silicon/NXP/iMX6Pkg/iMX6Pkg.dec > @@ -0,0 +1,143 @@ > +# > +# Copyright (c) 2018 Microsoft Corporation. All rights reserved. > +# > +# This program and the accompanying materials > +# are licensed and made available under the terms and conditions of the BSD License > +# which accompanies this distribution. The full text of the license may be found at > +# http://opensource.org/licenses/bsd-license.php > +# > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +# > + > +[Defines] > + DEC_SPECIFICATION = 0x0001001A > + PACKAGE_NAME = iMX6Pkg > + PACKAGE_GUID = 6eba6648-d853-4eb3-9761-528b82d5ab04 > + PACKAGE_VERSION = 0.1 > + > +################################################################################ > +# > +# Include Section - list of Include Paths that are provided by this package. > +# Comments are used for Keywords and Module Types. > +# > +# Supported Module Types: > +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER > +# DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION > +# > +################################################################################ > +[Includes.common] > + Include # Root include for the package > + Silicon/NXP/iMXPlatformPkg/Include # Root include for the iMXPlatform package > + > +[LibraryClasses] > + iMXIoMuxLib|Silicon/NXP/iMX6Pkg/Include/iMX6IoMux.h > + iMX6ClkPwrLib|Silicon/NXP/iMX6Pkg/Include/iMX6ClkPwr.h > + iMX6UsbPhyLib|Silicon/NXP/iMX6Pkg/Include/iMX6UsbPhy.h > + > +[Protocols.common] > + gEfiSdhcProtocolGuid = { 0x46055b0f, 0x992a, 0x4ad7, { 0x8f, 0x81, 0x14, 0x81, 0x86, 0xff, 0xdf, 0x72 } } This is too generic a name to belong to a protocol GUID defined in a platform-specific package. (But the Sdhc implementation is a bit up in the air, so...) > + > +[Guids.common] > + giMX6TokenSpaceGuid = { 0x24b09abe, 0x4e47, 0x481c, { 0xa9, 0xad, 0xce, 0xf1, 0x2c, 0x39, 0x23, 0x27} } > + > +[PcdsFixedAtBuild.common] > + # > + # Frame buffer is set to the first addressable memory on the i.MX6 > + # Sabre board for convenience. > + # Keep in mind that this chunk of memory is the only one that remains fixed > + # through the various boot stages (primary boot->UEFI->Windows. > + # > + giMX6TokenSpaceGuid.PcdFrameBufferBase|0x10000000|UINT32|0x0000000A > + giMX6TokenSpaceGuid.PcdFrameBufferSize|0x00800000|UINT32|0x0000000B > + > + # > + # Performance counter > + # > + gEmbeddedTokenSpaceGuid.PcdEmbeddedFdPerformanceCounterFrequencyInHz|1000000|UINT32 |0xC > + gEmbeddedTokenSpaceGuid.PcdEmbeddedFdPerformanceCounterPeriodInNanoseconds|1000|UINT32 |0xD These would need to be defined in EmbeddedPkg.dec. Can't hijack other packages' namespace. / Leif > + > + # > + # USB EHCI Controller > + # > + giMX6TokenSpaceGuid.PcdEHCIBase|0x02184000|UINT32|0xE > + giMX6TokenSpaceGuid.PcdEHCILength|0x4000|UINT32|0xF > + giMX6TokenSpaceGuid.PcdIsUsbPortOTG|TRUE|BOOLEAN|0x10 > + giMX6TokenSpaceGuid.PcdUSBOTGBase|0x02184000|UINT32|0x11 > + > + # > + # ARM System Reset Controller (SRC) > + # > + giMX6TokenSpaceGuid.PcdSrcBase|0x020D8000|UINT32|0x2B > + > + # > + # PCIE > + # > + # PCI Host config space is fixed at 0x01FFC000. The memory range from > + # 0x01000000 - 0x01FFBFFF is assigned for PCIe. The memory layout defined > + # by the boot loader is as below > + # > + # PCIe Device Config Space : 0x01F00000 - 0x01F80000 > + # PCIe IO (unsupported) : 0x01100000 - 0x011FFFFF > + # PCIe Memory : 0x01200000 - 0x012FFFFF > + # > + giMX6TokenSpaceGuid.PcdPcieDeviceConfigBase|0x01F00000|UINT32|0x2C > + giMX6TokenSpaceGuid.PcdPcieDeviceConfigSize|0x00080000|UINT32|0x2D > + giMX6TokenSpaceGuid.PcdPcieHostConfigBase|0x01FFC000|UINT32|0x2E > + giMX6TokenSpaceGuid.PcdPcieIOBase|0x00000000|UINT32|0x2F > + giMX6TokenSpaceGuid.PcdPcieIOSize|0x00000000|UINT32|0x30 > + giMX6TokenSpaceGuid.PcdPciMemoryBase|0x01100000|UINT32|0x31 > + giMX6TokenSpaceGuid.PcdPciMemorySize|0x00D00000|UINT32|0x32 > + giMX6TokenSpaceGuid.PcdPciPrefetchMemoryBase|0x00000000|UINT32|0x33 > + giMX6TokenSpaceGuid.PcdPciPrefetchMemorySize|0x00000000|UINT32|0x34 > + giMX6TokenSpaceGuid.PcdPcieResetGpio|FALSE|BOOLEAN|0x35 > + giMX6TokenSpaceGuid.PcdPcieResetGpioBankNumber|0|UINT32|0x36 > + giMX6TokenSpaceGuid.PcdPcieResetGpioIoNumber|0|UINT32|0x37 > + > + # > + # SMBIOS Type1 > + # > + giMX6TokenSpaceGuid.PcdSystemFamily|L""|VOID*|0x38 > + giMX6TokenSpaceGuid.PcdSystemManufacturer|L""|VOID*|0x39 > + giMX6TokenSpaceGuid.PcdSystemProductName|L""|VOID*|0x3A > + giMX6TokenSpaceGuid.PcdSystemSkuNumber|L""|VOID*|0x3B > + giMX6TokenSpaceGuid.PcdSystemVersionNumber|L""|VOID*|0x3C > + giMX6TokenSpaceGuid.PcdSystemUuid|{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}|VOID*|0x3D > + > + # > + # SMBIOS Type2 > + # > + giMX6TokenSpaceGuid.PcdBoardAssetTag|L""|VOID*|0x3E > + giMX6TokenSpaceGuid.PcdBoardLocationInChassis|L""|VOID*|0x3F > + giMX6TokenSpaceGuid.PcdBoardManufacturer|L""|VOID*|0x40 > + giMX6TokenSpaceGuid.PcdBoardProductName|L""|VOID*|0x41 > + giMX6TokenSpaceGuid.PcdBoardVersionNumber|L""|VOID*|0x42 > + > + # > + # SMBIOS Type3 > + # > + giMX6TokenSpaceGuid.PcdChassisAssetTag|L""|VOID*|0x43 > + giMX6TokenSpaceGuid.PcdChassisManufacturer|L""|VOID*|0x44 > + giMX6TokenSpaceGuid.PcdChassisVersionNumber|L""|VOID*|0x45 > + > + # SMBIOS Type4 > + giMX6TokenSpaceGuid.PcdProcessorAssetTag|L""|VOID*|0x46 > + giMX6TokenSpaceGuid.PcdProcessorManufacturer|L""|VOID*|0x47 > + giMX6TokenSpaceGuid.PcdProcessorPartNumber|L""|VOID*|0x48 > + giMX6TokenSpaceGuid.PcdProcessorSocketDesignation|L""|VOID*|0x49 > + giMX6TokenSpaceGuid.PcdProcessorVersionNumber|L""|VOID*|0x4A > + > + # SMBIOS Type16 > + giMX6TokenSpaceGuid.PcdPhysicalMemoryMaximumCapacity|0x0|UINT32|0x4B > + > + # SMBIOS Type17 > + giMX6TokenSpaceGuid.PcdMemoryBankLocation|L""|VOID*|0x4C > + giMX6TokenSpaceGuid.PcdMemoryDeviceLocation|L""|VOID*|0x4D > + > + # SMBIOS Type19 > + giMX6TokenSpaceGuid.PcdMemoryEndAddress|0x0|UINT32|0x4E > + giMX6TokenSpaceGuid.PcdMemoryStartAddress|0x0|UINT32|0x4F > + > +[PcdsFeatureFlag.common] > + giMX6TokenSpaceGuid.PcdGpuEnable|FALSE|BOOLEAN|0x00001000 > + giMX6TokenSpaceGuid.PcdLvdsEnable|FALSE|BOOLEAN|0x00001001 > -- > 2.16.2.gvfs.1.33.gf5370f1 >