From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::442; helo=mail-wr1-x442.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id AF0552118D933 for ; Wed, 7 Nov 2018 05:13:07 -0800 (PST) Received: by mail-wr1-x442.google.com with SMTP id z16-v6so17366981wrv.2 for ; Wed, 07 Nov 2018 05:13:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=pbHc6AgoIX7hCRuO6uOZUFO9QoJeoWG+cJ6rs9cOVj4=; b=i/eMKKLFsX//Eb1jkcme9wB2e0MwH4BJyg5eIUu/50NywCrTf37lRsIERJlLEb+j4a ioO8unc23dynRZ0YR8UuhEzJbnnny1VgPn4pUL2lha8u11/O/7xkZDfJrpmKVoEspzBQ s3zgIkXoVfCeBfICpaE48diZ+xfdA+BFqHZf4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=pbHc6AgoIX7hCRuO6uOZUFO9QoJeoWG+cJ6rs9cOVj4=; b=roNY7UzUO3U5Nj3oCQ4A9QEqZU3/I+Gw53/ObZoiG6C4IVlGOi+6fu6vgTf3d9e8Zx 6ku7kyLUB59pUe+ppH8fuY/gYpkGYDHr5IL+dzzPv6Brau9tFhKoBGE2LHN4MRqTx4xo sXL6o6WjqyyFm3Te8sSqfVi0m1nglFUtNvTiL9L4QIkNyyLo1AOE/b07UZ9aNdb6FxZp zbrUPE53+5Xco+WOfqRX8og4NIiPBOEXGC7UZmoKSmCkH7I35A29ZNvYYjeFcrsxSaiw fw2vbHLiJAFodmLox3OnkDwyzo3rAIhQo5v+cB9wEfo4gFla5ZbFSQqRJBmD6Spvneuk 7u9A== X-Gm-Message-State: AGRZ1gLCDkgDgRNZNFrTk9G5QdUIOz994NuV8++IrHRy3CNSXU+GZ87X oIUGANR4I8j/z6kMYgxU6c7I1885Ybs= X-Google-Smtp-Source: AJdET5cDWZUTk1v//I0Sqzd9A4BFmiSAjsbupA+n13gM/JVvSMPSsuMJFlDTF6/PLSNoiMx0hud/xQ== X-Received: by 2002:a5d:660c:: with SMTP id n12-v6mr173285wru.19.1541596385190; Wed, 07 Nov 2018 05:13:05 -0800 (PST) Received: from localhost.localdomain (laubervilliers-657-1-83-120.w92-154.abo.wanadoo.fr. [92.154.90.120]) by smtp.gmail.com with ESMTPSA id e10-v6sm1690204wmg.23.2018.11.07.05.13.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 07 Nov 2018 05:13:04 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Cc: lersek@redhat.com, liming.gao@intel.com, michael.d.kinney@intel.com, marc.zyngier@arm.com, leif.lindholm@linaro.org, Ard Biesheuvel Date: Wed, 7 Nov 2018 14:13:01 +0100 Message-Id: <20181107131301.15852-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.19.1 MIME-Version: 1.0 Subject: [PATCH] MdePkg/BaseIoLibIntrinsicArmVirt ARM: avoid double word loads and stores X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 07 Nov 2018 13:13:08 -0000 Content-Transfer-Encoding: 8bit BaseIoLibIntrinsicArmVirt was created to prevent LTO from merging accesses to MMIO regions, resulting in instructions with multiple output registers that KVM on ARM cannot emulate (since the exception syndrome information that KVM relies on can only describe a single output register) However, using double word loads on ARM amounts to the same thing, and so code that relies on doing 64-bit MMIO to regions that are emulated under KVM (such as the GICv3 TYPER register) will still suffer from the original issue. So replace ldrd and strd with equivalent two instruction sequences. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S index 3ad22bd5706d..0d802d6928d6 100644 --- a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S +++ b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S @@ -125,7 +125,8 @@ ASM_PFX(MmioWrite32Internal): // @return The value read. // ASM_PFX(MmioRead64Internal): - ldrd r0, r1, [r0] + ldr r1, [r0, #4] + ldr r0, [r0] dmb bx lr @@ -141,5 +142,6 @@ ASM_PFX(MmioRead64Internal): // ASM_PFX(MmioWrite64Internal): dmb st - strd r2, r3, [r0] + str r2, [r0] + str r3, [r0, #4] bx lr -- 2.19.1