From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.115; helo=mga14.intel.com; envelope-from=eric.dong@intel.com; receiver=edk2-devel@lists.01.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id ED28421A07A80 for ; Wed, 7 Nov 2018 18:58:04 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Nov 2018 18:58:04 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,478,1534834800"; d="scan'208";a="272288226" Received: from ydong10-win10.ccr.corp.intel.com ([10.239.9.125]) by orsmga005.jf.intel.com with ESMTP; 07 Nov 2018 18:58:03 -0800 From: Eric Dong To: edk2-devel@lists.01.org Cc: Laszlo Ersek , Ruiyu Ni Date: Thu, 8 Nov 2018 10:58:00 +0800 Message-Id: <20181108025800.12112-3-eric.dong@intel.com> X-Mailer: git-send-email 2.15.0.windows.1 In-Reply-To: <20181108025800.12112-1-eric.dong@intel.com> References: <20181108025800.12112-1-eric.dong@intel.com> Subject: [Patch 2/2] UefiCpuPkg/PiSmmCpuDxeSmm: Separate semaphore container. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 08 Nov 2018 02:58:05 -0000 In current implementation, core level semaphore use same container with package level semaphore. This design will let the core level semaphore not works as expected in below case: 1. Feature A has CPU_FEATURE_CORE_BEFORE dependence with Feature B. 2. Feature C has CPU_FEATURE_PACKAGE_AFTER dependence with Feature B. in this case an core level semaphore will be add between A and B, and an package level semaphore will be add between B and C. For a CPU has one package, two cores and 4 threads. Execute like below: Thread 1 Thread 2 ..... Thread 4 ReleaseSemaph(1,2) -| WaitForSemaph(1(2)) -|<-----------------------These two are Core Semaph ReleaseSemaph(1,2) -| WaitForSemaph(2) -| <--- Core Semaph ReleaseSemaph (1,2,3,4) -| WaitForSemaph (1(4)) -| <---------------- Package Semaph ReleaseSemaph(3,4) WaitForSemaph(4(2)) <- Core Semaph In above case, for thread 4, when it executes a core semaphore, i will found WaitForSemaph(4(2)) is met because Thread 1 has execute a package semaphore and ReleaseSemaph(4) for it before. This is not an expect behavior. Thread 4 should wait for thread 3 to do this. Fix this issue by separate the semaphore container for core level and package level. Cc: Laszlo Ersek Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong --- UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c index a45e2dd3d7..65461485a4 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c @@ -41,9 +41,10 @@ typedef struct { // Flags used when program the register. // typedef struct { - volatile UINTN ConsoleLogLock; // Spinlock used to control console. - volatile UINTN MemoryMappedLock; // Spinlock used to program mmio - volatile UINT32 *SemaphoreCount; // Semaphore used to program semaphore. + volatile UINTN ConsoleLogLock; // Spinlock used to control console. + volatile UINTN MemoryMappedLock; // Spinlock used to program mmio + volatile UINT32 *CoreSemaphoreCount; // Semaphore used to program semaphore. + volatile UINT32 *PackageSemaphoreCount; // Semaphore used to program semaphore. } PROGRAM_CPU_REGISTER_FLAGS; // @@ -348,11 +349,12 @@ ProgramProcessorRegister ( ASSERT ( (ApLocation != NULL) && (CpuStatus->ValidCoreCountPerPackage != 0) && - (CpuFlags->SemaphoreCount) != NULL + (CpuFlags->CoreSemaphoreCount != NULL) && + (CpuFlags->PackageSemaphoreCount != NULL) ); - SemaphorePtr = CpuFlags->SemaphoreCount; switch (RegisterTableEntry->Value) { case CoreDepType: + SemaphorePtr = CpuFlags->CoreSemaphoreCount; // // Get Offset info for the first thread in the core which current thread belongs to. // @@ -373,6 +375,7 @@ ProgramProcessorRegister ( break; case PackageDepType: + SemaphorePtr = CpuFlags->PackageSemaphoreCount; ValidCoreCountPerPackage = (UINT32 *)(UINTN)CpuStatus->ValidCoreCountPerPackage; // // Get Offset info for the first thread in the package which current thread belongs to. @@ -1037,10 +1040,14 @@ GetAcpiCpuData ( ASSERT (mAcpiCpuData.ApLocation != 0); } if (CpuStatus->PackageCount != 0) { - mCpuFlags.SemaphoreCount = AllocateZeroPool ( + mCpuFlags.CoreSemaphoreCount = AllocateZeroPool ( sizeof (UINT32) * CpuStatus->PackageCount * CpuStatus->MaxCoreCount * CpuStatus->MaxThreadCount); - ASSERT (mCpuFlags.SemaphoreCount != NULL); + ASSERT (mCpuFlags.CoreSemaphoreCount != NULL); + mCpuFlags.PackageSemaphoreCount = AllocateZeroPool ( + sizeof (UINT32) * CpuStatus->PackageCount * + CpuStatus->MaxCoreCount * CpuStatus->MaxThreadCount); + ASSERT (mCpuFlags.PackageSemaphoreCount != NULL); } InitializeSpinLock((SPIN_LOCK*) &mCpuFlags.MemoryMappedLock); InitializeSpinLock((SPIN_LOCK*) &mCpuFlags.ConsoleLogLock); -- 2.15.0.windows.1