From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::442; helo=mail-wr1-x442.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id AC17C21180F30 for ; Thu, 8 Nov 2018 23:58:53 -0800 (PST) Received: by mail-wr1-x442.google.com with SMTP id u9-v6so871450wrr.0 for ; Thu, 08 Nov 2018 23:58:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=VI1dPZvRADSyZ0mUup/8INF4kG884o+YMV3l0nKKsCc=; b=k2Pg8Rxt/OjbmfX/k6xpAEMb3lYT5aZvEQexBZaay18VQNq7xORgOOk50Xsu+5Nosq ugiTOA1BrLJma7WMEE8o/J3j5Jioj9WDWqC3JEbrsRHDqnHkEB1xAEr9CgyA33eZU5rg eEpgfWiEiGXLMLVsaAS6wYDEafv2ug6Lzna8U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=VI1dPZvRADSyZ0mUup/8INF4kG884o+YMV3l0nKKsCc=; b=PKf7yl2mFJUKPjJ1p4p66Pdx6KztGpD8ykppx2BQ2SqGfirO3QnfJs0k7YR+ENBtV+ t9Wmc4s1SPfXsHHbkw89QDXOY95qjp/m22dFnsUbY+pAzeYWt8UlXvUywXlRN8sY6oV8 KjQzQB6VCh2tud+x4UjOgOUA0JNUOxkN+OA/qPwYimBGfK0o4xGKwSuRHeNk1/T0so1w PFch32W5x7/1+TEHehXYHrhIroG3/dXWSwgWZgYmcBBotv40o99QbNRi2zeuWPi97NOr Rhu43hz7fpmw50ubVNkidFo3yrlYWqzzYB2LLxkUyj+wQD5lp+G0FuXvO9qutRiioK59 VUwg== X-Gm-Message-State: AGRZ1gJAWigTCIBpO36lZe5fC6gUe2j2M2wK/ShWQUtMtBDknBuLF1wm gsqOMYSTiMIPQqnzRFfohXzCzKT3L94= X-Google-Smtp-Source: AJdET5dCzQ0WpM0txoFcVbjI4qpha0/w0dTV9fW4eMHmyGGaYxOjgw/qIM+qG7x1nXMloO4r8hOFSQ== X-Received: by 2002:adf:f382:: with SMTP id m2-v6mr6812674wro.111.1541750332058; Thu, 08 Nov 2018 23:58:52 -0800 (PST) Received: from harold.home ([2a01:cb1d:112:6f00:744a:cf78:9aaa:a66d]) by smtp.gmail.com with ESMTPSA id k5-v6sm9083165wre.82.2018.11.08.23.58.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Nov 2018 23:58:51 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Fri, 9 Nov 2018 08:58:48 +0100 Message-Id: <20181109075848.12029-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.19.1 MIME-Version: 1.0 Subject: [PATCH v2 edk2-platforms] Silicon/SynQuacerPciCpuIo2Dxe: fix PCIe I/O translation X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 09 Nov 2018 07:58:55 -0000 Content-Transfer-Encoding: 8bit Commit 9dd8190e4995 ("Silicon/SynQuacer: tweak PCI I/O windows for ACPI/Linux support") updated the min/max/offset definitions for the PCIe I/O resource windows on SynQuacer, and updated the read path of the platform's EfiCpuIo2 protocol implementation, but failed to update the write path as well, resulting in spurious errors if when attempting to write to PCIe I/O ports on PCIe RC #1, which uses translation for the I/O BAR window. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- v2: use helper function and temp vars Silicon/Socionext/SynQuacer/Drivers/SynQuacerPciCpuIo2Dxe/SynQuacerPciCpuIo2Dxe.c | 62 ++++++++++++-------- 1 file changed, 37 insertions(+), 26 deletions(-) diff --git a/Silicon/Socionext/SynQuacer/Drivers/SynQuacerPciCpuIo2Dxe/SynQuacerPciCpuIo2Dxe.c b/Silicon/Socionext/SynQuacer/Drivers/SynQuacerPciCpuIo2Dxe/SynQuacerPciCpuIo2Dxe.c index 736b20cd5129..049657231cab 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/SynQuacerPciCpuIo2Dxe/SynQuacerPciCpuIo2Dxe.c +++ b/Silicon/Socionext/SynQuacer/Drivers/SynQuacerPciCpuIo2Dxe/SynQuacerPciCpuIo2Dxe.c @@ -354,6 +354,37 @@ CpuMemoryServiceWrite ( return EFI_SUCCESS; } +STATIC +EFI_STATUS +TranslateIoAddress ( + IN OUT UINT64 *Address + ) +{ + UINT64 Start; + UINT64 End; + UINT64 Shift; + + Start = SYNQUACER_PCI_SEG0_PORTIO_MIN + SYNQUACER_PCI_SEG0_PORTIO_OFFSET; + End = SYNQUACER_PCI_SEG0_PORTIO_MAX + SYNQUACER_PCI_SEG0_PORTIO_OFFSET; + Shift = SYNQUACER_PCI_SEG0_PORTIO_MEMBASE - SYNQUACER_PCI_SEG0_PORTIO_OFFSET; + + if (*Address >= Start && *Address <= End) { + *Address += Shift; + return EFI_SUCCESS; + } + + Start = SYNQUACER_PCI_SEG1_PORTIO_MIN + SYNQUACER_PCI_SEG1_PORTIO_OFFSET; + End = SYNQUACER_PCI_SEG1_PORTIO_MAX + SYNQUACER_PCI_SEG1_PORTIO_OFFSET; + Shift = SYNQUACER_PCI_SEG1_PORTIO_MEMBASE - SYNQUACER_PCI_SEG1_PORTIO_OFFSET; + + if (*Address >= Start && *Address <= End) { + *Address += Shift; + return EFI_SUCCESS; + } + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; +} + /** Reads I/O registers. @@ -415,22 +445,9 @@ CpuIoServiceRead ( return Status; } - if ((Address >= (SYNQUACER_PCI_SEG0_PORTIO_MIN + - SYNQUACER_PCI_SEG0_PORTIO_OFFSET)) && - (Address <= (SYNQUACER_PCI_SEG0_PORTIO_MAX + - SYNQUACER_PCI_SEG0_PORTIO_OFFSET))) { - Address += SYNQUACER_PCI_SEG0_PORTIO_MEMBASE - - SYNQUACER_PCI_SEG0_PORTIO_OFFSET; - } else if ((Address >= (SYNQUACER_PCI_SEG1_PORTIO_MIN + - SYNQUACER_PCI_SEG1_PORTIO_OFFSET)) && - (Address <= (SYNQUACER_PCI_SEG1_PORTIO_MAX + - SYNQUACER_PCI_SEG1_PORTIO_OFFSET))) { - Address += SYNQUACER_PCI_SEG1_PORTIO_MEMBASE - - SYNQUACER_PCI_SEG1_PORTIO_OFFSET; - - } else { - ASSERT (FALSE); - return EFI_INVALID_PARAMETER; + Status = TranslateIoAddress (&Address); + if (EFI_ERROR (Status)) { + return Status; } // @@ -518,16 +535,9 @@ CpuIoServiceWrite ( return Status; } - if ((Address >= SYNQUACER_PCI_SEG0_PORTIO_MIN) && - (Address <= SYNQUACER_PCI_SEG0_PORTIO_MAX)) { - Address += SYNQUACER_PCI_SEG0_PORTIO_MEMBASE; - } else if ((Address >= SYNQUACER_PCI_SEG1_PORTIO_MIN) && - (Address <= SYNQUACER_PCI_SEG1_PORTIO_MAX)) { - Address += SYNQUACER_PCI_SEG1_PORTIO_MEMBASE; - - } else { - ASSERT (FALSE); - return EFI_INVALID_PARAMETER; + Status = TranslateIoAddress (&Address); + if (EFI_ERROR (Status)) { + return Status; } // -- 2.19.1