From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::444; helo=mail-wr1-x444.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 0D1172118EF42 for ; Tue, 13 Nov 2018 17:05:47 -0800 (PST) Received: by mail-wr1-x444.google.com with SMTP id b13so15356500wrx.6 for ; Tue, 13 Nov 2018 17:05:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=4QfhhjQhT9HKDxY5XaFhUyvd5LB5qbHlWGpNX+kwS38=; b=iq6ZOP/zYuKBPjQLomMSWjYIiLqTHAPuIRKa6zmJtWOE5eL6VjdP4FsItx8BazKDZG c4jMjYd1Q066K1+dCDPe5jqrJiPYxn9gxqPCy9m0Zq6XVrDnqh4BSFBlokjNXijcr84g VWHaNuDPDROL1zX/uebEsuYw7uOV2vBzYQeXk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=4QfhhjQhT9HKDxY5XaFhUyvd5LB5qbHlWGpNX+kwS38=; b=pw6IR8uFOPpsnw91pyNQcDf/48u3yihRtGnLlowAv/pOVzmjRol0qr38E/CNJzNbwd GW8DrIq+zdsVwBBPtUeDHCl2yZRTk2dOM4fR92C+kASKGcCA9sDGEUq631kuS1LtZXY/ C5s47IV9jqD0kiHcK6uTB/L7/6tb71yRNa65vvkYkCyibXGNp06UIng3d14k8iQU0fSb rlPmCyiwtzwnS8wkYxZ+XdJpbT1rCsHmJ0BADSlE3Y03a8P9Z3DE4hi6iNl2UOQIpJWh dY66QkHyJBQmIqI5661DPc586XbDEuA1+D5EEmOHNXhBH0Vc48JFxQRZGjSx+mnTWZ03 0sLw== X-Gm-Message-State: AGRZ1gL/GTKqL3E5yggGlhpnq65icfNcDvfYzenWHfiy04muo74xVn8C WNRVYfpV8ZVzqTtp+V4NNGXI4g== X-Google-Smtp-Source: AJdET5eXhj+JwLrWR/iPzkWCYaMgDizgy5HG7/vsmTwKRbjbpz0wUUChWd7Jrtbx2zHX4h7NSkwrmA== X-Received: by 2002:a5d:63cf:: with SMTP id c15-v6mr7188703wrw.221.1542157546284; Tue, 13 Nov 2018 17:05:46 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id v189-v6sm14398894wmd.40.2018.11.13.17.05.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 13 Nov 2018 17:05:45 -0800 (PST) Date: Wed, 14 Nov 2018 01:05:43 +0000 From: Leif Lindholm To: Ming Huang Cc: linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org, ard.biesheuvel@linaro.org, michael.d.kinney@intel.com, lersek@redhat.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, john.garry@huawei.com, xinliang.liu@linaro.org, zhangfeng56@huawei.com, Prasanth Pulla Message-ID: <20181114010543.vdrerefiijuec4y5@bivouac.eciton.net> References: <20181029035111.53262-1-ming.huang@linaro.org> <20181029035111.53262-5-ming.huang@linaro.org> MIME-Version: 1.0 In-Reply-To: <20181029035111.53262-5-ming.huang@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-non-osi v1 4/4] Hisilicon/D06: Fix SBSA PE-15 failed issue X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 14 Nov 2018 01:05:48 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline +Prasanth On Mon, Oct 29, 2018 at 11:51:11AM +0800, Ming Huang wrote: > PE test case 15 flow: > Primary core(cacheable shareable) and slave cores(non-cacheable) > access the same memory area for communication. > For each slave core{ > 1 Turn on slave core; > 2 run the payload function; > 3 Write result in memory to notify primary core and follow > clean and invalid instruction; clean and invalidate > 4 Slave core turn off itself; > } > The result in DDR may rewrite by cache data. The essence of > this problem is that primary core and slave core access the > same area with different cache attribute. > Configure L3T register to fix this issue; Does this change have any performance implications? Prasanth: would PE test 15 not be _expected_ to fail if primary and secondary cores access the buffers with different cachability attributes? > Build commit informations: > edk2:53caffc33b6 > edk2-platforms:d4d7e39886a > HwPgk:6e91ea20fda HwPkg. / Leif > TrustedFirmware:5888a78d43c > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ming Huang > --- > Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi | Bin 230784 -> 230816 bytes > 1 file changed, 0 insertions(+), 0 deletions(-) > > diff --git a/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi b/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi > index 8b6d740..b5aa0aa 100644 > Binary files a/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi and b/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi differ > -- > 2.18.0 >