From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::441; helo=mail-wr1-x441.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr1-x441.google.com (mail-wr1-x441.google.com [IPv6:2a00:1450:4864:20::441]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id EA4AF2118FF03 for ; Tue, 13 Nov 2018 17:10:48 -0800 (PST) Received: by mail-wr1-x441.google.com with SMTP id y3-v6so15368175wrh.10 for ; Tue, 13 Nov 2018 17:10:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=kJd9xxkoaFQGbETKATAp6/NQeVhR3EE85grxtAeIzWw=; b=bjN0UxWeTdBpJzmE1A/CW6IlVjFC23JvXi0ZAKaEkBBk13peoljSrP6OHRt60NAZVH qoWsZUJhCD3tnSAmO08h4xhH6YNZSpp1OqVuUqOf5qVREFFx+56AhpPdQWIgqQ1bsHHp Es9W9NSbQgBlCd4v6MOrdnt3HznHgDEwwQUd0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=kJd9xxkoaFQGbETKATAp6/NQeVhR3EE85grxtAeIzWw=; b=RvA6brkxf8z4CtLUUOa9oZu78q75TjTx2Xt0lKFbipIBdamhtBOUGRGJJcQgNrPNpx UC13HxOdHwMpBHQnetxBCGmZXbKGC8yHdnUDtBemzPysYmwU+tmNZhD4bC66clTgIoj1 Lf0UD7GTaRSKPFrLtfNCv3wgI8SLTGHhGLKeS543zgMpkDloS5pOh1HAQ54XFzR4ZZ68 bIQyKwTWF1ZkmsNzXu8ZVnf1fxE+w1EAW0CuoHj25NABm9p0tIhqD8vyuOGLnWNqvT7G WuP9CoFHh2DIk+cbP/gFU6HY3FVW9QK4L6dD6PX1DMnJNhQpUwQ2jYazjL/0EtF6MOJR EDQw== X-Gm-Message-State: AGRZ1gJuuUh7As05F5Pqai239QkV42zNZUagCjIMc6BqBo++fxv5Mb+B 6STt61RIQB6cbyHpEeKLmFyiSw== X-Google-Smtp-Source: AJdET5c7s84qJEojiR45XeeEVW506RIDfVoElDiN3iAvfxsLhdwt/11xagKlNIBKfd7xLJbngctJ9w== X-Received: by 2002:adf:f542:: with SMTP id j2-v6mr6748087wrp.70.1542157846903; Tue, 13 Nov 2018 17:10:46 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id k15sm6231196wru.8.2018.11.13.17.10.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 13 Nov 2018 17:10:46 -0800 (PST) Date: Wed, 14 Nov 2018 01:10:44 +0000 From: Leif Lindholm To: Marcin Wojtas Cc: edk2-devel@lists.01.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, jsd@semihalf.com, jaz@semihalf.com, kostap@marvell.com Message-ID: <20181114011044.inajftqy7qmfq7n3@bivouac.eciton.net> References: <1540000661-1956-1-git-send-email-mw@semihalf.com> <1540000661-1956-2-git-send-email-mw@semihalf.com> MIME-Version: 1.0 In-Reply-To: <1540000661-1956-2-git-send-email-mw@semihalf.com> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [platforms: PATCH 01/12] Marvell/Library: ArmadaSoCDescLib: Add GPIO information X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 14 Nov 2018 01:10:49 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Sat, Oct 20, 2018 at 03:57:30AM +0200, Marcin Wojtas wrote: > This patch introduces new library callback (ArmadaSoCDescGpioGet ()), > which dynamically allocates and fills MV_SOC_GPIO_DESC structure with > the SoC description of GPIO controllers. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Marcin Wojtas > --- > Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h | 10 +++++ > Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h | 15 ++++++++ > Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c | 39 ++++++++++++++++++++ > 3 files changed, 64 insertions(+) > > diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h > index c14b985..85dd67c 100644 > --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h > +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h > @@ -22,6 +22,7 @@ > // Common macros > // > #define MV_SOC_CP_BASE(Cp) (0xF2000000 + ((Cp) * 0x2000000)) > +#define MV_SOC_AP_COUNT 1 I think all of my comments on this patch can be summarised as "what is an AP in this context"? The term either needs explicit documenting, or expansion in the macro names such that documentation is not required. / Leif > > // > // Platform description of AHCI controllers > @@ -38,6 +39,15 @@ > #define MV_SOC_COMPHY_MUX_BITS 4 > > // > +// Platform description of GPIO controllers > +// > +#define MV_SOC_AP_GPIO_BASE 0xF06F5040 > +#define MV_SOC_AP_GPIO_PIN_COUNT 20 > +#define MV_SOC_GPIO_PER_CP_COUNT 2 > +#define MV_SOC_CP_GPIO_BASE(Gpio) (0x440100 + ((Gpio) * 0x40)) > +#define MV_SOC_CP_GPIO_PIN_COUNT(Gpio) ((Gpio) == 0 ? 32 : 31) > + > +// > // Platform description of I2C controllers > // > #define MV_SOC_I2C_PER_CP_COUNT 2 > diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h > index cdfb51b..f3d4f80 100644 > --- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h > +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h > @@ -46,6 +46,21 @@ ArmadaSoCDescCpBaseGet ( > ); > > // > +// GPIO devices description template definition > +// > +typedef struct { > + UINTN GpioBaseAddress; > + UINTN GpioPinCount; > +} MV_SOC_GPIO_DESC; > + > +EFI_STATUS > +EFIAPI > +ArmadaSoCDescGpioGet ( > + IN OUT MV_SOC_GPIO_DESC **GpioDesc, > + IN OUT UINTN *DescCount > + ); > + > +// > // I2C > // > typedef struct { > diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c > index 6902fda..7db4ec7 100644 > --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c > +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c > @@ -74,6 +74,45 @@ ArmadaSoCDescCpBaseGet ( > > EFI_STATUS > EFIAPI > +ArmadaSoCDescGpioGet ( > + IN OUT MV_SOC_GPIO_DESC **GpioDesc, > + IN OUT UINTN *DescCount > + ) > +{ > + MV_SOC_GPIO_DESC *Desc; > + UINTN CpCount, CpIndex, Index; > + > + CpCount = FixedPcdGet8 (PcdMaxCpCount); > + > + *DescCount = CpCount * MV_SOC_GPIO_PER_CP_COUNT + MV_SOC_AP_COUNT; > + Desc = AllocateZeroPool (*DescCount * sizeof (MV_SOC_GPIO_DESC)); > + if (Desc == NULL) { > + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); > + return EFI_OUT_OF_RESOURCES; > + } > + > + *GpioDesc = Desc; > + > + /* AP GPIO controller */ > + Desc->GpioBaseAddress = MV_SOC_AP_GPIO_BASE; > + Desc->GpioPinCount = MV_SOC_AP_GPIO_PIN_COUNT; > + Desc++; > + > + /* CP GPIO controllers */ > + for (CpIndex = 0; CpIndex < CpCount; CpIndex++) { > + for (Index = 0; Index < MV_SOC_GPIO_PER_CP_COUNT; Index++) { > + Desc->GpioBaseAddress = MV_SOC_CP_BASE (CpIndex) + > + MV_SOC_CP_GPIO_BASE (Index); > + Desc->GpioPinCount = MV_SOC_CP_GPIO_PIN_COUNT (Index); > + Desc++; > + } > + } > + > + return EFI_SUCCESS; > +} > + > +EFI_STATUS > +EFIAPI > ArmadaSoCDescI2cGet ( > IN OUT MV_SOC_I2C_DESC **I2cDesc, > IN OUT UINTN *DescCount > -- > 2.7.4 >