From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::642; helo=mail-pl1-x642.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pl1-x642.google.com (mail-pl1-x642.google.com [IPv6:2607:f8b0:4864:20::642]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1EBEF2118FF3C for ; Wed, 14 Nov 2018 11:27:27 -0800 (PST) Received: by mail-pl1-x642.google.com with SMTP id a14so3644015plm.12 for ; Wed, 14 Nov 2018 11:27:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=uXXuLjEJT7oMxQ98cAUDwXADclXtLGgK2BqGC+bHuxg=; b=YcBuZiMPBLKrFjjmO9UOCNVhj0IFoUFlpqJ9zrPOhNn+oQ0DGy6Zc615Id1X9NfZVe WlC91zLZ6SDKFPI++w1TRXt7uFnnNPNgmBvM44RFa4U5uDeLz7vqHrdnrzMtFaqBcDW5 B6h70xkJY26Nof69hOUfjWfnCo+AqQoRr4Xos= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=uXXuLjEJT7oMxQ98cAUDwXADclXtLGgK2BqGC+bHuxg=; b=aYhxg+gcbV+CMdPf2mC1WM9wt8bGf1BcQ9UhwLsM4oxcHmp+WvIHZRmpn9FTUjFPrA pzIVJqCh8pOjNLR1EJh2J3n5akMXcuvRnyf0iA7QCNawVQeI9ihGNvH1tgP5tgu9Y9BZ Xqs+GT/jF+xsDh7N/kEhpj0h5/2tCRr5JoiJ9v1gpbANBSjeU6C0LEzF/HuHKCu3z6Mr plCqK1ye7QUT5Vda07EOZsoiTtgNF+Hl79Gox7T4aWxB8PArV1QptohKf5OT24uvYMVk 6WqyHOBXUsldxrt+1SU6sAfiBlcYHvC5P/DMU0vWd2P9dJVotKf0VurEBPXdcB/QY+Wy klGg== X-Gm-Message-State: AGRZ1gLpWHgEI0qXVm9NRzMewbfaP4GJrlaFCpXHVWeMyhIL9mLr/Vta 5KQgR5xYNOgHz51ynha2JX4My9gzO7q8Xw== X-Google-Smtp-Source: AJdET5cCvZFo3ONfif0+pVrMbO0/DzD3rMQ4v0PPfGe6bpmGr5y65aNggrc3Hpjyb61e/O8qrAh5IA== X-Received: by 2002:a17:902:aa0a:: with SMTP id be10mr3146100plb.266.1542223647333; Wed, 14 Nov 2018 11:27:27 -0800 (PST) Received: from mba13.psav.com ([64.114.255.97]) by smtp.gmail.com with ESMTPSA id k38sm57375277pgb.33.2018.11.14.11.27.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 14 Nov 2018 11:27:26 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Wed, 14 Nov 2018 11:27:24 -0800 Message-Id: <20181114192724.27068-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.1 Subject: [PATCH] ArmPkg/ArmGicDxe ARM: fix encoding for GICv3 interrupt acknowledge X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 14 Nov 2018 19:27:28 -0000 Fix a typo in the 32-bit ARM version of the GICv3 driver, which uses the wrong system register encoding to access ICC_IAR1, and attempted to access ICC_IAR0 instead. This results in boot time hangs both under QEMU emulation and on real hardware. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.S | 2 +- ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.asm | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.S b/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.S index a72f3c865163..c308d2fa3e2f 100644 --- a/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.S +++ b/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.S @@ -66,7 +66,7 @@ ASM_FUNC(ArmGicV3EndOfInterrupt) // VOID // ); ASM_FUNC(ArmGicV3AcknowledgeInterrupt) - mrc p15, 0, r0, c12, c8, 0 //ICC_IAR1 + mrc p15, 0, r0, c12, c12, 0 //ICC_IAR1 bx lr //VOID diff --git a/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.asm b/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.asm index 4228fb59be54..222047d1ad43 100644 --- a/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.asm +++ b/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.asm @@ -66,7 +66,7 @@ // VOID // ); RVCT_ASM_EXPORT ArmGicV3AcknowledgeInterrupt - mrc p15, 0, r0, c12, c8, 0 //ICC_IAR1 + mrc p15, 0, r0, c12, c12, 0 //ICC_IAR1 bx lr //VOID -- 2.17.1