From: Ming Huang <ming.huang@linaro.org>
To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org,
edk2-devel@lists.01.org, graeme.gregory@linaro.org
Cc: ard.biesheuvel@linaro.org, michael.d.kinney@intel.com,
lersek@redhat.com, wanghuiqiang@huawei.com,
huangming23@huawei.com, zhangjinsong2@huawei.com,
huangdaode@hisilicon.com, john.garry@huawei.com,
xinliang.liu@linaro.org, zhangfeng56@huawei.com,
Ming Huang <ming.huang@linaro.org>
Subject: [PATCH edk2-platforms v2 01/15] Hisilicon/D0x: Modify IORT
Date: Fri, 16 Nov 2018 14:56:48 +0800 [thread overview]
Message-ID: <20181116065702.30559-2-ming.huang@linaro.org> (raw)
In-Reply-To: <20181116065702.30559-1-ming.huang@linaro.org>
Main gist is reformatting some of the IORT into a form the current
acpica-tools can handle, and also fix some bugfixes and closing
of comment blocks.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <ming.huang@linaro.org>
Reported-by: Al Stone <ahs3@redhat.com>
---
Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl | 24 +++++---
Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl | 64 ++++++++++++--------
Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Iort.asl | 34 ++++-------
Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620IortNoSmmu.asl | 6 +-
4 files changed, 71 insertions(+), 57 deletions(-)
diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl
index 929548514934..bb70dcd0c443 100644
--- a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl
+++ b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl
@@ -282,11 +282,11 @@
/* RC 0 */
[0001] Type : 02
-[0002] Length : 0034
-[0001] Revision : 00
+[0002] Length : 0038
+[0001] Revision : 01
[0004] Reserved : 00000000
[0004] Mapping Count : 00000001
-[0004] Mapping Offset : 00000020
+[0004] Mapping Offset : 00000024
[0008] Memory Properties : [IORT Memory Access Properties]
[0004] Cache Coherency : 00000001
@@ -301,6 +301,8 @@
Device Attribute : 0
[0004] ATS Attribute : 00000000
[0004] PCI Segment Number : 00000000
+ Memory Size Limit : 00
+ Reserved : 00000000
[0004] Input base : 00000000
[0004] ID Count : 00002000
@@ -311,11 +313,11 @@
/* RC 1 */
[0001] Type : 02
-[0002] Length : 0034
-[0001] Revision : 00
+[0002] Length : 0038
+[0001] Revision : 01
[0004] Reserved : 00000000
[0004] Mapping Count : 00000001
-[0004] Mapping Offset : 00000020
+[0004] Mapping Offset : 00000024
[0008] Memory Properties : [IORT Memory Access Properties]
[0004] Cache Coherency : 00000001
@@ -330,6 +332,8 @@
Device Attribute : 0
[0004] ATS Attribute : 00000000
[0004] PCI Segment Number : 00000001
+ Memory Size Limit : 00
+ Reserved : 00000000
[0004] Input base : 0000e000
[0004] ID Count : 00002000
@@ -340,11 +344,11 @@
/* RC 2 */
[0001] Type : 02
-[0002] Length : 0034
-[0001] Revision : 00
+[0002] Length : 0038
+[0001] Revision : 01
[0004] Reserved : 00000000
[0004] Mapping Count : 00000001
-[0004] Mapping Offset : 00000020
+[0004] Mapping Offset : 00000024
[0008] Memory Properties : [IORT Memory Access Properties]
[0004] Cache Coherency : 00000001
@@ -359,6 +363,8 @@
Device Attribute : 0
[0004] ATS Attribute : 00000000
[0004] PCI Segment Number : 00000002
+ Memory Size Limit : 00
+ Reserved : 00000000
[0004] Input base : 00008000
[0004] ID Count : 00002000
diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl
index 9955f6dbeb78..b64fcb4c7891 100644
--- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl
+++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl
@@ -392,11 +392,11 @@
/*1P NA PCIe2 */
[0001] Type : 02
-[0002] Length : 0034
-[0001] Revision : 00
+[0002] Length : 0038
+[0001] Revision : 01
[0004] Reserved : 00000000
[0004] Mapping Count : 00000001
-[0004] Mapping Offset : 00000020
+[0004] Mapping Offset : 00000024
[0008] Memory Properties : [IORT Memory Access Properties]
[0004] Cache Coherency : 00000001
@@ -411,6 +411,8 @@
Device Attribute : 0
[0004] ATS Attribute : 00000000
[0004] PCI Segment Number : 00000002
+ Memory Size Limit : 00
+ Reserved : 00000000
[0004] Input base : 0000f800
[0004] ID Count : 00000800
@@ -420,11 +422,11 @@
Single Mapping : 0
/* 1P NB PCIe0 */
[0001] Type : 02
-[0002] Length : 0034
-[0001] Revision : 00
+[0002] Length : 0038
+[0001] Revision : 01
[0004] Reserved : 00000000
[0004] Mapping Count : 00000001
-[0004] Mapping Offset : 00000020
+[0004] Mapping Offset : 00000024
[0008] Memory Properties : [IORT Memory Access Properties]
[0004] Cache Coherency : 00000001
@@ -439,6 +441,8 @@
Device Attribute : 0
[0004] ATS Attribute : 00000000
[0004] PCI Segment Number : 00000004
+ Memory Size Limit : 00
+ Reserved : 00000000
[0004] Input base : 00008800
[0004] ID Count : 00000800
@@ -449,11 +453,11 @@
/* 1P NB PCIe1 */
[0001] Type : 02
-[0002] Length : 0034
-[0001] Revision : 00
+[0002] Length : 0038
+[0001] Revision : 01
[0004] Reserved : 00000000
[0004] Mapping Count : 00000001
-[0004] Mapping Offset : 00000020
+[0004] Mapping Offset : 00000024
[0008] Memory Properties : [IORT Memory Access Properties]
[0004] Cache Coherency : 00000001
@@ -468,6 +472,8 @@
Device Attribute : 0
[0004] ATS Attribute : 00000000
[0004] PCI Segment Number : 00000005
+ Memory Size Limit : 00
+ Reserved : 00000000
[0004] Input base : 00007800
[0004] ID Count : 00000800
@@ -478,11 +484,11 @@
/* 1P NB PCIe2 */
[0001] Type : 02
-[0002] Length : 0034
-[0001] Revision : 00
+[0002] Length : 0038
+[0001] Revision : 01
[0004] Reserved : 00000000
[0004] Mapping Count : 00000001
-[0004] Mapping Offset : 00000020
+[0004] Mapping Offset : 00000024
[0008] Memory Properties : [IORT Memory Access Properties]
[0004] Cache Coherency : 00000001
@@ -497,6 +503,8 @@
Device Attribute : 0
[0004] ATS Attribute : 00000000
[0004] PCI Segment Number : 00000006
+ Memory Size Limit : 00
+ Reserved : 00000000
[0004] Input base : 0000c000
[0004] ID Count : 00000800
@@ -506,11 +514,11 @@
Single Mapping : 0
/* 1P NB PCIe3 */
[0001] Type : 02
-[0002] Length : 0034
-[0001] Revision : 00
+[0002] Length : 0038
+[0001] Revision : 01
[0004] Reserved : 00000000
[0004] Mapping Count : 00000001
-[0004] Mapping Offset : 00000020
+[0004] Mapping Offset : 00000024
[0008] Memory Properties : [IORT Memory Access Properties]
[0004] Cache Coherency : 00000001
@@ -525,6 +533,8 @@
Device Attribute : 0
[0004] ATS Attribute : 00000000
[0004] PCI Segment Number : 00000007
+ Memory Size Limit : 00
+ Reserved : 00000000
[0004] Input base : 00009000
[0004] ID Count : 00000800
@@ -534,11 +544,11 @@
Single Mapping : 0
/* 2P NA PCIe2*/
[0001] Type : 02
-[0002] Length : 0034
-[0001] Revision : 00
+[0002] Length : 0038
+[0001] Revision : 01
[0004] Reserved : 00000000
[0004] Mapping Count : 00000001
-[0004] Mapping Offset : 00000020
+[0004] Mapping Offset : 00000024
[0008] Memory Properties : [IORT Memory Access Properties]
[0004] Cache Coherency : 00000001
@@ -553,6 +563,8 @@
Device Attribute : 0
[0004] ATS Attribute : 00000000
[0004] PCI Segment Number : 0000000a
+ Memory Size Limit : 00
+ Reserved : 00000000
[0004] Input base : 00001000
[0004] ID Count : 00001000
@@ -563,11 +575,11 @@
/* 2P NB PCIe0*/
[0001] Type : 02
-[0002] Length : 0034
-[0001] Revision : 00
+[0002] Length : 0038
+[0001] Revision : 01
[0004] Reserved : 00000000
[0004] Mapping Count : 00000001
-[0004] Mapping Offset : 00000020
+[0004] Mapping Offset : 00000024
[0008] Memory Properties : [IORT Memory Access Properties]
[0004] Cache Coherency : 00000001
@@ -582,6 +594,8 @@
Device Attribute : 0
[0004] ATS Attribute : 00000000
[0004] PCI Segment Number : 0000000c
+ Memory Size Limit : 00
+ Reserved : 00000000
[0004] Input base : 00002000
[0004] ID Count : 00001000
@@ -592,11 +606,11 @@
/* 2P NB PCIe1*/
[0001] Type : 02
-[0002] Length : 0034
-[0001] Revision : 00
+[0002] Length : 0038
+[0001] Revision : 01
[0004] Reserved : 00000000
[0004] Mapping Count : 00000001
-[0004] Mapping Offset : 00000020
+[0004] Mapping Offset : 00000024
[0008] Memory Properties : [IORT Memory Access Properties]
[0004] Cache Coherency : 00000001
@@ -611,6 +625,8 @@
Device Attribute : 0
[0004] ATS Attribute : 00000000
[0004] PCI Segment Number : 0000000d
+ Memory Size Limit : 00
+ Reserved : 00000000
[0004] Input base : 00003000
[0004] ID Count : 00001000
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Iort.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Iort.asl
index 33b5d5250bd4..08e15c17bf40 100644
--- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Iort.asl
+++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Iort.asl
@@ -53,9 +53,7 @@
[0004] PRI Interrupt : 00000000
[0004] GERR Interrupt : 00000000
[0004] Sync Interrupt : 00000000
-[0001] Proximity Domain : 01
-[0001] Reserved : 00
-[0002] Reserved : 0000
+[0004] Proximity Domain : 00000001
[0004] DeviceID mapping index : 00000002
[0004] Input base : 00000000
@@ -99,9 +97,7 @@
[0004] PRI Interrupt : 00000000
[0004] GERR Interrupt : 00000000
[0004] Sync Interrupt : 00000000
-[0001] Proximity Domain : 01
-[0001] Reserved : 00
-[0002] Reserved : 0000
+[0004] Proximity Domain : 00000001
[0004] DeviceID mapping index : 0001
[0004] Input base : 00007c00
@@ -139,9 +135,7 @@
[0004] PRI Interrupt : 00000000
[0004] GERR Interrupt : 00000000
[0004] Sync Interrupt : 00000000
-[0001] Proximity Domain : 01
-[0001] Reserved : 00
-[0002] Reserved : 0000
+[0004] Proximity Domain : 00000001
[0004] DeviceID mapping index : 00000001
[0004] Input base : 00007400
@@ -179,9 +173,7 @@
[0004] PRI Interrupt : 00000000
[0004] GERR Interrupt : 00000000
[0004] Sync Interrupt : 00000000
-[0001] Proximity Domain : 03
-[0001] Reserved : 00
-[0002] Reserved : 0000
+[0004] Proximity Domain : 00000003
[0004] DeviceID mapping index : 00000002
[0004] Input base : 00008000
@@ -225,9 +217,7 @@
[0004] PRI Interrupt : 00000000
[0004] GERR Interrupt : 00000000
[0004] Sync Interrupt : 00000000
-[0001] Proximity Domain : 03
-[0001] Reserved : 00
-[0002] Reserved : 0000
+[0004] Proximity Domain : 00000003
[0004] DeviceID mapping index : 0001
[0004] Input base : 0000BC00
@@ -265,9 +255,7 @@
[0004] PRI Interrupt : 00000000
[0004] GERR Interrupt : 00000000
[0004] Sync Interrupt : 00000000
-[0001] Proximity Domain : 03
-[0001] Reserved : 00
-[0002] Reserved : 0000
+[0004] Proximity Domain : 00000003
[0004] DeviceID mapping index : 00000001
[0004] Input base : 0000B400
@@ -287,10 +275,10 @@
/*0x2FC RC 0 */
[0001] Type : 02
[0002] Length : 00A0
-[0001] Revision : 00
+[0001] Revision : 01
[0004] Reserved : 00000000
[0004] Mapping Count : 0000000C
-[0004] Mapping Offset : 00000028
+[0004] Mapping Offset : 00000024
[0008] Memory Properties : [IORT Memory Access Properties]
[0004] Cache Coherency : 00000001
@@ -305,6 +293,8 @@
Device Attribute : 0
[0004] ATS Attribute : 00000000
[0004] PCI Segment Number : 00000000 // should match with above MCFG
+ Memory Size Limit : 00
+ Reserved : 00000000
/* BDF of pcie host 0 -> stream ID of pcie 0/1 SMMU */
[0004] Input base : 00000000
@@ -322,7 +312,7 @@
[0004] Flags (decoded below) : 00000000
Single Mapping : 1
-/* host2 and host3 should no open smmu for chips smmu bug *
+/* host2 and host3 should no open smmu for chips smmu bug */
/* BDF of pcie host 2 -> stream ID of pcie 0/1 ITS */
[0004] Input base : 00007a00
[0004] ID Count : 00000100 // the number of IDs in range
@@ -371,7 +361,7 @@
[0004] Flags (decoded below) : 00000000
Single Mapping : 1
-/* host8 and host9 should no open smmu for chips smmu bug *
+/* host8 and host9 should no open smmu for chips smmu bug */
/* BDF of pcie host 8 -> stream ID of pcie ITS */
[0004] Input base : 0000BA00
[0004] ID Count : 00000100 // the number of IDs in range
diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620IortNoSmmu.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620IortNoSmmu.asl
index 63d11b83ebed..c9e1cbd6830d 100644
--- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620IortNoSmmu.asl
+++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620IortNoSmmu.asl
@@ -36,10 +36,10 @@
/*0x4c RC 0 */
[0001] Type : 02
[0002] Length : 00A0
-[0001] Revision : 00
+[0001] Revision : 01
[0004] Reserved : 00000000
[0004] Mapping Count : 0000000C
-[0004] Mapping Offset : 00000028
+[0004] Mapping Offset : 00000024
[0008] Memory Properties : [IORT Memory Access Properties]
[0004] Cache Coherency : 00000001
@@ -54,6 +54,8 @@
Device Attribute : 0
[0004] ATS Attribute : 00000000
[0004] PCI Segment Number : 00000000 // should match with above MCFG
+ Memory Size Limit : 00
+ Reserved : 00000000
/* BDF of pcie host 0 -> stream ID of pcie 0/1 SMMU */
[0004] Input base : 00000000
--
2.9.5
next prev parent reply other threads:[~2018-11-16 6:57 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-16 6:56 [PATCH edk2-platforms v2 00/15] Fix D06 SBSA/SBBR issue and improve Ming Huang
2018-11-16 6:56 ` Ming Huang [this message]
2018-11-16 6:56 ` [PATCH edk2-platforms v2 02/15] Silicon/Hisilicon/D06: Add watchdog to GTDT Ming Huang
2018-11-16 6:56 ` [PATCH edk2-platforms v2 03/15] Silicon/Hisilicon/D06: Drop _CID for fwts issue Ming Huang
2018-11-16 6:56 ` [PATCH edk2-platforms v2 04/15] Silicon/Hisilicon/D06: Fix fwts issue in Dbg2 Ming Huang
2018-11-16 6:56 ` [PATCH edk2-platforms v2 05/15] Silicon/Hisilicon/D06: Fix fwts issue in FADT Ming Huang
2018-11-16 6:56 ` [PATCH edk2-platforms v2 06/15] Hisilicon/D06: Move some functions to OemMiscLib Ming Huang
2018-11-19 18:30 ` Leif Lindholm
2018-11-20 6:38 ` Ming Huang
2018-11-20 10:38 ` Leif Lindholm
2018-11-16 6:56 ` [PATCH edk2-platforms v2 07/15] Hisilicon/D0x: Fix secure boot bug in FlashFvbDxe Ming Huang
2018-11-19 18:13 ` Leif Lindholm
2018-11-20 6:42 ` Ming Huang
2018-11-19 18:19 ` Ard Biesheuvel
2018-11-20 6:44 ` Ming Huang
2018-11-16 6:56 ` [PATCH edk2-platforms v2 08/15] Silicon/Hisilicon/D06: Reserve ECAM resource in DSDT Ming Huang
2018-11-16 6:56 ` [PATCH edk2-platforms v2 09/15] Silicon/Hisilicon/D06: Modify GTDT timer flag Ming Huang
2018-11-16 6:56 ` [PATCH edk2-platforms v2 10/15] Hisilicon/D06: Modify Gic base Ming Huang
2018-11-19 18:20 ` Leif Lindholm
2018-11-20 6:55 ` Ming Huang
2018-11-20 10:40 ` Leif Lindholm
2018-11-16 6:56 ` [PATCH edk2-platforms v2 11/15] Silicon/Hisilicon/D06: Set TA as Node 0 for TA boot Ming Huang
2018-11-16 6:56 ` [PATCH edk2-platforms v2 12/15] Silicon/Hisilicon/D03: Drop _CID for fwts issue Ming Huang
2018-11-16 6:57 ` [PATCH edk2-platforms v2 13/15] Silicon/Hisilicon/D05: " Ming Huang
2018-11-16 6:57 ` [PATCH edk2-platforms v2 14/15] Hisilicon: Drop Pv660 source code Ming Huang
2018-11-16 6:57 ` [PATCH edk2-platforms v2 15/15] Hisilicon/D06: Correct HIDs/UIDs of PCI host bridges Ming Huang
2018-11-19 18:42 ` [PATCH edk2-platforms v2 00/15] Fix D06 SBSA/SBBR issue and improve Leif Lindholm
2018-11-20 7:02 ` Ming Huang
2018-11-20 10:32 ` Leif Lindholm
2018-11-20 12:42 ` Ming Huang
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