From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::342; helo=mail-wm1-x342.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7D93021A07A80 for ; Mon, 19 Nov 2018 10:42:55 -0800 (PST) Received: by mail-wm1-x342.google.com with SMTP id q26so6275634wmf.5 for ; Mon, 19 Nov 2018 10:42:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=FRj0NAom0fp4Ow1rv2niT+wH7/AwDJuT1W2Zy65b7Po=; b=ZxIwnOIy7iZNGHxSq99hnGY9BrsUPwvAE4b6SY1hRrDCZlzoAaazdUvf6y0lcL45+g 9mV/UIrjyF7gtWixfuzHhUqDl9WQNoKRLSww+aQJ9xDITe7FNdb0Pc2XssJUrGxuuBXh ZtU4jMwMIX2QP5BftwOSHIb3S2pBhUYSxnQA0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=FRj0NAom0fp4Ow1rv2niT+wH7/AwDJuT1W2Zy65b7Po=; b=to0P0MspmK9obw+oXqD4pf/1UZ8O0CjLFFyQie7v7ksoVv9iEkY0aaj5EUvGtrjelS cCVJ3/fauKQOqhmcAgZodcphRinJXhs6dcb5XtisPrOgrcfn2/WMokwSb85Vnf+3vBz3 LWliKsx9M0IczoCM4ZFGgZnABGwoLynzbHL+EqPqtz4K53ovxnB6NI7F7xK58bg9uyCQ 2Tp2cpJQ2ZqmETOpmtC+3J0Fxeq+bozjv8kn1gFE41gMrnnX1LkdE1Y/mOPoDP7eSIfX FWijz+fVHc8lNEd3pJmWKcHUJbCzIrMDRl2c/mPdy5UL+eU6Yh/7XAmakBe+AeArhVp/ vZcw== X-Gm-Message-State: AA+aEWZtOkQuL62n2hOFzcHBbuf1a7faL9A4FHOQgueGfIxBCOqDrzb6 YPSZ6EHI0C1SFdKkogbQpu4E7A== X-Google-Smtp-Source: AJdET5cqrnqGHmwRziehWA5TPfqIN6mRM1IaHv+tZO4VXFenCIvpRBDL3JJ0AHPYmueOxyBoSjrAFg== X-Received: by 2002:a1c:da82:: with SMTP id r124-v6mr7869785wmg.54.1542652973913; Mon, 19 Nov 2018 10:42:53 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id d5sm5087029wrx.22.2018.11.19.10.42.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 19 Nov 2018 10:42:53 -0800 (PST) Date: Mon, 19 Nov 2018 18:42:51 +0000 From: Leif Lindholm To: Ming Huang Cc: linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org, ard.biesheuvel@linaro.org, michael.d.kinney@intel.com, lersek@redhat.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, john.garry@huawei.com, xinliang.liu@linaro.org, zhangfeng56@huawei.com Message-ID: <20181119184251.rc3ld3iz7amqi6ey@bivouac.eciton.net> References: <20181116065702.30559-1-ming.huang@linaro.org> MIME-Version: 1.0 In-Reply-To: <20181116065702.30559-1-ming.huang@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms v2 00/15] Fix D06 SBSA/SBBR issue and improve X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 19 Nov 2018 18:42:56 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Nov 16, 2018 at 02:56:47PM +0800, Ming Huang wrote: > Main Change since v1: > 1. Add IORT patch; > 2. Add HIDs/UIDs bug for PciHostBridgeLib; > 3. Drop Pv660; > 4. Drop two patchs: > Modify for SBBR fwts SetTime_Func test case; > Fix SBBR-SCT AuthVar issue > > Code can also be found in github: > https://github.com/hisilicon/OpenPlatformPkg.git > branch: d06-acs-platforms-v2 > > > Ming Huang (15): > Hisilicon/D0x: Modify IORT > Silicon/Hisilicon/D06: Add watchdog to GTDT > Silicon/Hisilicon/D06: Drop _CID for fwts issue > Silicon/Hisilicon/D06: Fix fwts issue in Dbg2 > Silicon/Hisilicon/D06: Fix fwts issue in FADT > Hisilicon/D06: Move some functions to OemMiscLib > Hisilicon/D0x: Fix secure boot bug in FlashFvbDxe > Silicon/Hisilicon/D06: Reserve ECAM resource in DSDT > Silicon/Hisilicon/D06: Modify GTDT timer flag > Hisilicon/D06: Modify Gic base > Silicon/Hisilicon/D06: Set TA as Node 0 for TA boot > Silicon/Hisilicon/D03: Drop _CID for fwts issue > Silicon/Hisilicon/D05: Drop _CID for fwts issue > Hisilicon: Drop Pv660 source code > Hisilicon/D06: Correct HIDs/UIDs of PCI host bridges The following patches (in this order): Hisilicon: Drop Pv660 source code Hisilicon/D0x: Modify IORT Silicon/Hisilicon/D03: Drop _CID for fwts issue Silicon/Hisilicon/D05: Drop _CID for fwts issue Silicon/Hisilicon/D06: Drop _CID for fwts issue Silicon/Hisilicon/D06: Add watchdog to GTDT Silicon/Hisilicon/D06: Fix fwts issue in Dbg2 Silicon/Hisilicon/D06: Fix fwts issue in FADT Silicon/Hisilicon/D06: Reserve ECAM resource in DSDT Silicon/Hisilicon/D06: Modify GTDT timer flag Hisilicon/D06: Correct HIDs/UIDs of PCI host bridges Reviewed-by: Leif Lindholm Pushed as 46d3a977b9..ce4f7528ed. Please rebase on new master and address comments for v3. If you can merge Silicon/Hisilicon/D06: Set TA as Node 0 for TA boot and Hisilicon/D06: Modify Gic base as requested and get those sent out before I start work tomorrow, we are in pretty good shape for me to roll out an -rc1 tomorrow. (Which would be good, because I hope to have Wednesday-Friday as holiday :) If you can also address "Fix secure boot bug in FlashFvbDxe", that should be all remaining functional changes. FYI: I am now working against edk2 tag edk2-stable201811. / Leif > Silicon/Hisilicon/HisiPkg.dec | 1 + > Platform/Hisilicon/D03/D03.dsc | 5 + > Platform/Hisilicon/D05/D05.dsc | 5 + > Platform/Hisilicon/D06/D06.dsc | 7 +- > Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf | 2 + > Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf | 2 +- > Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf | 2 +- > Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.inf | 1 - > Silicon/Hisilicon/Pv660/Drivers/IoInitDxe/IoInitDxe.inf | 58 -- > Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitDxe.inf | 56 -- > Silicon/Hisilicon/Pv660/Drivers/SasInitDxe/SasV1Init.inf | 48 - > Silicon/Hisilicon/Pv660/Drivers/UnInstallAcpiTableDxe/UnInstallAcpiTable.inf | 57 -- > Silicon/Hisilicon/Pv660/Pv660AcpiTables/AcpiTables.inf | 60 -- > Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Platform.h | 2 +- > Silicon/Hisilicon/Include/Library/OemMiscLib.h | 9 + > Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClock.h | 4 - > Silicon/Hisilicon/Pv660/Drivers/IoInitDxe/Smmu.h | 36 - > Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInit.h | 93 -- > Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.h | 239 ----- > Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieKernelApi.h | 346 ------- > Silicon/Hisilicon/Pv660/Drivers/UnInstallAcpiTableDxe/UnInstallAcpiTable.h | 30 - > Silicon/Hisilicon/Pv660/Include/Library/SerdesLib.h | 120 --- > Silicon/Hisilicon/Pv660/Pv660AcpiTables/Pv660Platform.h | 48 - > Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c | 82 ++ > Platform/Hisilicon/D06/Library/PciHostBridgeLib/PciHostBridgeLib.c | 28 +- > Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c | 14 +- > Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.c | 90 +- > Silicon/Hisilicon/Pv660/Drivers/IoInitDxe/IoInitDxe.c | 94 -- > Silicon/Hisilicon/Pv660/Drivers/IoInitDxe/Smmu.c | 442 --------- > Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInit.c | 103 -- > Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.c | 1048 -------------------- > Silicon/Hisilicon/Pv660/Drivers/SasInitDxe/SasV1Init.c | 114 --- > Silicon/Hisilicon/Pv660/Drivers/UnInstallAcpiTableDxe/UnInstallAcpiTable.c | 119 --- > Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl | 24 +- > Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/Com.asl | 1 - > Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl | 8 - > Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl | 64 +- > Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Com.asl | 1 - > Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl | 13 - > Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Com.asl | 1 - > Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mbig.asl | 48 - > Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl | 36 +- > Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Fadt.aslc | 2 +- > Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Gtdt.aslc | 35 +- > Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Dbg2.aslc | 4 +- > Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Iort.asl | 40 +- > Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620IortNoSmmu.asl | 6 +- > Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Srat.aslc | 194 ++-- > Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/MadtHi1620.aslc | 2 +- > Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dbg2.aslc | 94 -- > Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/CPU.asl | 88 -- > Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl | 38 - > Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Ctl.asl | 38 - > Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl | 29 - > Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl | 956 ------------------ > Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Mbig.asl | 86 -- > Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Pci.asl | 181 ---- > Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Usb.asl | 136 --- > Silicon/Hisilicon/Pv660/Pv660AcpiTables/Facs.aslc | 67 -- > Silicon/Hisilicon/Pv660/Pv660AcpiTables/Fadt.aslc | 93 -- > Silicon/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc | 96 -- > Silicon/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl | 274 ----- > Silicon/Hisilicon/Pv660/Pv660AcpiTables/Madt.aslc | 130 --- > Silicon/Hisilicon/Pv660/Pv660AcpiTables/Mcfg.aslc | 80 -- > Silicon/Hisilicon/Pv660/Pv660AcpiTables/SASSSDT.ASL | 169 ---- > Silicon/Hisilicon/Pv660/Pv660AcpiTables/SATASSDT.ASL | 51 - > Silicon/Hisilicon/Pv660/Pv660AcpiTables/Spcr.aslc | 64 -- > 67 files changed, 361 insertions(+), 6153 deletions(-) > delete mode 100644 Silicon/Hisilicon/Pv660/Drivers/IoInitDxe/IoInitDxe.inf > delete mode 100644 Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitDxe.inf > delete mode 100644 Silicon/Hisilicon/Pv660/Drivers/SasInitDxe/SasV1Init.inf > delete mode 100644 Silicon/Hisilicon/Pv660/Drivers/UnInstallAcpiTableDxe/UnInstallAcpiTable.inf > delete mode 100644 Silicon/Hisilicon/Pv660/Pv660AcpiTables/AcpiTables.inf > delete mode 100644 Silicon/Hisilicon/Pv660/Drivers/IoInitDxe/Smmu.h > delete mode 100644 Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInit.h > delete mode 100644 Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.h > delete mode 100644 Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieKernelApi.h > delete mode 100644 Silicon/Hisilicon/Pv660/Drivers/UnInstallAcpiTableDxe/UnInstallAcpiTable.h > delete mode 100644 Silicon/Hisilicon/Pv660/Include/Library/SerdesLib.h > delete mode 100644 Silicon/Hisilicon/Pv660/Pv660AcpiTables/Pv660Platform.h > delete mode 100644 Silicon/Hisilicon/Pv660/Drivers/IoInitDxe/IoInitDxe.c > delete mode 100644 Silicon/Hisilicon/Pv660/Drivers/IoInitDxe/Smmu.c > delete mode 100644 Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInit.c > delete mode 100644 Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.c > delete mode 100644 Silicon/Hisilicon/Pv660/Drivers/SasInitDxe/SasV1Init.c > delete mode 100644 Silicon/Hisilicon/Pv660/Drivers/UnInstallAcpiTableDxe/UnInstallAcpiTable.c > delete mode 100644 Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dbg2.aslc > delete mode 100644 Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/CPU.asl > delete mode 100644 Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl > delete mode 100644 Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Ctl.asl > delete mode 100644 Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl > delete mode 100644 Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl > delete mode 100644 Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Mbig.asl > delete mode 100644 Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Pci.asl > delete mode 100644 Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Usb.asl > delete mode 100644 Silicon/Hisilicon/Pv660/Pv660AcpiTables/Facs.aslc > delete mode 100644 Silicon/Hisilicon/Pv660/Pv660AcpiTables/Fadt.aslc > delete mode 100644 Silicon/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc > delete mode 100644 Silicon/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl > delete mode 100644 Silicon/Hisilicon/Pv660/Pv660AcpiTables/Madt.aslc > delete mode 100644 Silicon/Hisilicon/Pv660/Pv660AcpiTables/Mcfg.aslc > delete mode 100644 Silicon/Hisilicon/Pv660/Pv660AcpiTables/SASSSDT.ASL > delete mode 100644 Silicon/Hisilicon/Pv660/Pv660AcpiTables/SATASSDT.ASL > delete mode 100644 Silicon/Hisilicon/Pv660/Pv660AcpiTables/Spcr.aslc > > -- > 2.9.5 >