From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::342; helo=mail-wm1-x342.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E78D921B02822 for ; Fri, 23 Nov 2018 04:14:46 -0800 (PST) Received: by mail-wm1-x342.google.com with SMTP id r11-v6so11681361wmb.2 for ; Fri, 23 Nov 2018 04:14:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4EcCUImUyi7GfJXvhW0Ur6xoXw7uWeXW6PpmJ1+BtZA=; b=bZW9MAgKVXavHp7eGE5QS4Zfm3L7ytoVX5O2rylHDmklMW88f+UeP9JdQWZsIBjN8q Yfgm6Ylk/bl6Oxcek5D3f5YHz4u8ilc5P+fPTH2YR9/BCYbQ1STUtQzdc/aNHnk08zHC R/yjDdAhUa5PneTVwYn9FM0gtSiSHvF/AuyvE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4EcCUImUyi7GfJXvhW0Ur6xoXw7uWeXW6PpmJ1+BtZA=; b=U0veQxj8b8GvUjjSJ6dgcjmjo4weIbrgM4RbrLTQzDVOErhyXLzN9jAb/mjvyobh8Z M+d3d3bmZrvMTifm5fBNU5L794VLvYmKTHwNF+gseaUlpkLK+u96C8zzHGwx4zoSh5BA wGaoVICe9nbDrtbbaEyMKoex3NTue7YpB7oWVDEGW4mgDQCC/ITO3I+x2GJbE1jGxnjz Kzg9Ald+FNXU7qfppgXgytdFefGxYPc6Jk2mB5hJTJXUta++RCWolfEmTJIX0fYZVzxy +0L9N3UpYSSoHYfXdnc8/K+rbu5ddmp+fs8x7k4eRfsPjjKPM1BoMY0BnzAljbA463Lv Kh5w== X-Gm-Message-State: AA+aEWbi7SW7WUkQz3GPzqVgWawoBILv/dJcTXRbMm4Sap70xX4doZAz T41t2Ub/FYvY48te/QY0d9sbin8RQSqfqQ== X-Google-Smtp-Source: AJdET5eJgfcfphK5JbOKMHPruTZ+DsN/v7OXgg0Pi4m4vJhyHXTGF053tSCz9Rh1VuCTp74/DwOCUQ== X-Received: by 2002:a1c:ee46:: with SMTP id m67mr12909616wmh.59.1542975285155; Fri, 23 Nov 2018 04:14:45 -0800 (PST) Received: from mba13.wifi.ns.nl (33.153.69.91.rev.sfr.net. [91.69.153.33]) by smtp.gmail.com with ESMTPSA id x79sm16469106wmd.42.2018.11.23.04.14.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Nov 2018 04:14:44 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Cc: Ard Biesheuvel , Laszlo Ersek , Leif Lindholm , Eric Auger , Andrew Jones , Philippe Mathieu-Daude , Julien Grall Date: Fri, 23 Nov 2018 13:14:27 +0100 Message-Id: <20181123121431.22353-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181123121431.22353-1-ard.biesheuvel@linaro.org> References: <20181123121431.22353-1-ard.biesheuvel@linaro.org> Subject: [PATCH 1/5] ArmPkg/ArmLib: add support for reading the max physical address space size X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 23 Nov 2018 12:14:47 -0000 Add a helper function that returns the maximum physical address space size as supported by the current CPU. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- ArmPkg/Include/Library/ArmLib.h | 6 ++++++ ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S | 16 ++++++++++++++++ ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S | 8 ++++++++ 3 files changed, 30 insertions(+) diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h index ffda50e9d767..9a804c15fdb6 100644 --- a/ArmPkg/Include/Library/ArmLib.h +++ b/ArmPkg/Include/Library/ArmLib.h @@ -733,4 +733,10 @@ ArmWriteCntvOff ( UINT64 Val ); +UINTN +EFIAPI +ArmGetPhysicalAddressBits ( + VOID + ); + #endif // __ARM_LIB__ diff --git a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S index 1ef2f61f5979..75ab8dade485 100644 --- a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S +++ b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S @@ -196,4 +196,20 @@ ASM_FUNC(ArmWriteSctlr) 3:msr sctlr_el3, x0 4:ret +ASM_FUNC(ArmGetPhysicalAddressBits) + mrs x0, id_aa64mmfr0_el1 + adr x1, .LPARanges + and x0, x0, #7 + ldrb w0, [x1, x0] + ret + +// +// Bits 0..2 of the AA64MFR0_EL1 system register encode the size of the +// physical address space support on this CPU: +// 0 == 32 bits, 1 == 36 bits, etc etc +// 6 and 7 are reserved +// +.LPARanges: + .byte 32, 36, 40, 42, 44, 48, -1, -1 + ASM_FUNCTION_REMOVE_IF_UNREFERENCED diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S index f2a517671f0a..f2f3c9a25991 100644 --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S +++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S @@ -165,4 +165,12 @@ ASM_FUNC(ArmWriteCpuActlr) isb bx lr +ASM_FUNC (ArmGetPhysicalAddressBits) + mrc p15, 0, r0, c0, c1, 4 // MMFR0 + and r0, r0, #0xf // VMSA [3:0] + cmp r0, #5 // >5 implies LPAE support + movlt r0, #32 // 32 bits if no LPAE + movge r0, #40 // 40 bits if LPAE + bx lr + ASM_FUNCTION_REMOVE_IF_UNREFERENCED -- 2.17.1