From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::444; helo=mail-wr1-x444.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 72B032119489A for ; Fri, 23 Nov 2018 04:14:48 -0800 (PST) Received: by mail-wr1-x444.google.com with SMTP id z5so7836995wrt.11 for ; Fri, 23 Nov 2018 04:14:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=apnpEQS6NK3xY1MjGrHYfNg1VjArbmfZ1KWaTVOYZXU=; b=ZtCgVz92w2AyfHi1zMFWDRebHLmgkdjLFqecg+vDQRj0Vgm/lj2sUn499Gl8oBW9Lt 4pjjLKlZaiF4ekVbL2c6pIek3fZ9TshF+ADdDt7PIwbQGePQB30a3oM/gKe0QtFKLb8l EaFaiA1YJBm2weEiYjcI4mos5pgILf+1XHu50= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=apnpEQS6NK3xY1MjGrHYfNg1VjArbmfZ1KWaTVOYZXU=; b=Ku82uQCPs+ei4V+sjHuXK+9L8Sr75pnxPjYsaaVjGRMhyG/LbYORdQoMnrbjAE6p2x eNXA1Y8vHWpJBqP0+rGofp2cenmcj8bGQDDSdDNKe3pf7S5eunzQw5GW44paburWCeDl Er8C7kCaMGqTt7NtUboVvDgBolV3GeeaiV6ruLpyEZg75xyfuZdQWrNbMlpaM3D6JrNT Yrye+ROgE8TqQSd9R9/zGUbOg6PlOA/Y42XP9iznxoJ1qzlDnZ+YBSj+6A7zPNNtTeNZ Tt0zx4Bnk1NPLUJmhDGE5j/sKkzRj537WKDhJPfE74oHE1Xc85+oguQMELtofjPveewZ rLOQ== X-Gm-Message-State: AA+aEWbPh2Z8efw1egIQEXz/L2FaPOMNXzvc+e2opXcByj1t1a28t0Kg 6pEScuvxUc1NHpX8DCHR9RpT+0Ct6Uh7Cw== X-Google-Smtp-Source: AFSGD/VQOFIyyld2wggWXJqhEnq7PyJYnKeKGW16cooaN3ZU7TK5XQuYI7xEVQTDx0ZfAY5PHuVgdA== X-Received: by 2002:a5d:568c:: with SMTP id f12mr12992635wrv.101.1542975286639; Fri, 23 Nov 2018 04:14:46 -0800 (PST) Received: from mba13.wifi.ns.nl (33.153.69.91.rev.sfr.net. [91.69.153.33]) by smtp.gmail.com with ESMTPSA id x79sm16469106wmd.42.2018.11.23.04.14.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Nov 2018 04:14:45 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Cc: Ard Biesheuvel , Laszlo Ersek , Leif Lindholm , Eric Auger , Andrew Jones , Philippe Mathieu-Daude , Julien Grall Date: Fri, 23 Nov 2018 13:14:28 +0100 Message-Id: <20181123121431.22353-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181123121431.22353-1-ard.biesheuvel@linaro.org> References: <20181123121431.22353-1-ard.biesheuvel@linaro.org> Subject: [PATCH 2/5] ArmPkg/ArmMmuLib: take the CPU supported maximum PA space into account X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 23 Nov 2018 12:14:48 -0000 In preparation of permitting the virt code to define a larger PA space size via gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize than what the CPU actually supports, take the CPU's capabilities into account when setting up the page tables. This is necessary because KVM will shortly support variable PA space sizes, and to support running the same UEFI binaries regardless of that limit, PcdPrePiCpuMemorySize needs to be treated as an upper bound rather than a fixed size. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c index 4b62ecb6a476..a4fde9b59383 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -593,6 +593,7 @@ ArmConfigureMmu ( { VOID* TranslationTable; UINT32 TranslationTableAttribute; + UINTN MaxAddressBits; UINT64 MaxAddress; UINTN T0SZ; UINTN RootTableEntryCount; @@ -605,7 +606,9 @@ ArmConfigureMmu ( } // Cover the entire GCD memory space - MaxAddress = (1UL << PcdGet8 (PcdPrePiCpuMemorySize)) - 1; + MaxAddressBits = MIN (ArmGetPhysicalAddressBits (), + PcdGet8 (PcdPrePiCpuMemorySize)); + MaxAddress = (1UL << MaxAddressBits) - 1; // Lookup the Table Level to get the information LookupAddresstoRootTable (MaxAddress, &T0SZ, &RootTableEntryCount); -- 2.17.1