From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::441; helo=mail-wr1-x441.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr1-x441.google.com (mail-wr1-x441.google.com [IPv6:2a00:1450:4864:20::441]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4905921195BC9 for ; Mon, 26 Nov 2018 14:38:32 -0800 (PST) Received: by mail-wr1-x441.google.com with SMTP id v13so17200752wrw.5 for ; Mon, 26 Nov 2018 14:38:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=U1egfUx3wEWaThtxyV8AThFJr6LCRN0RWUmzwpQcVPM=; b=MOW9FB23KpCTTku1lhvtpBqsZxLqH797+zfQlbR4e7AKONMQO0lXiThUnztaPNiIxA LScvr7Tu79GtuK8d1D4qp6hEVZkMp4yxd1Ra3nrCiUF1yJ9kLcZeGww0ZXY9TM7LZAoI FYOm3o5iOuybZAtQlTJWXVx//WMmafYYUFSQM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=U1egfUx3wEWaThtxyV8AThFJr6LCRN0RWUmzwpQcVPM=; b=mGyk7pi1R2xx912QUiMb7Bch8u4AqKmEI4+sYQLZZgzAAU3f1XQUV4mEQNNSGMxJOx SSGkpe/UhNpT/5yrwidT4kI6LyCHyydq+6HFgPOOwZIYFQFi2li2D10uUGPFjQMHL2Mw CInUD820FzBaERhTG8lfIezx6d9G74YgBgqaFD4/TOcg5KxqPeFWioAHcshncs8choI7 HV28a4uNTmX2D57Oi/LAhgjBkQ7S7JJ+MQjqgKEJSWrw5wEc3/83EF8Ihag1RyfSXcg3 TuvoL7N3Z37igGH+4HB5rCV/CEUkWxqIOuucBbElvD/99fax4h7LP+2XlRwbLlOYz6yX wJTw== X-Gm-Message-State: AA+aEWaznodR/DQSIuazY2O+cRcd1Ofyrlvyel221dpwyagUWODgecPd bbpKslsomennw3WJdwhEz3Y61mhHUds= X-Google-Smtp-Source: AFSGD/W/aFz1nCJj6OJF99AKDbKXENcwV5Q2xOwqV6fAb4lMh9BKhTexxuPjTM+EcN9B8LYvpDpt6w== X-Received: by 2002:adf:ec50:: with SMTP id w16mr25927372wrn.171.1543271910456; Mon, 26 Nov 2018 14:38:30 -0800 (PST) Received: from harold.home ([2a01:cb1d:112:6f00:8571:4c23:4f5c:5eb7]) by smtp.gmail.com with ESMTPSA id v5sm2641916wrn.71.2018.11.26.14.38.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 26 Nov 2018 14:38:29 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Cc: Ard Biesheuvel , Laszlo Ersek , Leif Lindholm , Eric Auger , Andrew Jones , Philippe Mathieu-Daude , Julien Grall Date: Mon, 26 Nov 2018 23:37:51 +0100 Message-Id: <20181126223801.17121-4-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181126223801.17121-1-ard.biesheuvel@linaro.org> References: <20181126223801.17121-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Subject: [PATCH v2 03/13] ArmPkg/ArmMmuLib: take the CPU supported maximum PA space into account X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 26 Nov 2018 22:38:32 -0000 Content-Transfer-Encoding: 8bit In preparation of dropping PcdPrePiCpuMemorySize entirely, base the maximum size of the identity map on the capabilities of the CPU. Since that may exceed what is architecturally permitted when using 4 KB pages, take ARM_MMU_IDMAP_RANGE into account as well. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf | 3 --- ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf | 3 --- ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 11 +++++++++-- 3 files changed, 9 insertions(+), 8 deletions(-) diff --git a/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf b/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf index b9f264de8d26..246963361e45 100644 --- a/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf +++ b/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf @@ -40,8 +40,5 @@ [LibraryClasses] CacheMaintenanceLib MemoryAllocationLib -[Pcd.AARCH64] - gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize - [Pcd.ARM] gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride diff --git a/ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf b/ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf index ecf13f790734..f689c193b862 100644 --- a/ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf +++ b/ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf @@ -35,6 +35,3 @@ [LibraryClasses] ArmLib CacheMaintenanceLib MemoryAllocationLib - -[Pcd.AARCH64] - gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c index 4b62ecb6a476..c1c72358ec8d 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -604,8 +604,15 @@ ArmConfigureMmu ( return EFI_INVALID_PARAMETER; } - // Cover the entire GCD memory space - MaxAddress = (1UL << PcdGet8 (PcdPrePiCpuMemorySize)) - 1; + // + // Limit the virtual address space to what we can actually use: UEFI + // mandates a 1:1 mapping, so no point in making the virtual address + // space larger than the physical address space. We also have to take + // into account the architectural limitations that result from UEFI's + // use of 4 KB pages. + // + MaxAddress = MIN (LShiftU64 (1ULL, ArmGetPhysicalAddressBits ()), + ARM_MMU_IDMAP_RANGE) - 1; // Lookup the Table Level to get the information LookupAddresstoRootTable (MaxAddress, &T0SZ, &RootTableEntryCount); -- 2.19.1