From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::444; helo=mail-wr1-x444.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id ABC592119620A for ; Wed, 28 Nov 2018 06:34:13 -0800 (PST) Received: by mail-wr1-x444.google.com with SMTP id v6so26518742wrr.12 for ; Wed, 28 Nov 2018 06:34:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qNHE9q2xToQm2C9o1zkYwWqpPhb6cTf1V+A8xAWUeFo=; b=hMpM2E6AXbJJsrLjnD3zNS7e+BRVGtOHPzURA2qjLlFdIyVSCnVr2e4l9nWKrMRiwm Xh/q4SwkqKdGabqdCSvSQ1MsRJtKzy1+vb2dvkxX9+hO3D2oqcEQjvw7NKTrk/R8tqvC JIsLHHPUJC2/V6HnpyX6n0IMT3LyEeipQkoVQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qNHE9q2xToQm2C9o1zkYwWqpPhb6cTf1V+A8xAWUeFo=; b=q1TNl7+m9H0CxIHpkCuqF/ZPfgLZYqaRRwiWeSJCWyTEv9HP/pjo50R8xlcfdoTMVK JDIWc4Tg45aBx5bLkbFicYBK+b3egSbmxvS7TjUZp9Fepsbamdrm9pX5qSiqf4WgZIY8 2JazVheEQsTYc8LzHyQ0We6d4aGYyTg6rdwVCYYmke3muvvspwdD5DkrRCaeCEoW28CF dCGxSTIhEzmhpS4ZDWNhRQybCMva+uga1rH3Kv6JBPU4H+Zf2eLVwQdSrL206mFtXMPn 0l9rc0ie+vGqBDPUZTkVWH8nhpY5Lbl6QQxZcZyMn8SBjn4UNzOS39a0ZRdiEhGr3VsX 5Lqw== X-Gm-Message-State: AA+aEWbQcE4bAHVDAyuE7YFqxxqH6YVOG74eXTjLjAGptMQfqPjubOWL 46HGy9ixfOVzq18tJQiZ1YGDFL+0oRU= X-Google-Smtp-Source: AFSGD/UJ93BqjFhv2zMv373GslnTscNPk1H+vlRAD5i8PTXf0eNHScm1BSqKSctMA9XUH8zyzvnPcA== X-Received: by 2002:adf:c042:: with SMTP id c2mr19974074wrf.158.1543415652018; Wed, 28 Nov 2018 06:34:12 -0800 (PST) Received: from harold.home ([2a01:cb1d:112:6f00:296f:238b:c20d:3626]) by smtp.gmail.com with ESMTPSA id 6sm3391891wmk.26.2018.11.28.06.34.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 28 Nov 2018 06:34:11 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Cc: Ard Biesheuvel , Laszlo Ersek , Leif Lindholm , Eric Auger , Andrew Jones , Philippe Mathieu-Daude , Julien Grall Date: Wed, 28 Nov 2018 15:33:47 +0100 Message-Id: <20181128143357.991-7-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181128143357.991-1-ard.biesheuvel@linaro.org> References: <20181128143357.991-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Subject: [PATCH v3 06/16] ArmPkg/ArmLib: add support for reading the max physical address space size X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 28 Nov 2018 14:34:14 -0000 Content-Transfer-Encoding: 8bit Add a helper function that returns the maximum physical address space size as supported by the current CPU. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- ArmPkg/Include/Library/ArmLib.h | 6 ++++++ ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S | 17 +++++++++++++++++ ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S | 8 ++++++++ ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm | 8 ++++++++ 4 files changed, 39 insertions(+) diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h index ffda50e9d767..9a804c15fdb6 100644 --- a/ArmPkg/Include/Library/ArmLib.h +++ b/ArmPkg/Include/Library/ArmLib.h @@ -733,4 +733,10 @@ ArmWriteCntvOff ( UINT64 Val ); +UINTN +EFIAPI +ArmGetPhysicalAddressBits ( + VOID + ); + #endif // __ARM_LIB__ diff --git a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S index 1ef2f61f5979..b7173e00b039 100644 --- a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S +++ b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S @@ -196,4 +196,21 @@ ASM_FUNC(ArmWriteSctlr) 3:msr sctlr_el3, x0 4:ret +ASM_FUNC(ArmGetPhysicalAddressBits) + mrs x0, id_aa64mmfr0_el1 + adr x1, .LPARanges + and x0, x0, #0xf + ldrb w0, [x1, x0] + ret + +// +// Bits 0..3 of the AA64MFR0_EL1 system register encode the size of the +// physical address space support on this CPU: +// 0 == 32 bits, 1 == 36 bits, etc etc +// 7 and up are reserved +// +.LPARanges: + .byte 32, 36, 40, 42, 44, 48, 52, 0 + .byte 0, 0, 0, 0, 0, 0, 0, 0 + ASM_FUNCTION_REMOVE_IF_UNREFERENCED diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S index f2a517671f0a..0e9f9d0453e4 100644 --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S +++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S @@ -165,4 +165,12 @@ ASM_FUNC(ArmWriteCpuActlr) isb bx lr +ASM_FUNC (ArmGetPhysicalAddressBits) + mrc p15, 0, r0, c0, c1, 4 // MMFR0 + and r0, r0, #0xf // VMSA [3:0] + cmp r0, #5 // >= 5 implies LPAE support + movlt r0, #32 // 32 bits if no LPAE + movge r0, #40 // 40 bits if LPAE + bx lr + ASM_FUNCTION_REMOVE_IF_UNREFERENCED diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm index 219140c22b13..3eb52875971d 100644 --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm +++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm @@ -169,4 +169,12 @@ isb bx lr + RVCT_ASM_EXPORT ArmGetPhysicalAddressBits + mrc p15, 0, r0, c0, c1, 4 ; MMFR0 + and r0, r0, #0xf ; VMSA [3:0] + cmp r0, #5 ; >= 5 implies LPAE support + movlt r0, #32 ; 32 bits if no LPAE + movge r0, #40 ; 40 bits if LPAE + bx lr + END -- 2.19.1