From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::442; helo=mail-wr1-x442.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C56A121196213 for ; Wed, 28 Nov 2018 06:34:16 -0800 (PST) Received: by mail-wr1-x442.google.com with SMTP id x10so26527901wrs.8 for ; Wed, 28 Nov 2018 06:34:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+MaGAl8WwjtCUc+2+Szt8QZrOFeoSkczEiOZPUnj0ms=; b=gpSFQiG33/dceFydAXOH7+8+2rTrlVr7qwz/Zy82T7psEUnWRCp1YY/8k6GkmFNOIt RIrKV80uImAEMFAvETHOt7dsJgas6xUNnBIBsxYq1oF6aBuxbVPDLl9YZo1bduAutddw k5/fgsXkDmsMNF4q+skbKUkLihQW2XkvjauU0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+MaGAl8WwjtCUc+2+Szt8QZrOFeoSkczEiOZPUnj0ms=; b=QUYvZ+WlD8mHcCo4MzsrLxVUKoaZ0heg0U+daDWpHsrlwTNJr1nTsswVqEcQg1VWM8 RZgVaJoOHAu4hMrgkScyErwZdkau5TtbR2dxl+I+LnNMUE3qVlkWAU79rQp+wNQDqgaE PCVKTB0axm2/eE/opiLnzaj1+Lbp7Rwb6wAy61YIvVRNWfqJGC6CS6ik4xDagwEsqzPV +uADIz0b4BUGYtoDz2pxxW/P5PwRxC9FRBrgTkdzEQnEAXeEx1VlbF+mp4aw9lFeBOiQ VACnzUQvKIAFDPAdV17Ef0doiYKN2jo6zm0Jct9tTTfXQ6zj4HhVEnkLIH9j7/L0+OwX xnow== X-Gm-Message-State: AA+aEWZ1fmUf8uIrIBefBiwQSzZMCwpc+jy5wGWX8de4VRuGtHAUWruL kUqaQAxHOLzdZo2FqHNNfRny0K27yHo= X-Google-Smtp-Source: AFSGD/VQS2YjijuDtKPLC34BY+YZqFxoU/8m1JP2uYBqcuHCCin9+yCKKMiTGbgHzYEC5DTMJpJ/gQ== X-Received: by 2002:a05:6000:1189:: with SMTP id g9mr33590158wrx.221.1543415654533; Wed, 28 Nov 2018 06:34:14 -0800 (PST) Received: from harold.home ([2a01:cb1d:112:6f00:296f:238b:c20d:3626]) by smtp.gmail.com with ESMTPSA id 6sm3391891wmk.26.2018.11.28.06.34.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 28 Nov 2018 06:34:13 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Cc: Ard Biesheuvel , Laszlo Ersek , Leif Lindholm , Eric Auger , Andrew Jones , Philippe Mathieu-Daude , Julien Grall Date: Wed, 28 Nov 2018 15:33:49 +0100 Message-Id: <20181128143357.991-9-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181128143357.991-1-ard.biesheuvel@linaro.org> References: <20181128143357.991-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Subject: [PATCH v3 08/16] ArmPkg/ArmMmuLib: take the CPU supported maximum PA space into account X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 28 Nov 2018 14:34:17 -0000 Content-Transfer-Encoding: 8bit In preparation of dropping PcdPrePiCpuMemorySize entirely, base the maximum size of the identity map on the capabilities of the CPU. Since that may exceed what is architecturally permitted when using 4 KB pages, take MAX_ADDRESS into account as well. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf | 3 --- ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf | 3 --- ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 11 +++++++++-- 3 files changed, 9 insertions(+), 8 deletions(-) diff --git a/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf b/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf index b9f264de8d26..246963361e45 100644 --- a/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf +++ b/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf @@ -40,8 +40,5 @@ [LibraryClasses] CacheMaintenanceLib MemoryAllocationLib -[Pcd.AARCH64] - gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize - [Pcd.ARM] gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride diff --git a/ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf b/ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf index ecf13f790734..f689c193b862 100644 --- a/ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf +++ b/ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf @@ -35,6 +35,3 @@ [LibraryClasses] ArmLib CacheMaintenanceLib MemoryAllocationLib - -[Pcd.AARCH64] - gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c index 4b62ecb6a476..5403b8d4070e 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -604,8 +604,15 @@ ArmConfigureMmu ( return EFI_INVALID_PARAMETER; } - // Cover the entire GCD memory space - MaxAddress = (1UL << PcdGet8 (PcdPrePiCpuMemorySize)) - 1; + // + // Limit the virtual address space to what we can actually use: UEFI + // mandates a 1:1 mapping, so no point in making the virtual address + // space larger than the physical address space. We also have to take + // into account the architectural limitations that result from UEFI's + // use of 4 KB pages. + // + MaxAddress = MIN (LShiftU64 (1ULL, ArmGetPhysicalAddressBits ()) - 1, + MAX_ADDRESS); // Lookup the Table Level to get the information LookupAddresstoRootTable (MaxAddress, &T0SZ, &RootTableEntryCount); -- 2.19.1