From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::444; helo=mail-wr1-x444.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id ECD4621193078 for ; Thu, 29 Nov 2018 07:42:27 -0800 (PST) Received: by mail-wr1-x444.google.com with SMTP id 96so2386647wrb.2 for ; Thu, 29 Nov 2018 07:42:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=59FwYpjL3rvfWDDgISS4sbbrX7OkipwrlgvXlQJpmTg=; b=DP1Y9U58w/+eRyZFOef+yxWJCX9SLFiqmfdYqXu9q4wu1glyNsbV99GDvXeVgoIa5v NmviPlgIgB6jPmlno0PtCZLK/NWE55/sXZ8HtyD6jnO8AC1OCOod++jG5BTz3mFtGH7K xKKMrUkYu+LLoyiS3NLr9oJRD/7XVWcRsc7CQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=59FwYpjL3rvfWDDgISS4sbbrX7OkipwrlgvXlQJpmTg=; b=ruWDFEEv7yJv9Qs8xnhE4oRSG8jwDcwn1eYAsjsK50C6OyBi6R/2z4oIjqQEQxJP3P sO1A/CYZ0XfizCvJKrWDNioICY/EHvkjIiV2TKXclCm5WajB34fvtZTOPYmdgfhH63Rz JXcYPQYfuHJscBjk5FfMAy4ovfyer+lLHWQd0+brm4WTLr6mSV0OxuhYH2y4tlHs2MsW wg04pb24q3Rc2NNcC1nYJmwK1vz82F2wdvJGPF9BPaamQYCcyFqYm27KsNcqNMfcqn+f 075XCeqT8wkIMZxkhAlzqdt8LtioNoMmODVYMJZnzXHQr6kNZdPPmVByV9En675g5dHY +J5Q== X-Gm-Message-State: AA+aEWY+Lf9Pu6HRPWCGCUivoX0rc9gIbf39GmWAVPuvrQhG3Ifhmmc7 AGFTXGo3gFLbT/pB+NjK562nFGvXsCE= X-Google-Smtp-Source: AFSGD/WYS5dEVyesW6qKerR1HlSUlI8bICf6AGZWlaXjcKytwA2/wY/V8/diWhNjl/fDIQkLywlzWg== X-Received: by 2002:adf:a1d2:: with SMTP id v18mr1786620wrv.87.1543506146478; Thu, 29 Nov 2018 07:42:26 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id c65sm2188736wma.24.2018.11.29.07.42.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 29 Nov 2018 07:42:25 -0800 (PST) Date: Thu, 29 Nov 2018 15:42:23 +0000 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org, Laszlo Ersek , Eric Auger , Andrew Jones , Philippe Mathieu-Daude , Julien Grall Message-ID: <20181129154223.jov6jlqsu4vsljxa@bivouac.eciton.net> References: <20181128143357.991-1-ard.biesheuvel@linaro.org> <20181128143357.991-7-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <20181128143357.991-7-ard.biesheuvel@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH v3 06/16] ArmPkg/ArmLib: add support for reading the max physical address space size X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 29 Nov 2018 15:42:28 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Nov 28, 2018 at 03:33:47PM +0100, Ard Biesheuvel wrote: > Add a helper function that returns the maximum physical address space > size as supported by the current CPU. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm > --- > ArmPkg/Include/Library/ArmLib.h | 6 ++++++ > ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S | 17 +++++++++++++++++ > ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S | 8 ++++++++ > ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm | 8 ++++++++ > 4 files changed, 39 insertions(+) > > diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h > index ffda50e9d767..9a804c15fdb6 100644 > --- a/ArmPkg/Include/Library/ArmLib.h > +++ b/ArmPkg/Include/Library/ArmLib.h > @@ -733,4 +733,10 @@ ArmWriteCntvOff ( > UINT64 Val > ); > > +UINTN > +EFIAPI > +ArmGetPhysicalAddressBits ( > + VOID > + ); > + > #endif // __ARM_LIB__ > diff --git a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S > index 1ef2f61f5979..b7173e00b039 100644 > --- a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S > +++ b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S > @@ -196,4 +196,21 @@ ASM_FUNC(ArmWriteSctlr) > 3:msr sctlr_el3, x0 > 4:ret > > +ASM_FUNC(ArmGetPhysicalAddressBits) > + mrs x0, id_aa64mmfr0_el1 > + adr x1, .LPARanges > + and x0, x0, #0xf > + ldrb w0, [x1, x0] > + ret > + > +// > +// Bits 0..3 of the AA64MFR0_EL1 system register encode the size of the > +// physical address space support on this CPU: > +// 0 == 32 bits, 1 == 36 bits, etc etc > +// 7 and up are reserved > +// > +.LPARanges: > + .byte 32, 36, 40, 42, 44, 48, 52, 0 > + .byte 0, 0, 0, 0, 0, 0, 0, 0 > + > ASM_FUNCTION_REMOVE_IF_UNREFERENCED > diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S > index f2a517671f0a..0e9f9d0453e4 100644 > --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S > +++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S > @@ -165,4 +165,12 @@ ASM_FUNC(ArmWriteCpuActlr) > isb > bx lr > > +ASM_FUNC (ArmGetPhysicalAddressBits) > + mrc p15, 0, r0, c0, c1, 4 // MMFR0 > + and r0, r0, #0xf // VMSA [3:0] > + cmp r0, #5 // >= 5 implies LPAE support > + movlt r0, #32 // 32 bits if no LPAE > + movge r0, #40 // 40 bits if LPAE > + bx lr > + > ASM_FUNCTION_REMOVE_IF_UNREFERENCED > diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm > index 219140c22b13..3eb52875971d 100644 > --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm > +++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm > @@ -169,4 +169,12 @@ > isb > bx lr > > + RVCT_ASM_EXPORT ArmGetPhysicalAddressBits > + mrc p15, 0, r0, c0, c1, 4 ; MMFR0 > + and r0, r0, #0xf ; VMSA [3:0] > + cmp r0, #5 ; >= 5 implies LPAE support > + movlt r0, #32 ; 32 bits if no LPAE > + movge r0, #40 ; 40 bits if LPAE > + bx lr > + > END > -- > 2.19.1 >