From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::342; helo=mail-wm1-x342.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D43CA21198CB3 for ; Tue, 11 Dec 2018 06:03:22 -0800 (PST) Received: by mail-wm1-x342.google.com with SMTP id a18so2395890wmj.1 for ; Tue, 11 Dec 2018 06:03:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=HcCjs39JwB0rhX5Ltivp/4Qy5epBhXMr0eYPD+HrjUI=; b=H8AtV9J5oFCuGaEjSrzJJFBfrfu3h/RcaXIIgQBsyBhilL2++O22MEnlZd5wASz/gX pJQD/oA3yzGf0tiJBG7/18Vg4d1EdN5KVvC48RPI7PcYwyPhYeDV69NEV18Zf8sSyIlS 9sr2B560ROosMFEgLD653h/mXmhA1IW3DGYas= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=HcCjs39JwB0rhX5Ltivp/4Qy5epBhXMr0eYPD+HrjUI=; b=po885og0XLmoXTMKc4XvZmo7UYxA3IwVkBluSnlO52VJzfZdhP6WGtiVYskeZbxI1C tmVH85TiPdnZjYDGmv/vasavbs/1lA4GTDIiBd9JYzHatgqumPX7N3URSmBBPCTw5hOL ZjUjlrP6N1Sn+EE2vUZ/e3kJzJI1dpKk7ZuyhoNaxVGc8eSZbtSQaUHJF9nNTDONGC4I Pgumin6/aXnIE/Zv9DS6Al7Yvjl/QVnrWbf0ZpmviqgxGBbjAPO9DTXo/lywBD4rGADh YTuNX7BIrfpuXI8V2do791oEUfoJq8u6qrlsvE7ZImF3yn/IjPILjJWGjaYoMLipsYpR hxoQ== X-Gm-Message-State: AA+aEWbueFYK2vh4oERrdJd006lEVK/2zqJoiPfXEPWP3SXsFX4LU0N+ mnl510pSMHYRXZMIBzSLvGCidYs6K6U= X-Google-Smtp-Source: AFSGD/WxW0FU1GBdVNaxF653eKciT19XXSypFmW8PGBfdXYCoKlVLdJBYBdHjNIuRf9/bH/u4MuKYA== X-Received: by 2002:a1c:f207:: with SMTP id s7mr2349922wmc.87.1544537000921; Tue, 11 Dec 2018 06:03:20 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id c8sm10063803wrx.42.2018.12.11.06.03.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 11 Dec 2018 06:03:19 -0800 (PST) Date: Tue, 11 Dec 2018 14:03:18 +0000 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org Message-ID: <20181211140318.kkciujb52xsqgf3c@bivouac.eciton.net> References: <20181211132510.21359-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <20181211132510.21359-1-ard.biesheuvel@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH] ArmPkg/DefaultExceptionHandlerLib ARM: avoid endless loop in RELEASE builds X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 11 Dec 2018 14:03:23 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Tue, Dec 11, 2018 at 02:25:10PM +0100, Ard Biesheuvel wrote: > Ensure that we prevent the CPU from proceeding after having taken an > unhandled exception on a RELEASE build, which does not contain the > ASSERT() which ensures this on DEBUG and NOOPT builds. Sounds like a good idea. Some silly questions below: > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel > --- > ArmPkg/Library/DefaultExceptionHandlerLib/Arm/DefaultExceptionHandler.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/ArmPkg/Library/DefaultExceptionHandlerLib/Arm/DefaultExceptionHandler.c b/ArmPkg/Library/DefaultExceptionHandlerLib/Arm/DefaultExceptionHandler.c > index 0b9da031b47d..9d96d5aabd96 100644 > --- a/ArmPkg/Library/DefaultExceptionHandlerLib/Arm/DefaultExceptionHandler.c > +++ b/ArmPkg/Library/DefaultExceptionHandlerLib/Arm/DefaultExceptionHandler.c > @@ -267,10 +267,15 @@ DefaultExceptionHandler ( > DEBUG ((EFI_D_ERROR, "\n")); > ASSERT (FALSE); > > + if (!PcAdjust) { Won't this always be 0 for a RELEASE build? (By convention if nothing else.) And won't we already have ASSERTed in any other case? > + CpuDeadLoop (); > + } > + > // Clear the error registers that we have already displayed incase some one wants to keep going > SystemContext.SystemContextArm->DFSR = 0; > SystemContext.SystemContextArm->IFSR = 0; > > // If some one is stepping past the exception handler adjust the PC to point to the next instruction > SystemContext.SystemContextArm->PC += PcAdjust; > + Hmm? / Leif > } > -- > 2.19.2 >