From: Leif Lindholm <leif.lindholm@linaro.org>
To: Chris Co <Christopher.Co@microsoft.com>
Cc: "edk2-devel@lists.01.org" <edk2-devel@lists.01.org>,
Ard Biesheuvel <ard.biesheuvel@linaro.org>,
Michael D Kinney <michael.d.kinney@intel.com>
Subject: Re: [PATCH edk2-platforms 11/27] Silicon/NXP: Add i.MX6 SoC header files
Date: Thu, 13 Dec 2018 17:11:56 +0000 [thread overview]
Message-ID: <20181213171155.h5egq7mrt6fxhpja@bivouac.eciton.net> (raw)
In-Reply-To: <20180921082542.35768-12-christopher.co@microsoft.com>
On Fri, Sep 21, 2018 at 08:26:02AM +0000, Chris Co wrote:
> This adds includes for NXP i.MX6 SoC family, specifically Dual/Quad,
> Solo/DualLite, SoloX, DualPlus/QuadPlus families.
> These are the header files for managing clocks, IoMux, and general
> SoC register layout information.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Christopher Co <christopher.co@microsoft.com>
> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> Cc: Leif Lindholm <leif.lindholm@linaro.org>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> ---
> Silicon/NXP/iMX6Pkg/Include/iMX6.h | 39 +
> Silicon/NXP/iMX6Pkg/Include/iMX6BoardLib.h | 55 +
> Silicon/NXP/iMX6Pkg/Include/iMX6ClkPwr.h | 105 +
> Silicon/NXP/iMX6Pkg/Include/iMX6ClkPwr_DQ.h | 181 ++
> Silicon/NXP/iMX6Pkg/Include/iMX6ClkPwr_SDL.h | 176 ++
> Silicon/NXP/iMX6Pkg/Include/iMX6ClkPwr_SX.h | 190 ++
> Silicon/NXP/iMX6Pkg/Include/iMX6IoMux.h | 202 ++
> Silicon/NXP/iMX6Pkg/Include/iMX6IoMux_DQP.h | 2466 ++++++++++++++++++++
> Silicon/NXP/iMX6Pkg/Include/iMX6IoMux_SDL.h | 1875 +++++++++++++++
> Silicon/NXP/iMX6Pkg/Include/iMX6IoMux_SX.h | 2270 ++++++++++++++++++
> Silicon/NXP/iMX6Pkg/Include/iMX6_DQ.h | 332 +++
> Silicon/NXP/iMX6Pkg/Include/iMX6_DQP.h | 335 +++
> Silicon/NXP/iMX6Pkg/Include/iMX6_SDL.h | 301 +++
> Silicon/NXP/iMX6Pkg/Include/iMX6_SX.h | 1730 ++++++++++++++
> Silicon/NXP/iMX6Pkg/Include/iMX6_common.h | 1350 +++++++++++
> 15 files changed, 11607 insertions(+)
>
> diff --git a/Silicon/NXP/iMX6Pkg/Include/iMX6.h b/Silicon/NXP/iMX6Pkg/Include/iMX6.h
> new file mode 100644
> index 000000000000..ded03eced048
> --- /dev/null
> +++ b/Silicon/NXP/iMX6Pkg/Include/iMX6.h
> @@ -0,0 +1,39 @@
> +/** @file
> +*
> +* Copyright (c) 2018 Microsoft Corporation. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#ifndef __IMX6_H__
> +#define __IMX6_H__
> +
> +// Platform specific definition
> +#define EFI_ACPI_OEM_TABLE_ID SIGNATURE_64('I','M','X','6','E','D','K','2')
> +#define EFI_ACPI_OEM_REVISION 0x01000101
> +#define EFI_ACPI_CREATOR_ID SIGNATURE_32('I','M','X','6')
> +#define EFI_ACPI_CREATOR_REVISION 0x00000001
> +
> +#if defined(CPU_IMX6DQ)
> +#include "iMX6_DQ.h"
> +#elif defined(CPU_IMX6DQP)
> +#include "iMX6_DQP.h"
> +#elif defined(CPU_IMX6SDL)
> +#include "iMX6_SDL.h"
> +#elif defined(CPU_IMX6SX)
> +#include "iMX6_SX.h"
> +#else
> +#error iMX6 CPU Type Not Defined! (Preprocessor Flag)
> +#endif
> +
> +#define SERIAL_DEBUG_PORT_INIT_MSG "\r\nDebug Serial Port Init\r\n"
> +#define SERIAL_PORT_INIT_MSG "UART"
> +
> +#endif // __IMX6_H__
> diff --git a/Silicon/NXP/iMX6Pkg/Include/iMX6BoardLib.h b/Silicon/NXP/iMX6Pkg/Include/iMX6BoardLib.h
> new file mode 100644
> index 000000000000..7997ebc72897
> --- /dev/null
> +++ b/Silicon/NXP/iMX6Pkg/Include/iMX6BoardLib.h
> @@ -0,0 +1,55 @@
> +/** @file
> +*
> +* Copyright (c) 2018 Microsoft Corporation. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#ifndef _IMX6_BOARD_LIB_H_
> +#define _IMX6_BOARD_LIB_H_
> +
> +/*
> + Mandatory functions to implement by the board library.
> +*/
> +
> +VOID
> +ImxClkPwrInit (
> + );
> +
> +/*
> + Optional functions to implement by the board library.
> + The default implementation of these functions if not overridden is NOOP.
> +*/
> +
> +VOID
> +SdhcInit (
> + );
> +
> +VOID
> +EhciInit (
> + );
> +
> +VOID
> +I2cInit (
> + );
> +
> +VOID
> +SpiInit (
> + );
> +
> +VOID
> +PcieInit (
> + );
> +
> +VOID
> +SetupAudio (
> + );
> +
> +#endif // _IMX6_BOARD_LIB_H_
> diff --git a/Silicon/NXP/iMX6Pkg/Include/iMX6ClkPwr.h b/Silicon/NXP/iMX6Pkg/Include/iMX6ClkPwr.h
> new file mode 100644
> index 000000000000..18262751c443
> --- /dev/null
> +++ b/Silicon/NXP/iMX6Pkg/Include/iMX6ClkPwr.h
> @@ -0,0 +1,105 @@
> +/** @file
> +*
> +* Copyright (c) 2018 Microsoft Corporation. All rights reserved.
> +* Copyright 2018 NXP
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#ifndef _IMX6_CLK_PWR_H_
> +#define _IMX6_CLK_PWR_H_
> +
> +// The valid value for PLL loop divider is 27-54 so define the range of valid
> +// frequency for PLL5 below before divider is applied.
> +#define PLL5_MIN_FREQ 648000000
> +#define PLL5_MAX_FREQ 1296000000
> +
> +#if defined(CPU_IMX6DQ) || defined (CPU_IMX6DQP)
> +#include "iMX6ClkPwr_DQ.h"
> +#elif defined(CPU_IMX6SDL)
> +#include "iMX6ClkPwr_SDL.h"
> +#elif defined(CPU_IMX6SX)
> +#include "iMX6ClkPwr_SX.h"
> +#else
> +#error iMX6 CPU Type Not Defined!
> +#endif
> +
> +typedef enum {
> + IMX_CLOCK_GATE_STATE_OFF = 0x0,
> + IMX_CLOCK_GATE_STATE_ON_RUN = 0x1,
> + IMX_CLOCK_GATE_STATE_ON = 0x3,
> +} IMX_CLOCK_GATE_STATE;
> +
> +typedef struct {
> + UINT32 Frequency;
> + IMX_CLK Parent;
> +} IMX_CLOCK_INFO;
> +
> +VOID
> +ImxClkPwrSetClockGate (
> + IN IMX_CLK_GATE ClockGate,
> + IN IMX_CLOCK_GATE_STATE State
> + );
> +
> +// Set multiple clock gates to a given state
> +VOID
> +ImxClkPwrSetClockGates (
> + IN CONST IMX_CLK_GATE *ClockGateList,
> + IN UINTN ClockGateCount,
> + IN IMX_CLOCK_GATE_STATE State
> + );
> +
> +IMX_CLOCK_GATE_STATE
> +ImxClkPwrGetClockGate (
> + IN IMX_CLK_GATE ClockGate
> + );
> +
> +EFI_STATUS
> +ImxClkPwrGetClockInfo (
> + IN IMX_CLK ClockId,
> + OUT IMX_CLOCK_INFO *ClockInfo
> +);
> +
> +EFI_STATUS
> +ImxClkPwrGpuEnable (
> + );
> +
> +EFI_STATUS
> +ImxClkPwrIpuDIxEnable (
> + );
> +
> +EFI_STATUS ImxClkPwrIpuLDBxEnable (
> + );
> +
> +EFI_STATUS
> +ImxSetPll5ReferenceRate (
> + UINT32 ClockRate
> + );
> +
> +EFI_STATUS
> +ImxClkPwrClkOut1Enable (
> + IMX_CLK Clock,
> + UINT32 Divider
> + );
> +
> +VOID
> +ImxClkPwrClkOut1Disable (
> + );
> +
> +EFI_STATUS
> +ImxClkPwrValidateClocks (
> + );
> +
> +CONST CHAR16
> +*StringFromImxClk (
> + IN IMX_CLK Value
> + );
> +
> +#endif // _IMX6_CLK_PWR_H_
> diff --git a/Silicon/NXP/iMX6Pkg/Include/iMX6ClkPwr_DQ.h b/Silicon/NXP/iMX6Pkg/Include/iMX6ClkPwr_DQ.h
> new file mode 100644
> index 000000000000..253e7c028bcb
> --- /dev/null
> +++ b/Silicon/NXP/iMX6Pkg/Include/iMX6ClkPwr_DQ.h
> @@ -0,0 +1,181 @@
> +/** @file
> +*
> +* Copyright (c) 2018 Microsoft Corporation. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#ifndef _IMX6_CLK_PWR_DQ_H_
> +#define _IMX6_CLK_PWR_DQ_H_
> +
> +// Clock signal definitions
> +typedef enum {
> + IMX_CLK_NONE,
> + IMX_OSC_CLK,
> + IMX_PLL1_MAIN_CLK,
> + IMX_PLL2_MAIN_CLK,
> + IMX_PLL2_PFD0,
> + IMX_PLL2_PFD1,
> + IMX_PLL2_PFD2,
> + IMX_PLL3_MAIN_CLK,
> + IMX_PLL3_PFD0,
> + IMX_PLL3_PFD1,
> + IMX_PLL3_PFD2,
> + IMX_PLL3_PFD3,
> + IMX_PLL4_MAIN_CLK,
> + IMX_PLL5_MAIN_CLK,
> + IMX_CLK1,
> + IMX_CLK2,
> + IMX_PLL1_SW_CLK,
> + IMX_STEP_CLK,
> + IMX_PLL3_SW_CLK,
> + IMX_AXI_ALT,
> + IMX_AXI_CLK_ROOT,
> + IMX_PERIPH_CLK2,
> + IMX_PERIPH_CLK,
> + IMX_PRE_PERIPH_CLK,
> + IMX_PRE_PERIPH2_CLK,
> + IMX_PERIPH2_CLK,
> + IMX_ARM_CLK_ROOT,
> + IMX_MMDC_CH0_CLK_ROOT,
> + IMX_MMDC_CH1_CLK_ROOT,
> + IMX_AHB_CLK_ROOT,
> + IMX_IPG_CLK_ROOT,
> + IMX_PERCLK_CLK_ROOT,
> + IMX_USDHC1_CLK_ROOT,
> + IMX_USDHC2_CLK_ROOT,
> + IMX_USDHC3_CLK_ROOT,
> + IMX_USDHC4_CLK_ROOT,
> + IMX_SSI1_CLK_ROOT,
> + IMX_SSI2_CLK_ROOT,
> + IMX_SSI3_CLK_ROOT,
> + IMX_GPU2D_AXI_CLK_ROOT,
> + IMX_GPU3D_AXI_CLK_ROOT,
> + IMX_PCIE_AXI_CLK_ROOT,
> + IMX_VDO_AXI_CLK_ROOT,
> + IMX_IPU1_HSP_CLK_ROOT,
> + IMX_IPU2_HSP_CLK_ROOT,
> + IMX_GPU2D_CORE_CLK_ROOT,
> + IMX_ACLK_EIM_SLOW_CLK_ROOT,
> + IMX_ACLK_CLK_ROOT,
> + IMX_ENFC_CLK_ROOT,
> + IMX_GPU3D_CORE_CLK_ROOT,
> + IMX_GPU3D_SHADER_CLK_ROOT,
> + IMX_VPU_AXI_CLK_ROOT,
> + IMX_IPU1_DI0_CLK_ROOT,
> + IMX_IPU1_DI1_CLK_ROOT,
> + IMX_IPU2_DI0_CLK_ROOT,
> + IMX_IPU2_DI1_CLK_ROOT,
> + IMX_LDB_DI0_SERIAL_CLK_ROOT,
> + IMX_LDB_DI0_IPU,
> + IMX_LDB_DI1_SERIAL_CLK_ROOT,
> + IMX_LDB_DI1_IPU,
> + IMX_SPDIF0_CLK_ROOT,
> + IMX_SPDIF1_CLK_ROOT,
> + IMX_ESAI_CLK_ROOT,
> + IMX_HSI_TX_CLK_ROOT,
> + IMX_CAN_CLK_ROOT,
> + IMX_ECSPI_CLK_ROOT,
> + IMX_UART_CLK_ROOT,
> + IMX_VIDEO_27M_CLK_ROOT,
> + IMX_CLK_MAX,
> +} IMX_CLK;
> +
> +// Clock gate definitions
> +typedef enum {
> + IMX_AIPS_TZ1_CLK_ENABLE,
> + IMX_AIPS_TZ2_CLK_ENABLE,
> + IMX_APBHDMA_HCLK_ENABLE,
> + IMX_ASRC_CLK_ENABLE,
> + IMX_CAAM_SECURE_MEM_CLK_ENABLE,
> + IMX_CAAM_WRAPPER_ACLK_ENABLE,
> + IMX_CAAM_WRAPPER_IPG_ENABLE,
> + IMX_CAN1_CLK_ENABLE,
> + IMX_CAN1_SERIAL_CLK_ENABLE,
> + IMX_CAN2_CLK_ENABLE,
> + IMX_CAN2_SERIAL_CLK_ENABLE,
> + IMX_ARM_DBG_CLK_ENABLE,
> + IMX_DCIC1_CLK_ENABLE,
> + IMX_DCIC2_CLK_ENABLE,
> + IMX_DTCP_CLK_ENABLE,
> + IMX_ECSPI1_CLK_ENABLE,
> + IMX_ECSPI2_CLK_ENABLE,
> + IMX_ECSPI3_CLK_ENABLE,
> + IMX_ECSPI4_CLK_ENABLE,
> + IMX_ECSPI5_CLK_ENABLE,
> + IMX_ENET_CLK_ENABLE,
> + IMX_EPIT1_CLK_ENABLE,
> + IMX_EPIT2_CLK_ENABLE,
> + IMX_ESAI_CLK_ENABLE,
> + IMX_GPT_CLK_ENABLE,
> + IMX_GPT_SERIAL_CLK_ENABLE,
> + IMX_GPU2D_CLK_ENABLE,
> + IMX_GPU3D_CLK_ENABLE,
> + IMX_HDMI_TX_ENABLE,
> + IMX_HDMI_TX_ISFRCLK_ENABLE,
> + IMX_I2C1_SERIAL_CLK_ENABLE,
> + IMX_I2C2_SERIAL_CLK_ENABLE,
> + IMX_I2C3_SERIAL_CLK_ENABLE,
> + IMX_IIM_CLK_ENABLE,
> + IMX_IOMUX_IPT_CLK_IO_ENABLE,
> + IMX_IPMUX1_CLK_ENABLE,
> + IMX_IPMUX2_CLK_ENABLE,
> + IMX_IPMUX3_CLK_ENABLE,
> + IMX_IPSYNC_IP2APB_TZASC1_IPG_MASTER_CLK_ENABLE,
> + IMX_IPSYNC_IP2APB_TZASC2_IPG_MASTER_CLK_ENABLE,
> + IMX_IPSYNC_VDOA_IPG_MASTER_CLK_ENABLE,
> + IMX_IPU1_CLK_ENABLE,
> + IMX_IPU1_DI0_CLK_ENABLE,
> + IMX_IPU1_DI1_CLK_ENABLE,
> + IMX_IPU2_CLK_ENABLE,
> + IMX_IPU2_DI0_CLK_ENABLE,
> + IMX_IPU2_DI1_CLK_ENABLE,
> + IMX_LDB_DI0_CLK_ENABLE,
> + IMX_LDB_DI1_CLK_ENABLE,
> + IMX_MIPI_CORE_CFG_CLK_ENABLE,
> + IMX_MLB_CLK_ENABLE,
> + IMX_MMDC_CORE_ACLK_FAST_CORE_P0_ENABLE,
> + IMX_MMDC_CORE_IPG_CLK_P0_ENABLE,
> + IMX_OCRAM_CLK_ENABLE,
> + IMX_OPENVGAXICLK_CLK_ROOT_ENABLE,
> + IMX_PCIE_ROOT_ENABLE,
> + IMX_PL301_MX6QFAST1_S133CLK_ENABLE,
> + IMX_PL301_MX6QPER1_BCHCLK_ENABLE,
> + IMX_PL301_MX6QPER2_MAINCLK_ENABLE,
> + IMX_PWM1_CLK_ENABLE,
> + IMX_PWM2_CLK_ENABLE,
> + IMX_PWM3_CLK_ENABLE,
> + IMX_PWM4_CLK_ENABLE,
> + IMX_RAWNAND_U_BCH_INPUT_APB_CLK_ENABLE,
> + IMX_RAWNAND_U_GPMI_BCH_INPUT_BCH_CLK_ENABLE,
> + IMX_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_CLK_ENABLE,
> + IMX_RAWNAND_U_GPMI_INPUT_APB_CLK_ENABLE,
> + IMX_ROM_CLK_ENABLE,
> + IMX_SATA_CLK_ENABLE,
> + IMX_SDMA_CLK_ENABLE,
> + IMX_SPBA_CLK_ENABLE,
> + IMX_SPDIF_CLK_ENABLE,
> + IMX_SSI1_CLK_ENABLE,
> + IMX_SSI2_CLK_ENABLE,
> + IMX_SSI3_CLK_ENABLE,
> + IMX_UART_CLK_ENABLE,
> + IMX_UART_SERIAL_CLK_ENABLE,
> + IMX_USBOH3_CLK_ENABLE,
> + IMX_USDHC1_CLK_ENABLE,
> + IMX_USDHC2_CLK_ENABLE,
> + IMX_USDHC3_CLK_ENABLE,
> + IMX_USDHC4_CLK_ENABLE,
> + IMX_EIM_SLOW_CLK_ENABLE,
> + IMX_VDOAXICLK_CLK_ENABLE,
> + IMX_VPU_CLK_ENABLE,
> + IMX_CLK_GATE_MAX,
> +} IMX_CLK_GATE;
> +
> +#endif /* _IMX6_CLK_PWR_DQ_H_ */
> diff --git a/Silicon/NXP/iMX6Pkg/Include/iMX6ClkPwr_SDL.h b/Silicon/NXP/iMX6Pkg/Include/iMX6ClkPwr_SDL.h
> new file mode 100644
> index 000000000000..d9e0bb1e15a7
> --- /dev/null
> +++ b/Silicon/NXP/iMX6Pkg/Include/iMX6ClkPwr_SDL.h
> @@ -0,0 +1,176 @@
> +/** @file
> +*
> +* Copyright (c) 2018 Microsoft Corporation. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#ifndef _IMX6_CLK_PWR_SDL_H_
> +#define _IMX6_CLK_PWR_SDL_H_
> +
> +// Clock signal definitions for iMX6 Solo and DualLite
> +typedef enum {
> + IMX_CLK_NONE,
> + IMX_OSC_CLK,
> + IMX_PLL1_MAIN_CLK,
> + IMX_PLL2_MAIN_CLK,
> + IMX_PLL2_PFD0,
> + IMX_PLL2_PFD1,
> + IMX_PLL2_PFD2,
> + IMX_PLL3_MAIN_CLK,
> + IMX_PLL3_PFD0,
> + IMX_PLL3_PFD1,
> + IMX_PLL3_PFD2,
> + IMX_PLL3_PFD3,
> + IMX_PLL4_MAIN_CLK,
> + IMX_PLL5_MAIN_CLK,
> + IMX_CLK1,
> + IMX_CLK2,
> + IMX_PLL1_SW_CLK,
> + IMX_STEP_CLK,
> + IMX_PLL3_SW_CLK,
> + IMX_AXI_ALT,
> + IMX_AXI_CLK_ROOT,
> + IMX_PERIPH_CLK2,
> + IMX_PERIPH_CLK,
> + IMX_PRE_PERIPH_CLK,
> + IMX_PRE_PERIPH2_CLK,
> + IMX_PERIPH2_CLK,
> + IMX_ARM_CLK_ROOT,
> + IMX_MMDC_CH0_CLK_ROOT,
> + IMX_MMDC_CH1_CLK_ROOT,
> + IMX_AHB_CLK_ROOT,
> + IMX_IPG_CLK_ROOT,
> + IMX_PERCLK_CLK_ROOT,
> + IMX_USDHC1_CLK_ROOT,
> + IMX_USDHC2_CLK_ROOT,
> + IMX_USDHC3_CLK_ROOT,
> + IMX_USDHC4_CLK_ROOT,
> + IMX_SSI1_CLK_ROOT,
> + IMX_SSI2_CLK_ROOT,
> + IMX_SSI3_CLK_ROOT,
> + IMX_GPU2D_AXI_CLK_ROOT,
> + IMX_GPU3D_AXI_CLK_ROOT,
> + IMX_PCIE_AXI_CLK_ROOT,
> + IMX_VDO_AXI_CLK_ROOT,
> + IMX_IPU1_HSP_CLK_ROOT,
> + IMX_GPU2D_CORE_CLK_ROOT,
> + IMX_ACLK_EIM_SLOW_CLK_ROOT,
> + IMX_ACLK_CLK_ROOT,
> + IMX_ENFC_CLK_ROOT,
> + IMX_GPU3D_CORE_CLK_ROOT,
> + IMX_GPU3D_SHADER_CLK_ROOT,
> + IMX_VPU_AXI_CLK_ROOT,
> + IMX_IPU1_DI0_CLK_ROOT,
> + IMX_IPU1_DI1_CLK_ROOT,
> + IMX_LDB_DI0_SERIAL_CLK_ROOT,
> + IMX_LDB_DI0_IPU,
> + IMX_LDB_DI1_SERIAL_CLK_ROOT,
> + IMX_LDB_DI1_IPU,
> + IMX_SPDIF0_CLK_ROOT,
> + IMX_SPDIF1_CLK_ROOT,
> + IMX_ESAI_CLK_ROOT,
> + IMX_HSI_TX_CLK_ROOT,
> + IMX_CAN_CLK_ROOT,
> + IMX_ECSPI_CLK_ROOT,
> + IMX_UART_CLK_ROOT,
> + IMX_VIDEO_27M_CLK_ROOT,
> + IMX_CLK_MAX,
> +} IMX_CLK;
> +
> +// Clock gate definitions
> +typedef enum {
> + IMX_AIPS_TZ1_CLK_ENABLE,
> + IMX_AIPS_TZ2_CLK_ENABLE,
> + IMX_APBHDMA_HCLK_ENABLE,
> + IMX_ASRC_CLK_ENABLE,
> + IMX_CAAM_SECURE_MEM_CLK_ENABLE,
> + IMX_CAAM_WRAPPER_ACLK_ENABLE,
> + IMX_CAAM_WRAPPER_IPG_ENABLE,
> + IMX_CAN1_CLK_ENABLE,
> + IMX_CAN1_SERIAL_CLK_ENABLE,
> + IMX_CAN2_CLK_ENABLE,
> + IMX_CAN2_SERIAL_CLK_ENABLE,
> + IMX_ARM_DBG_CLK_ENABLE,
> + IMX_DCIC1_CLK_ENABLE,
> + IMX_DCIC2_CLK_ENABLE,
> + IMX_DTCP_CLK_ENABLE,
> + IMX_ECSPI1_CLK_ENABLE,
> + IMX_ECSPI2_CLK_ENABLE,
> + IMX_ECSPI3_CLK_ENABLE,
> + IMX_ECSPI4_CLK_ENABLE,
> + IMX_ECSPI5_CLK_ENABLE,
> + IMX_ENET_CLK_ENABLE,
> + IMX_EPIT1_CLK_ENABLE,
> + IMX_EPIT2_CLK_ENABLE,
> + IMX_ESAI_CLK_ENABLE,
> + IMX_GPT_CLK_ENABLE,
> + IMX_GPT_SERIAL_CLK_ENABLE,
> + IMX_GPU2D_CLK_ENABLE,
> + IMX_GPU3D_CLK_ENABLE,
> + IMX_HDMI_TX_ENABLE,
> + IMX_HDMI_TX_ISFRCLK_ENABLE,
> + IMX_I2C1_SERIAL_CLK_ENABLE,
> + IMX_I2C2_SERIAL_CLK_ENABLE,
> + IMX_I2C3_SERIAL_CLK_ENABLE,
> + IMX_I2C4_SERIAL_CLK_ENABLE,
> + IMX_IIM_CLK_ENABLE,
> + IMX_IOMUX_IPT_CLK_IO_ENABLE,
> + IMX_IPMUX1_CLK_ENABLE,
> + IMX_IPMUX2_CLK_ENABLE,
> + IMX_IPMUX3_CLK_ENABLE,
> + IMX_IPSYNC_IP2APB_TZASC1_IPG_MASTER_CLK_ENABLE,
> + IMX_IPSYNC_IP2APB_TZASC2_IPG_MASTER_CLK_ENABLE,
> + IMX_IPSYNC_VDOA_IPG_MASTER_CLK_ENABLE,
> + IMX_IPU1_CLK_ENABLE,
> + IMX_IPU1_DI0_CLK_ENABLE,
> + IMX_IPU1_DI1_CLK_ENABLE,
> + IMX_LDB_DI0_CLK_ENABLE,
> + IMX_LDB_DI1_CLK_ENABLE,
> + IMX_MIPI_CORE_CFG_CLK_ENABLE,
> + IMX_MLB_CLK_ENABLE,
> + IMX_MMDC_CORE_ACLK_FAST_CORE_P0_ENABLE,
> + IMX_MMDC_CORE_IPG_CLK_P0_ENABLE,
> + IMX_OCRAM_CLK_ENABLE,
> + IMX_OPENVGAXICLK_CLK_ROOT_ENABLE,
> + IMX_PCIE_ROOT_ENABLE,
> + IMX_PL301_MX6QFAST1_S133CLK_ENABLE,
> + IMX_PL301_MX6QPER1_BCHCLK_ENABLE,
> + IMX_PL301_MX6QPER2_MAINCLK_ENABLE,
> + IMX_PWM1_CLK_ENABLE,
> + IMX_PWM2_CLK_ENABLE,
> + IMX_PWM3_CLK_ENABLE,
> + IMX_PWM4_CLK_ENABLE,
> + IMX_RAWNAND_U_BCH_INPUT_APB_CLK_ENABLE,
> + IMX_RAWNAND_U_GPMI_BCH_INPUT_BCH_CLK_ENABLE,
> + IMX_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_CLK_ENABLE,
> + IMX_RAWNAND_U_GPMI_INPUT_APB_CLK_ENABLE,
> + IMX_ROM_CLK_ENABLE,
> + IMX_SATA_CLK_ENABLE,
> + IMX_SDMA_CLK_ENABLE,
> + IMX_SPBA_CLK_ENABLE,
> + IMX_SPDIF_CLK_ENABLE,
> + IMX_SSI1_CLK_ENABLE,
> + IMX_SSI2_CLK_ENABLE,
> + IMX_SSI3_CLK_ENABLE,
> + IMX_UART_CLK_ENABLE,
> + IMX_UART_SERIAL_CLK_ENABLE,
> + IMX_USBOH3_CLK_ENABLE,
> + IMX_USDHC1_CLK_ENABLE,
> + IMX_USDHC2_CLK_ENABLE,
> + IMX_USDHC3_CLK_ENABLE,
> + IMX_USDHC4_CLK_ENABLE,
> + IMX_EIM_SLOW_CLK_ENABLE,
> + IMX_VDOAXICLK_CLK_ENABLE,
> + IMX_VPU_CLK_ENABLE,
> + IMX_CLK_GATE_MAX,
> +} IMX_CLK_GATE;
> +
> +#endif /* _IMX6_CLK_PWR_SDL_H_ */
> diff --git a/Silicon/NXP/iMX6Pkg/Include/iMX6ClkPwr_SX.h b/Silicon/NXP/iMX6Pkg/Include/iMX6ClkPwr_SX.h
> new file mode 100644
> index 000000000000..8b03f5e45b00
> --- /dev/null
> +++ b/Silicon/NXP/iMX6Pkg/Include/iMX6ClkPwr_SX.h
> @@ -0,0 +1,190 @@
> +/** @file
> +*
> +* Copyright (c) 2018 Microsoft Corporation. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#ifndef _IMX6_CLK_PWR_SX_H_
> +#define _IMX6_CLK_PWR_SX_H_
> +
> +// Clock signal definitions
> +// Figure 19-2 Clock Tree
> +typedef enum {
> + IMX_CLK_NONE,
> + IMX_OSC_CLK,
> + IMX_PLL1_MAIN_CLK,
> + IMX_PLL2_MAIN_CLK,
> + IMX_PLL2_PFD0,
> + IMX_PLL2_PFD1,
> + IMX_PLL2_PFD2,
> + IMX_PLL2_PFD3,
> + IMX_PLL3_MAIN_CLK,
> + IMX_PLL3_PFD0,
> + IMX_PLL3_PFD1,
> + IMX_PLL3_PFD2,
> + IMX_PLL3_PFD3,
> + IMX_PLL4_MAIN_CLK,
> + IMX_PLL5_MAIN_CLK,
> + IMX_CLK1,
> + IMX_CLK2,
> + IMX_PLL1_SW_CLK,
> + IMX_STEP_CLK,
> + IMX_PLL3_SW_CLK,
> + IMX_PERIPH_CLK2,
> + IMX_PERIPH_CLK,
> + IMX_PRE_PERIPH_CLK,
> + IMX_ARM_CLK_ROOT,
> + IMX_MMDC_CLK_ROOT,
> + IMX_FABRIC_CLK_ROOT,
> + IMX_OCRAM_CLK_ROOT,
> + IMX_PCIE_CLK_ROOT,
> + IMX_AHB_CLK_ROOT,
> + IMX_PERCLK_CLK_ROOT,
> + IMX_IPG_CLK_ROOT,
> + IMX_USDHC1_CLK_ROOT,
> + IMX_USDHC2_CLK_ROOT,
> + IMX_USDHC3_CLK_ROOT,
> + IMX_USDHC4_CLK_ROOT,
> + IMX_ACLK_EIM_SLOW_CLK_ROOT,
> + IMX_GPU_AXI_CLK_ROOT,
> + IMX_GPU_CORE_CLK_ROOT,
> + IMX_VID_CLK_ROOT,
> + IMX_ESAI_CLK_ROOT,
> + IMX_AUDIO_CLK_ROOT,
> + IMX_SPDIF0_CLK_ROOT,
> + IMX_SSI1_CLK_ROOT,
> + IMX_SSI2_CLK_ROOT,
> + IMX_SSI3_CLK_ROOT,
> + IMX_LCDIF2_PIX_CLK_ROOT,
> + IMX_LCDIF1_PIX_CLK_ROOT,
> + IMX_LVDS_CLK_ROOT,
> + IMX_M4_CLK_ROOT,
> + IMX_ENET_CLK_ROOT,
> + IMX_QSPI1_CLK_ROOT,
> + IMX_QSPI2_CLK_ROOT,
> + IMX_DISPLAY_CLK_ROOT,
> + IMX_CSI_CLK_ROOT,
> + IMX_CAN_CLK_ROOT,
> + IMX_ECSPI_CLK_ROOT,
> + IMX_UART_CLK_ROOT,
> + IMX_CLK_MAX,
> +} IMX_CLK;
> +
> +// Clock gate definitions
> +typedef enum {
> + IMX_AIPS_TZ1_CLK_ENABLE,
> + IMX_AIPS_TZ2_CLK_ENABLE,
> + IMX_APBHDMA_HCLK_ENABLE,
> + IMX_ASRC_CLK_ENABLE,
> + IMX_CAAM_SECURE_MEM_CLK_ENABLE,
> + IMX_CAAM_WRAPPER_ACLK_ENABLE,
> + IMX_CAAM_WRAPPER_IPG_ENABLE,
> + IMX_CAN1_CLK_ENABLE,
> + IMX_CAN1_SERIAL_CLK_ENABLE,
> + IMX_CAN2_CLK_ENABLE,
> + IMX_CAN2_SERIAL_CLK_ENABLE,
> + IMX_ARM_DBG_CLK_ENABLE,
> + IMX_DCIC1_CLK_ENABLE,
> + IMX_DCIC2_CLK_ENABLE,
> + IMX_AIPS_TZ3_CLK_ENABLE,
> + IMX_ECSPI1_CLK_ENABLE,
> + IMX_ECSPI2_CLK_ENABLE,
> + IMX_ECSPI3_CLK_ENABLE,
> + IMX_ECSPI4_CLK_ENABLE,
> + IMX_ECSPI5_CLK_ENABLE,
> + IMX_EPIT1_CLK_ENABLE,
> + IMX_EPIT2_CLK_ENABLE,
> + IMX_ESAI_CLK_ENABLE,
> + IMX_WAKEUP_CLK_ENABLE,
> + IMX_GPT_CLK_ENABLE,
> + IMX_GPT_SERIAL_CLK_ENABLE,
> + IMX_GPU_CLK_ENABLE,
> + IMX_OCRAM_S_CLK_ENABLE,
> + IMX_CANFD_CLK_ENABLE,
> + IMX_CSI_CLK_ENABLE,
> + IMX_I2C1_SERIAL_CLK_ENABLE,
> + IMX_I2C2_SERIAL_CLK_ENABLE,
> + IMX_I2C3_SERIAL_CLK_ENABLE,
> + IMX_IIM_CLK_ENABLE,
> + IMX_IOMUX_IPT_CLK_IO_ENABLE,
> + IMX_IPMUX1_CLK_ENABLE,
> + IMX_IPMUX2_CLK_ENABLE,
> + IMX_IPMUX3_CLK_ENABLE,
> + IMX_IPSYNC_IP2APB_TZASC1_IPG_MASTER_CLK_ENABLE,
> + IMX_LCD_CLK_ENABLE,
> + IMX_PXP_CLK_ENABLE,
> + IMX_M4_CLK_ENABLE,
> + IMX_ENET_CLK_ENABLE,
> + IMX_DISP_AXI_CLK_ENABLE,
> + IMX_LCDIF2_PIX_CLK_ENABLE,
> + IMX_LCDIF1_PIX_CLK_ENABLE,
> + IMX_LDB_DI0_CLK_ENABLE,
> + IMX_QSPI1_CLK_ENABLE,
> + IMX_MLB_CLK_ENABLE,
> + IMX_MMDC_CORE_ACLK_FAST_CORE_P0_ENABLE,
> + IMX_MMDC_CORE_IPG_CLK_P0_ENABLE,
> + IMX_MMDC_CORE_IPG_CLK_P1_ENABLE,
> + IMX_OCRAM_CLK_ENABLE,
> + IMX_PCIE_ROOT_ENABLE,
> + IMX_QSPI2_CLK_ENABLE,
> + IMX_PL301_MX6QPER1_BCHCLK_ENABLE,
> + IMX_PL301_MX6QPER2_MAINCLK_ENABLE,
> + IMX_PWM1_CLK_ENABLE,
> + IMX_PWM2_CLK_ENABLE,
> + IMX_PWM3_CLK_ENABLE,
> + IMX_PWM4_CLK_ENABLE,
> + IMX_RAWNAND_U_BCH_INPUT_APB_CLK_ENABLE,
> + IMX_RAWNAND_U_GPMI_BCH_INPUT_BCH_CLK_ENABLE,
> + IMX_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_CLK_ENABLE,
> + IMX_RAWNAND_U_GPMI_INPUT_APB_CLK_ENABLE,
> + IMX_ROM_CLK_ENABLE,
> + IMX_SDMA_CLK_ENABLE,
> + IMX_SPBA_CLK_ENABLE,
> + IMX_SPDIF_AND_AUDIO_CLK_ENABLE,
> + IMX_SSI1_CLK_ENABLE,
> + IMX_SSI2_CLK_ENABLE,
> + IMX_SSI3_CLK_ENABLE,
> + IMX_UART_CLK_ENABLE,
> + IMX_UART_SERIAL_CLK_ENABLE,
> + IMX_SAI1_CLK_ENABLE,
> + IMX_SAI2_CLK_ENABLE,
> + IMX_USBOH3_CLK_ENABLE,
> + IMX_USDHC1_CLK_ENABLE,
> + IMX_USDHC2_CLK_ENABLE,
> + IMX_USDHC3_CLK_ENABLE,
> + IMX_USDHC4_CLK_ENABLE,
> + IMX_EIM_SLOW_CLK_ENABLE,
> + IMX_PWM8_CLK_ENABLE,
> + IMX_VADC_CLK_ENABLE,
> + IMX_GIS_CLK_ENABLE,
> + IMX_I2C4_SERIAL_CLK_ENABLE,
> + IMX_PWM5_CLK_ENABLE,
> + IMX_PWM6_CLK_ENABLE,
> + IMX_PWM7_CLK_ENABLE,
> + IMX_CLK_GATE_MAX,
> +} IMX_CLK_GATE;
> +
> +VOID
> +ImxClkPwrLcdClockDisable (
> + VOID
> + );
> +
> +VOID
> +ImxClkPwrLcdClockEnable (
> + VOID
> + );
> +
> +EFI_STATUS
> +ImxSetLcdIfClockRate (
> + IN UINT32 ClockRate
> + );
> +
> +#endif /* _IMX6_CLK_PWR_SX_H_ */
> diff --git a/Silicon/NXP/iMX6Pkg/Include/iMX6IoMux.h b/Silicon/NXP/iMX6Pkg/Include/iMX6IoMux.h
> new file mode 100644
> index 000000000000..30c859529a44
> --- /dev/null
> +++ b/Silicon/NXP/iMX6Pkg/Include/iMX6IoMux.h
> @@ -0,0 +1,202 @@
> +/** @file
> +*
> +* Copyright (c) 2018 Microsoft Corporation. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#ifndef _IMX6_IOMUX_H_
> +#define _IMX6_IOMUX_H_
> +
> +//
> +// IOMux common definition
> +//
> +#include <iMXIoMux.h>
> +
> +//
> +// GPIO common definition
> +//
> +#include <iMXGpio.h>
> +
> +#if defined(CPU_IMX6DQ) || defined (CPU_IMX6DQP)
> +#include "iMX6IoMux_DQP.h"
> +#elif defined(CPU_IMX6SX)
> +#include "iMX6IoMux_SX.h"
> +#elif defined(CPU_IMX6SDL)
> +#include "iMX6IoMux_SDL.h"
> +#else
> +#error CPU Preprocessor Flag Not Defined
> +#endif
> +
> +typedef UINT64 IMX_PADCFG;
> +
> +//
> +// Pad control settings
> +//
> +typedef enum {
> + IMX_HYS_DISABLED,
> + IMX_HYS_ENABLED,
> +} IMX_HYS;
> +
> +typedef enum {
> + IMX_PUS_100K_OHM_PD,
> + IMX_PUS_47K_OHM_PU,
> + IMX_PUS_100K_OHM_PU,
> + IMX_PUS_22K_OHM_PU,
> +} IMX_PUS;
> +
> +typedef enum {
> + IMX_PUE_KEEP,
> + IMX_PUE_PULL,
> +} IMX_PUE;
> +
> +typedef enum {
> + IMX_PKE_DISABLE,
> + IMX_PKE_ENABLE,
> +} IMX_PKE;
> +
> +typedef enum {
> + IMX_ODE_DISABLE,
> + IMX_ODE_ENABLE,
> +} IMX_ODE;
> +
> +typedef enum {
> + IMX_SPEED_LOW,
> + IMX_SPEED_MEDIUM = 2,
> + IMX_SPEED_MAXIMUM,
> +} IMX_SPEED;
> +
> +typedef enum {
> + IMX_DSE_HIZ,
> + IMX_DSE_260_OHM,
> + IMX_DSE_130_OHM,
> + IMX_DSE_90_OHM,
> + IMX_DSE_60_OHM,
> + IMX_DSE_50_OHM,
> + IMX_DSE_40_OHM,
> + IMX_DSE_33_OHM,
> +} IMX_DSE;
> +
> +typedef enum {
> + IMX_SRE_SLOW,
> + IMX_SRE_FAST,
> +} IMX_SRE;
> +
> +typedef enum {
> + IMX_SION_DISABLED,
> + IMX_SION_ENABLED,
> +} IMX_IOMUXC_CTL_SION;
> +
> +typedef union {
> + UINT32 AsUint32;
My brain cannot decide whether it's properly pointed this out in any
patch, or if I just put it in my draft for an earlier file that I then
discarded. Tardy reviewing helps no one :(
Anyway:
Please replace all these "As<type>" with "Raw" or "Data".
> + struct {
> + UINT32 SRE : 1;
> + UINT32 reserved0 : 2;
> + UINT32 DSE : 3;
> + UINT32 SPEED : 2;
> + UINT32 reserved1 : 3;
> + UINT32 ODE : 1 ;
> + UINT32 PKE : 1;
> + UINT32 PUE : 1;
> + UINT32 PUS : 2;
> + UINT32 HYS : 1;
> + UINT32 reserved2 : 15;
> + } Fields;
> +} IMX_IOMUXC_PAD_CTL;
None of these struct members follow the coding style.
The reserved ones are easy, just -> Reserved*.
For the rest, The abbreviations would appear to violate the coding
style (if not accompanied by a glossary at the start of the file), and
the names should normally be in CamelCase.
Are these the names they are referred to in the documentation?
Every comment I would have on this file follows this pattern, so I'm
stopping here. If we could agree on the way forward for this struct,
the same would apply for the rest of the file.
Regards,
Leif
next prev parent reply other threads:[~2018-12-13 17:12 UTC|newest]
Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-21 8:25 [PATCH edk2-platforms 00/27] Import Hummingboard Edge platform for Windows IoT Core Chris Co
2018-09-21 8:25 ` [PATCH edk2-platforms 01/27] Platform/Microsoft: Add OpteeClientPkg dec Chris Co
2018-10-31 20:43 ` Leif Lindholm
2018-11-01 10:55 ` Sumit Garg
2018-11-02 0:41 ` Chris Co
2018-11-02 5:24 ` Sumit Garg
2018-11-02 23:55 ` Chris Co
2018-11-05 10:07 ` Sumit Garg
2018-11-06 1:53 ` Chris Co
2018-11-06 11:09 ` Sumit Garg
2018-09-21 8:25 ` [PATCH edk2-platforms 02/27] Platform/Microsoft: Add SdMmc Dxe Driver Chris Co
2018-09-21 8:25 ` [PATCH edk2-platforms 04/27] Silicon/NXP: Add iMXPlatformPkg dec Chris Co
2018-09-21 8:25 ` [PATCH edk2-platforms 03/27] Platform/Microsoft: Add MsPkg Chris Co
2018-10-31 21:00 ` Leif Lindholm
2018-09-21 8:25 ` [PATCH edk2-platforms 05/27] Silicon/NXP: Add UART library support for i.MX platforms Chris Co
2018-11-01 8:59 ` Leif Lindholm
2018-11-02 1:46 ` Chris Co
2018-09-21 8:25 ` [PATCH edk2-platforms 06/27] Silicon/NXP: Add I2C " Chris Co
2018-11-01 17:53 ` Leif Lindholm
2018-09-21 8:25 ` [PATCH edk2-platforms 07/27] Silicon/NXP: Add i.MX display library support Chris Co
2018-11-01 18:05 ` Leif Lindholm
2018-11-29 0:55 ` Chris Co
2018-09-21 8:25 ` [PATCH edk2-platforms 08/27] Silicon/NXP: Add Virtual RTC support for i.MX platform Chris Co
2018-12-15 13:26 ` Leif Lindholm
2018-09-21 8:26 ` [PATCH edk2-platforms 09/27] Silicon/NXP: Add headers for SoC-specific i.MX packages to use Chris Co
2018-11-01 18:20 ` Leif Lindholm
2018-12-01 0:22 ` Chris Co
2018-12-03 9:42 ` Leif Lindholm
2018-12-04 1:44 ` Chris Co
2018-12-04 9:33 ` Ard Biesheuvel
2018-12-04 12:22 ` Leif Lindholm
2018-09-21 8:26 ` [PATCH edk2-platforms 10/27] Silicon/NXP: Add iMX6Pkg dec Chris Co
2018-11-01 18:25 ` Leif Lindholm
2018-09-21 8:26 ` [PATCH edk2-platforms 11/27] Silicon/NXP: Add i.MX6 SoC header files Chris Co
2018-12-13 17:11 ` Leif Lindholm [this message]
2018-09-21 8:26 ` [PATCH edk2-platforms 12/27] Silicon/NXP: Add i.MX6 I/O MUX library Chris Co
2018-11-08 18:00 ` Leif Lindholm
2018-12-04 1:41 ` Chris Co
2018-09-21 8:26 ` [PATCH edk2-platforms 13/27] Silicon/NXP: Add support for iMX SDHC Chris Co
2018-12-05 10:31 ` Leif Lindholm
2018-09-21 8:26 ` [PATCH edk2-platforms 14/27] Silicon/NXP: Add i.MX6 GPT and EPIT timer headers Chris Co
2018-11-08 18:14 ` Leif Lindholm
2018-12-04 2:06 ` Chris Co
2018-12-04 12:58 ` Leif Lindholm
2018-09-21 8:26 ` [PATCH edk2-platforms 15/27] Silicon/NXP: Add i.MX6 GPT Timer library Chris Co
2018-12-13 17:26 ` Leif Lindholm
2018-09-21 8:26 ` [PATCH edk2-platforms 16/27] Silicon/NXP: Add i.MX6 Timer DXE driver Chris Co
2018-12-13 17:33 ` Leif Lindholm
2018-09-21 8:26 ` [PATCH edk2-platforms 17/27] Silicon/NXP: Add i.MX6 USB Phy Library Chris Co
2018-12-14 17:10 ` Leif Lindholm
2018-09-21 8:26 ` [PATCH edk2-platforms 18/27] Silicon/NXP: Add i.MX6 Clock Library Chris Co
2018-12-14 18:12 ` Leif Lindholm
2018-09-21 8:26 ` [PATCH edk2-platforms 19/27] Silicon/NXP: Add i.MX6 ACPI tables Chris Co
2018-12-14 19:53 ` Leif Lindholm
2018-12-17 11:14 ` Ard Biesheuvel
2019-01-08 21:43 ` Chris Co
2019-01-29 14:09 ` Ard Biesheuvel
2018-09-21 8:26 ` [PATCH edk2-platforms 20/27] Silicon/NXP: Add i.MX6 Board init library Chris Co
2018-12-14 20:12 ` Leif Lindholm
2018-09-21 8:26 ` [PATCH edk2-platforms 21/27] Silicon/NXP: Add i.MX6 PCIe DXE driver Chris Co
2018-12-14 21:59 ` Leif Lindholm
2018-09-21 8:26 ` [PATCH edk2-platforms 22/27] Silicon/NXP: Add i.MX6 GOP driver Chris Co
2018-12-14 22:37 ` Leif Lindholm
2018-09-21 8:26 ` [PATCH edk2-platforms 23/27] Silicon/NXP: Add i.MX6 Smbios Driver Chris Co
2018-12-14 23:07 ` Leif Lindholm
2018-09-21 8:26 ` [PATCH edk2-platforms 24/27] Silicon/NXP: Add i.MX6 common dsc and fdf files Chris Co
2018-12-14 23:36 ` Leif Lindholm
2018-09-21 8:26 ` [PATCH edk2-platforms 25/27] Platform/Solidrun: Add Hummingboard Peripheral Initialization Chris Co
2018-12-15 12:12 ` Leif Lindholm
2018-09-21 8:26 ` [PATCH edk2-platforms 26/27] Platform/SolidRun: Add i.MX 6Quad Hummingboard Edge ACPI tables Chris Co
2018-12-15 12:19 ` Leif Lindholm
2018-09-21 8:26 ` [PATCH edk2-platforms 27/27] Platform/Solidrun: Add i.MX 6Quad Hummingboard Edge dsc and fdf files Chris Co
2018-12-15 12:28 ` Leif Lindholm
2018-12-15 13:32 ` [PATCH edk2-platforms 00/27] Import Hummingboard Edge platform for Windows IoT Core Leif Lindholm
2018-12-19 18:28 ` Chris Co
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