From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::344; helo=mail-wm1-x344.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm1-x344.google.com (mail-wm1-x344.google.com [IPv6:2a00:1450:4864:20::344]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A13B8211A1E3A for ; Fri, 14 Dec 2018 11:53:50 -0800 (PST) Received: by mail-wm1-x344.google.com with SMTP id n190so6806974wmd.0 for ; Fri, 14 Dec 2018 11:53:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=Y3W5RgpdS0/8N6B+kb9A5qw3bwgFPmN/GBhMGObuoPY=; b=SogMkgjV2hwh3vuoh0bkXOtqFz5EWRKNBE/doShjBTJnaEbXlSmWpT5wuwuSeoxOg+ oLgovbhfEqge7LeuSsrIfjr4m6RkJ95qRCBEwj3Tg54XKFGdadNzNTJ+NV+6jhCwSkQM a4pPu72sLBzAcp+dDgZsE25PxpD5Yv82c3IC0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=Y3W5RgpdS0/8N6B+kb9A5qw3bwgFPmN/GBhMGObuoPY=; b=h+7O90oI8nnthFj5yllFSvrGG51GthG8k3ONFu6pbidzFG7xOuzt99vaAZVxg8+etW keuK7bK6RDogHbwAuuSMrRVg8Hzuyx8Do/yA8Bd8T/QTQu4IIGfGWz2isK/dmWSAVVqs hHF+1iWdPAncvr3fo3YzziOQuDYxfJzqQGyimIF7I8U5r73hYMimTK9daVMracfH6A8V AdWqewzWr6V1LagBgDlaIoUhlJglLxhwHRnzHogx6lmJw5Vy3UhGXz/gYeNgGOcTJyqu 7Aj8aVl8CmkNIfpjVurUbxETxAJqcegTEmAT1gHADEU5J/nYSV3GSIShSOFrSDjLHPEV gwKg== X-Gm-Message-State: AA+aEWYq9EsWckFh0Ep6ja99+ftCpWd/LbBg6YkgaJA221d7PWA5IDWC qcfxk3nb8bh6ahFLUuXmnC1/fTUrxBU= X-Google-Smtp-Source: AFSGD/XtghEefkumcy32QHJHCPaJ15OZw55vr7vBxiHtT+EuZuAWwdIGWWdpSZtACWWOeqCshot0Ig== X-Received: by 2002:a1c:2e0c:: with SMTP id u12mr4288870wmu.81.1544817228062; Fri, 14 Dec 2018 11:53:48 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id o15sm5110799wrp.12.2018.12.14.11.53.46 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 14 Dec 2018 11:53:46 -0800 (PST) Date: Fri, 14 Dec 2018 19:53:45 +0000 From: Leif Lindholm To: Chris Co Cc: "edk2-devel@lists.01.org" , Ard Biesheuvel , Michael D Kinney Message-ID: <20181214195345.ds2n4arhth6opkua@bivouac.eciton.net> References: <20180921082542.35768-1-christopher.co@microsoft.com> <20180921082542.35768-20-christopher.co@microsoft.com> MIME-Version: 1.0 In-Reply-To: <20180921082542.35768-20-christopher.co@microsoft.com> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms 19/27] Silicon/NXP: Add i.MX6 ACPI tables X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 14 Dec 2018 19:53:51 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Sep 21, 2018 at 08:26:12AM +0000, Chris Co wrote: > This adds baseline ACPI table support for booting Windows on > NXP i.MX6 SoCs. Platforms may override these tables as necessary. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Christopher Co > Cc: Ard Biesheuvel > Cc: Leif Lindholm > Cc: Michael D Kinney > --- > Silicon/NXP/iMX6Pkg/AcpiTables/Csrt.aslc | 408 ++++++++++++++++++++ > Silicon/NXP/iMX6Pkg/AcpiTables/Dbg2.aslc | 142 +++++++ > Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Common.h | 106 +++++ > Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Enet.asl | 106 +++++ > Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Gfx.asl | 74 ++++ > Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Gpio.asl | 55 +++ > Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-I2c.asl | 67 ++++ > Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-PCIe.asl | 298 ++++++++++++++ > Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Platform.asl | 106 +++++ > Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Pwm.asl | 85 ++++ > Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Sdhc.asl | 133 +++++++ > Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Spi.asl | 103 +++++ > Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-TrEE.asl | 33 ++ > Silicon/NXP/iMX6Pkg/AcpiTables/Fadt.aslc | 60 +++ > Silicon/NXP/iMX6Pkg/AcpiTables/Madt.aslc | 120 ++++++ > Silicon/NXP/iMX6Pkg/AcpiTables/Mcfg.aslc | 92 +++++ > Silicon/NXP/iMX6Pkg/AcpiTables/Spcr.aslc | 95 +++++ > Silicon/NXP/iMX6Pkg/AcpiTables/Tpm2.aslc | 53 +++ > 18 files changed, 2136 insertions(+) Shouldn't there be a .inf in this patch as well? Oh, no, this is used as an include directory, and ... hmm. This gets a bit grotty later. Ard, could you suggest a better way of laying this out? > > diff --git a/Silicon/NXP/iMX6Pkg/AcpiTables/Csrt.aslc b/Silicon/NXP/iMX6Pkg/AcpiTables/Csrt.aslc > new file mode 100644 > index 000000000000..82c2420a2b7e > --- /dev/null > +++ b/Silicon/NXP/iMX6Pkg/AcpiTables/Csrt.aslc > @@ -0,0 +1,408 @@ > +/** @file > +* > +* Copyright (c) 2018 Microsoft Corporation. All rights reserved. > +* > +* This program and the accompanying materials > +* are licensed and made available under the terms and conditions of the BSD License > +* which accompanies this distribution. The full text of the license may be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +* > +**/ > + > +#include "../Include/Platform.h" > +#include "../Include/iMX6.h" #include #include should just work here, since any user must declare use of Silicon/NXP/iMX6Pkg/iMX6Pkg.dec anyway, and that puts the package Include in the include path. > + > +#pragma pack(push, iMX6Csrt, 1) > + > +// Timer Resource Group > +// Each timer consumes 4K of address space. > +#define TIMER_ADDRES_SIZE 0x1000 > +#define TIMER_CAP_ALWAYS_ON 0x00000001 // Timer is always ON. > +#define TIMER_CAP_UP_COUNTER 0x00000002 // Up counter vs. down counter (0) > +#define TIMER_CAP_READABLE 0x00000004 // Counter has a software interface. > +#define TIMER_CAP_PERIODIC 0x00000008 // Can generate periodic interrupts. > +#define TIMER_CAP_DRIVES_IRQ 0x00000010 // Timer interrupt drives a physical IRQ. > +#define TIMER_CAP_ONE_SHOT 0x00000020 // Counter can generate one-shot interrupts > + > +// Timer source clock codes > +typedef enum { > + GPT_CLOCK_NONE = 0, > + GPT_CLOCK_PERIPHERAL = 1, > + GPT_CLOCK_HI_FREQ = 2, > + GPT_CLOCK_EXT = 3, > + GPT_CLOCK_LOW_FREQ = 4, > +#if defined(CPU_IMX6DQ) || defined (CPU_IMX6DQP) > + GPT_CLOCK_OSC_DIV_8 = 5, > + GPT_CLOCK_OSC = 7, > +#elif (defined(CPU_IMX6SDL) || defined(CPU_IMX6SX)) > + GPT_CLOCK_OSC = 5, > +#else > +#error iMX6 CPU Type Not Defined (Preprocessor Flag) > +#endif > +} GPT_SOURCE_CLOCK; > + > +// EPIT timer source clock codes > +typedef enum { > + EPIT_CLOCK_NONE = 0, > + EPIT_CLOCK_PERIPHERAL = 1, > + EPIT_CLOCK_HI_FREQ = 2, > + EPIT_CLOCK_LOW_FREQ = 3, > +} EPIT_SOURCE_CLOCK; > + > +// Timer descriptor > +typedef struct { > + EFI_ACPI_5_0_CSRT_RESOURCE_DESCRIPTOR_HEADER Header; > + UINT32 Capabilities; > + UINT32 Width; > + UINT32 Source; > + UINT32 Frequency; > + UINT32 FrequencyScale; > + UINT32 BaseAddress; > + UINT32 Size; > + UINT32 Interrupt; > + UINT32 ChipType; > +} RD_TIMER; > + > +// Resource Group Shared Info > +typedef struct { > + UINT16 RevMajor; > + UINT16 RevMinor; > + UINT32 ChipType; > +} RG_PLATFORM_INFORMATION; > + > +// Timer group descriptor > +typedef struct { > + EFI_ACPI_5_0_CSRT_RESOURCE_GROUP_HEADER Header; > + RG_PLATFORM_INFORMATION PlatformInfo; > +#if defined(CPU_IMX6SDL) > + RD_TIMER Timers[3]; > +#else > + RD_TIMER Timers[4]; > +#endif > +} RG_TIMER; > + > +// PL310 L2 Cache Controller Resource Group > +#define CSRT_PL310_MINIMUM_VERSION 1 > +#define CSRT_PL310_VERSION_2 2 > +#define CSRT_PL310_RAW_PROTOCOL 0 > +#define CSRT_PL310_SMC_PROTOCOL 1 > + > +// We use PSCI_CPU_ON to turn on the L2 cache, with special value > +// 0x00100000 for the Core ID. PSCI sees this core ID and knows > +// this is an L2 cache operation, then looks at R2 for the > +// operation to perform. > +#define PSCI_FID_CPU_ON 0x84000003 > +#define L2CACHE_SMC_R1 0x00100000 > +#define L2CACHE_OP_ENABLE 1 > +#define L2CACHE_OP_DISABLE 2 > +#define L2CACHE_OP_ENABLE_WRITEBACK 3 > +#define L2CACHE_OP_DISABLE_WRITEBACK 4 > +#define L2CACHE_OP_ENABLE_WFLZ 5 > + > +typedef struct { > + UINT32 Immediate; > + UINT32 R0; > + UINT32 R1; > + UINT32 R2; > + UINT32 R3; > + UINT32 R12; > +} CSRT_SMC_INVOCATION_BLOCK; > + > +// L2 cache descriptor > +typedef struct { > + EFI_ACPI_5_0_CSRT_RESOURCE_DESCRIPTOR_HEADER Header; > + UINT32 Version; > + UINT32 ManagementProtocol; > + UINT64 Address; > + CSRT_SMC_INVOCATION_BLOCK InvokeEnable; > + CSRT_SMC_INVOCATION_BLOCK InvokeDisable; > + CSRT_SMC_INVOCATION_BLOCK InvokeEnableWriteback; > + CSRT_SMC_INVOCATION_BLOCK InvokeDisableWriteback; > + CSRT_SMC_INVOCATION_BLOCK InvokeEnableWFLZ; > +} RD_L2_CACHE; > + > +// PL310 L2 cache controller descriptor > +typedef struct { > + EFI_ACPI_5_0_CSRT_RESOURCE_GROUP_HEADER Header; > + RD_L2_CACHE L2Cache; > +} RG_L2_CACHE; > + > +// SmartDMA (SDMA) Controller Resource Group > +enum IMX_SDMA_CORE_CLOCK_RATIO { > + IMX_SDMA_CORE_CLOCK_TWICE_CORE_FREQ = 0, > + IMX_SDMA_CORE_CLOCK_EQUALS_CORE_FREQ = 1 > +}; > + > +// SDMA controller descriptor > +typedef struct { > + EFI_ACPI_5_0_CSRT_RESOURCE_DESCRIPTOR_HEADER Header; > + UINT32 ChipType; // IMX_CHIP_TYPE > + UINT64 RegistersBaseAddress; > + UINT64 IoMuxGPR0Address; > + UINT32 Interrupt; > + UINT32 SdmaCoreClockRatio; // IMX_SDMA_CORE_CLOCK_RATIO > +} RD_SDMA; > + > +// SDMA controller group descriptor > +typedef struct { > + EFI_ACPI_5_0_CSRT_RESOURCE_GROUP_HEADER Header; > + RD_SDMA Sdma; > +} RG_SDMA; > + > + > +// CSRT structure for this platform > +typedef struct { > + EFI_ACPI_DESCRIPTION_HEADER CsrtHeader; // Standard ACPI Header > + RG_TIMER TimerResourceGroup; // Timer Resource Group > +#ifndef CONFIG_L2CACHE_OFF > + RG_L2_CACHE L2CacheResourceGroup; // PL310 L2 Cache Resource Group > +#endif > + RG_SDMA SdmaResourceGroup; // SDMA Resource Group > +} EFI_ACPI_CSRT_TABLE; > + > +#pragma pack (pop, iMX6Csrt) > + > +EFI_ACPI_CSRT_TABLE Csrt = { > + // CSRT Header > + { > + EFI_ACPI_5_0_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE, // Signature "CSRT" > + sizeof (EFI_ACPI_DESCRIPTION_HEADER) + // Length > + sizeof (RG_TIMER) > +#ifndef CONFIG_L2CACHE_OFF > + + sizeof (RG_L2_CACHE) > +#endif > + + sizeof (RG_SDMA), > + EFI_ACPI_5_0_CSRT_REVISION, // Revision > + 0x00, // Checksum calculated at runtime. > + EFI_ACPI_OEM_ID, // OEMID is a 6 bytes long field. > + EFI_ACPI_OEM_TABLE_ID, // OEM table identification(8 bytes long). > + EFI_ACPI_OEM_REVISION, // OEM revision number. > + EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID. > + EFI_ACPI_CREATOR_REVISION, // ASL compiler revision number. > + }, > + > + // TimerResourceGroup > + { > + // Timer group header > + { > + sizeof (RG_TIMER), // Resource Group Length > + EFI_ACPI_VENDOR_ID, // VendorId > + 0, // SubvendorId > + 0x0101, // DeviceId > + 0, // SubdeviceId > + 0, // Revision > + 0, // Reserved > + sizeof (RG_PLATFORM_INFORMATION) // Platform Information shared info > + }, > + > + // Platform Information > + { > + 0x0001, // RevMajor > + 0x0000, // RevMinor > + 0, // IMX_CHIP_TYPE (not used) > + }, > + > + // Timers > + { > + // Counter (GPT) > + { > + { > + sizeof (RD_TIMER), // Resource Descriptor Length > + EFI_ACPI_CSRT_RD_TYPE_TIMER, // Resource Type > + EFI_ACPI_CSRT_RD_SUBTYPE_TIMER, // Resource Subtype > + 3, // ResourceId > + }, > + TIMER_CAP_READABLE | TIMER_CAP_UP_COUNTER, // Capabilities > + 32, // Timer width (bits) > + GPT_CLOCK_OSC, // Source is 111b for QD, 101b for SDL > + SOC_OSC_FREQUENCY_REF_HZ, // Frequency 24 MHz > + 24, // divider to make 1 MHz > + CSP_BASE_REG_PA_GPT, // 32 bit Physical address > + TIMER_ADDRES_SIZE, // Size of timer address space > + 0, // N.B. No interrupt on this counter > + }, > + > + // Timer0 (EPIT1) > + { > + { > + sizeof (RD_TIMER), // Resource Descriptor Length > + EFI_ACPI_CSRT_RD_TYPE_TIMER, // Resource Type > + EFI_ACPI_CSRT_RD_SUBTYPE_TIMER, // Resource Subtype > + 4, // ResourceId > + }, > + TIMER_CAP_ONE_SHOT | TIMER_CAP_PERIODIC | // Capabilities > + TIMER_CAP_ALWAYS_ON | TIMER_CAP_DRIVES_IRQ, > + 32, // Timer width (bits) > + EPIT_CLOCK_LOW_FREQ, // Source > + SOC_LOW_FREQ_REF_HZ, // Frequency > + 1, // Frequency scale > + CSP_BASE_REG_PA_EPIT1, // 32 bit Physical address > + TIMER_ADDRES_SIZE, // Size of timer address space > + IRQ_EPIT1, // Interrupt > + }, > + > + // Timer1 (EPIT2) > + { > + { > + sizeof (RD_TIMER), // Resource Descriptor Length > + EFI_ACPI_CSRT_RD_TYPE_TIMER, // Resource Type > + EFI_ACPI_CSRT_RD_SUBTYPE_TIMER, // Resource Subtype > + 5, // ResourceId > + }, > + TIMER_CAP_ONE_SHOT | TIMER_CAP_PERIODIC | // Capabilities > + TIMER_CAP_ALWAYS_ON | TIMER_CAP_DRIVES_IRQ, > + 32, // Timer width (bits) > + EPIT_CLOCK_LOW_FREQ, // Source > + SOC_LOW_FREQ_REF_HZ, // Frequency > + 1, // Frequency scale > + CSP_BASE_REG_PA_EPIT2, // 32 bit Physical address > + TIMER_ADDRES_SIZE, // Size of timer address space > + IRQ_EPIT2, // Interrupt > + }, > + > +#if defined(CPU_IMX6DQ) > + // SNVS LP Real Time Counter > + { > + { > + sizeof (RD_TIMER), // Resource Descriptor Length > + EFI_ACPI_CSRT_RD_TYPE_TIMER, // Resource Type > + EFI_ACPI_CSRT_RD_SUBTYPE_TIMER, // Resource Subtype > + 6, // ResourceId > + }, > + TIMER_CAP_UP_COUNTER | // Capabilities > + TIMER_CAP_READABLE | > + TIMER_CAP_ALWAYS_ON, > + 47, // Timer width (bits) > + 0, // Source (NA) > + SOC_LOW_FREQ_REF_HZ, // Frequency > + 1, // Frequency scale > + IMX_SNVS_BASE, // 32 bit Physical address > + TIMER_ADDRES_SIZE, // Size of timer address space > + IMX_SNVS_IRQ, // Interrupt > + }, > +#endif > + } > + }, > + > +#ifndef CONFIG_L2CACHE_OFF > + // L2CacheResourceGroup > + { > + // L2 cache group header > + { > + sizeof (RG_L2_CACHE), // Resource Group Length > + SIGNATURE_32 ('A', 'R', 'M', 'H'), // VendorId > + SIGNATURE_32 ('A', 'R', 'M', 'H'), // SubvendorId > + 0x0310, // DeviceId > + 0, // SubdeviceId > + 0, // Revision > + 0, // Reserved > + 0 // No shared info > + }, > + > + // PL310 L2 cache controller > + { > + { > + sizeof (RD_L2_CACHE), // Resource Descriptor Length > + EFI_ACPI_CSRT_RD_TYPE_CACHE, // Resource Type > + EFI_ACPI_CSRT_RD_SUBTYPE_CACHE, // Resource Subtype > + 0, // UID > + }, > + CSRT_PL310_VERSION_2, // Version > + CSRT_PL310_SMC_PROTOCOL, // Management Protocol > + CSP_BASE_REG_PA_PL310, // 64 bit Physical address > + // InvokeEnable > + { > + 0, // Immediate > + PSCI_FID_CPU_ON, // R0 > + L2CACHE_SMC_R1, // R1 > + L2CACHE_OP_ENABLE, // R2 > + 0, // R3 > + 0, // R12 > + }, > + > + // InvokeDisable > + { > + 0, // Immediate > + PSCI_FID_CPU_ON, // R0 > + L2CACHE_SMC_R1, // R1 > + L2CACHE_OP_DISABLE, // R2 > + 0, // R3 > + 0, // R12 > + }, > + > + // InvokeEnableWriteback > + { > + 0, // Immediate > + PSCI_FID_CPU_ON, // R0 > + L2CACHE_SMC_R1, // R1 > + L2CACHE_OP_ENABLE_WRITEBACK, // R2 > + 0, // R3 > + 0, // R12 > + }, > + > + // InvokeDisableWriteback > + { > + 0, // Immediate > + PSCI_FID_CPU_ON, // R0 > + L2CACHE_SMC_R1, // R1 > + L2CACHE_OP_DISABLE_WRITEBACK, // R2 > + 0, // R3 > + 0, // R12 > + }, > + > + // InvokeEnableWFLZ > + { > + 0, // Immediate > + PSCI_FID_CPU_ON, // R0 > + L2CACHE_SMC_R1, // R1 > + L2CACHE_OP_ENABLE_WFLZ, // R2 > + 0, // R3 > + 0, // R12 > + }, > + }, > + }, > +#endif > + > + // SdmaResourceGroup > + { > + // SDMA group header > + { > + sizeof (RG_SDMA), // Resource Group Length > + EFI_ACPI_VENDOR_ID, // VendorId > + 0, // SubvendorId > + 0x0111, // DeviceId > + 0, // SubdeviceId > + 0, // Revision > + 0, // Reserved > + 0 // No shared info > + }, > + > + // SDMA controller resource > + { > + { > + sizeof (RD_SDMA), // Resource Descriptor Length > + EFI_ACPI_CSRT_RD_TYPE_DMA, // Resource Type > + EFI_ACPI_CSRT_RD_SUBTYPE_DMA_CONTROLLER, // Resource Subtype > + 0, // UID > + }, > + 0, // IMX_CHIP_TYPE (not used) > + CSP_BASE_REG_PA_SDMA, // SDMA registers base physical address > + IOMUXC_GPR_BASE_ADDRESS, // IoMuxGPR0 physical address > + IRQ_SDMA, // IRQ number > + IMX_SDMA_CORE_CLOCK_TWICE_CORE_FREQ, // DMA/SDMA Core Clock Ratio: > + }, > + } > +}; > + > +VOID* > +ReferenceAcpiTable ( > + VOID > + ) > +{ > + // Reference the table being generated to prevent the optimizer from removing the > + // data structure from the executable > + return (VOID *)&Csrt; > +} > diff --git a/Silicon/NXP/iMX6Pkg/AcpiTables/Dbg2.aslc b/Silicon/NXP/iMX6Pkg/AcpiTables/Dbg2.aslc > new file mode 100644 > index 000000000000..65ce03d470ee > --- /dev/null > +++ b/Silicon/NXP/iMX6Pkg/AcpiTables/Dbg2.aslc > @@ -0,0 +1,142 @@ > +/** @file > +* > +* Copyright (c) 2018 Microsoft Corporation. All rights reserved. > +* > +* This program and the accompanying materials > +* are licensed and made available under the terms and conditions of the BSD License > +* which accompanies this distribution. The full text of the license may be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +* > +**/ > + > +#include > + > +#include "iMX6.h" #include > + > +// DBG2 Definitions > +#pragma pack (1) > + > +typedef enum { > + DBG2_TYPE_SERIAL = 0x8000, > + DBG2_TYPE_1394, > + DBG2_TYPE_USB, > + DBG2_TYPE_NET > +} DBG2_PORT_TYPE; > + > +#define EFI_ACPI_DEBUG_PORT_2_TABLE_REVISION 0x00000000 > +#define UART_NAME_SPACE_STRING_LENGTH sizeof("\\_SB.UAR1") > +#define UART_IMX6_UART_ADDRESS_SIZE 0x000000BC > + > +#if FixedPcdGet32(PcdKdUartInstance) == 1 > +#define KD_UART_BASE_ADDR CSP_BASE_REG_PA_UART1 > +#define KD_UART_ACPI_PATH "\\_SB.UAR1" > +#elif FixedPcdGet32(PcdKdUartInstance) == 2 > +#define KD_UART_BASE_ADDR CSP_BASE_REG_PA_UART2 > +#define KD_UART_ACPI_PATH "\\_SB.UAR2" > +#elif FixedPcdGet32(PcdKdUartInstance) == 3 > +#define KD_UART_BASE_ADDR CSP_BASE_REG_PA_UART3 > +#define KD_UART_ACPI_PATH "\\_SB.UAR3" > +#elif FixedPcdGet32(PcdKdUartInstance) == 4 > +#define KD_UART_BASE_ADDR CSP_BASE_REG_PA_UART4 > +#define KD_UART_ACPI_PATH "\\_SB.UAR4" > +#elif FixedPcdGet32(PcdKdUartInstance) == 5 > +#define KD_UART_BASE_ADDR CSP_BASE_REG_PA_UART5 > +#define KD_UART_ACPI_PATH "\\_SB.UAR5" > +#else > +#error "Invalid PcdKdUartInstance. Must be 1, 2, 3, 4, or 5" > +#endif > + > +// ACPI 5.0 DBG2 structure > +typedef struct { > + EFI_ACPI_DESCRIPTION_HEADER Header; > + UINT32 OffsetDbgDeviceInfo; > + UINT32 NumberDbgdeviceInfo; > +} EFI_ACPI_5_0_DEBUG_PORT_2_TABLE_HEADER; > + > +typedef struct { > + UINT8 Revision; > + UINT16 Length; > + UINT8 NumberofGenericAddressRegisters; > + UINT16 NameSpaceStringLength; > + UINT16 NameSpaceStringOffset; > + UINT16 OemDataLength; > + UINT16 OemDataOffset; > + UINT16 PortType; > + UINT16 PortSubtype; > + UINT16 Reserved; > + UINT16 BaseAddressRegisterOffset; > + UINT16 AddressSizeOffset; > +} DEBUG_DEVICE_INFO; > + > +typedef struct { > + DEBUG_DEVICE_INFO DeviceInfo; > + EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister; > + UINT32 AddressSize; > + char NameSpaceString[UART_NAME_SPACE_STRING_LENGTH]; > +} DEBUG_DEVICE_INFO_UART; > + > +typedef struct { > + EFI_ACPI_5_0_DEBUG_PORT_2_TABLE_HEADER Header; > + DEBUG_DEVICE_INFO_UART Uart; > +} EFI_ACPI_5_0_DEBUG_PORT_2_TABLE; > + > +#pragma pack () > + > +// Debug Port 2 table > +EFI_ACPI_5_0_DEBUG_PORT_2_TABLE Dbg2 = { > + { > + // Header > + { > + EFI_ACPI_5_0_DEBUG_PORT_2_TABLE_SIGNATURE, // Signature "DBG2" > + sizeof (EFI_ACPI_5_0_DEBUG_PORT_2_TABLE), // Length > + EFI_ACPI_DEBUG_PORT_2_TABLE_REVISION, // Revision > + EFI_ACPI_5_0_UNDEFINED, // Checksum - updated at runtime > + EFI_ACPI_OEM_ID, // OEM ID[6] > + EFI_ACPI_OEM_TABLE_ID, // OEM Table ID > + EFI_ACPI_OEM_REVISION, // OEM Revision > + EFI_ACPI_CREATOR_ID, // Creator ID > + EFI_ACPI_CREATOR_REVISION // Creator Revision > + }, > + sizeof (EFI_ACPI_5_0_DEBUG_PORT_2_TABLE_HEADER), // OffsetDbgDeviceinfo > + 1, // NumberDbgDeviceInfo > + }, > + { > + // Uart > + { > + // DeviceInfo > + EFI_ACPI_RESERVED_BYTE, // Revision > + sizeof (DEBUG_DEVICE_INFO_UART), // Length > + 1, // NumberofGenericAddressRegisters > + UART_NAME_SPACE_STRING_LENGTH, // NameSpaceStringLength > + OFFSET_OF (DEBUG_DEVICE_INFO_UART, NameSpaceString), // NameSpaceStringOffset > + 0, // OemDataLength > + EFI_ACPI_RESERVED_WORD, // OemDataOffset > + DBG2_TYPE_SERIAL, // PortType > + DBG_PORT_SUBTYPE_IMX6, // PortSubtype 000Ch > + EFI_ACPI_RESERVED_WORD, // Reserved > + OFFSET_OF (DEBUG_DEVICE_INFO_UART, BaseAddressRegister), // BaseAddressRegisterOffset > + OFFSET_OF (DEBUG_DEVICE_INFO_UART, AddressSize), // AddressSizeOffset > + }, > + { > + // BaseAddressRegister > + EFI_ACPI_5_0_SYSTEM_MEMORY, // AddressSpaceId > + 0x20, // RegisterBitWidth = 32 > + 0, // RegisterBitOffset = 0 > + 0x20, // AccessSize = 32 > + KD_UART_BASE_ADDR, // Address > + }, > + UART_IMX6_UART_ADDRESS_SIZE, // AddressSize > + KD_UART_ACPI_PATH, // NameSpaceString > + }, > +}; > + > +VOID* > +ReferenceAcpiTable ( > + VOID > + ) > +{ > + return (void *) &Dbg2; > +} > diff --git a/Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Common.h b/Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Common.h > new file mode 100644 > index 000000000000..4e4a3522e842 > --- /dev/null > +++ b/Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Common.h > @@ -0,0 +1,106 @@ > +/** @file > +* > +* Copyright (c) 2018 Microsoft Corporation. All rights reserved. > +* > +* This program and the accompanying materials > +* are licensed and made available under the terms and conditions of the BSD License > +* which accompanies this distribution. The full text of the license may be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +* > +**/ > + > +// IMX alternate settings codes > +#define IMX_ALT0 0x0 > +#define IMX_ALT1 0x1 > +#define IMX_ALT2 0x2 > +#define IMX_ALT3 0x3 > +#define IMX_ALT4 0x4 > +#define IMX_ALT5 0x5 > +#define IMX_ALT6 0x6 > +#define IMX_ALT7 0x7 > + > +// IMX SDMA request lines. > +// These are logical values, the mapping to the SOC > +// actual DMA request lines are done in the HAL extension. > +#define SDMA_REQ_VPU 0 > +#define SDMA_REQ_IPU2 1 > +#define SDMA_REQ_IPU1 2 > +#define SDMA_REQ_HDMI_AUDIO 3 > +#define SDMA_REQ_ECSPI1_RX 4 > +#define SDMA_REQ_ECSPI1_TX 5 > +#define SDMA_REQ_ECSPI2_RX 6 > +#define SDMA_REQ_ECSPI2_TX 7 > +#define SDMA_REQ_ECSPI3_RX 8 > +#define SDMA_REQ_ECSPI3_TX 9 > +#define SDMA_REQ_ECSPI4_RX 10 > +#define SDMA_REQ_ECSPI4_TX 11 > +#define SDMA_REQ_ECSPI5_RX 12 > +#define SDMA_REQ_ECSPI5_TX 13 > +#define SDMA_REQ_I2C1_RX 14 > +#define SDMA_REQ_I2C1_TX 15 > +#define SDMA_REQ_I2C2_RX 16 > +#define SDMA_REQ_I2C2_TX 17 > +#define SDMA_REQ_I2C3_RX 18 > +#define SDMA_REQ_I2C3_TX 19 > +#define SDMA_REQ_UART1_RX 20 > +#define SDMA_REQ_UART1_TX 21 > +#define SDMA_REQ_UART2_RX 22 > +#define SDMA_REQ_UART2_TX 23 > +#define SDMA_REQ_UART3_RX 24 > +#define SDMA_REQ_UART3_TX 25 > +#define SDMA_REQ_UART4_RX 26 > +#define SDMA_REQ_UART4_TX 27 > +#define SDMA_REQ_UART5_RX 28 > +#define SDMA_REQ_UART5_TX 29 > +#define SDMA_REQ_SPDIF_RX 30 > +#define SDMA_REQ_SPDIF_TX 31 > +#define SDMA_REQ_EPIT1 32 > +#define SDMA_REQ_EPIT2 33 > +#define SDMA_REQ_GPT 34 > +#define SDMA_REQ_ASRC_RXA 35 > +#define SDMA_REQ_ASRC_RXB 36 > +#define SDMA_REQ_ASRC_RXC 37 > +#define SDMA_REQ_ASRC_TXA 38 > +#define SDMA_REQ_ASRC_TXB 39 > +#define SDMA_REQ_ASRC_TXC 40 > +#define SDMA_REQ_ESAI_RX 41 > +#define SDMA_REQ_ESAI_TX 42 > +#define SDMA_REQ_ASRC_TXA_2_ESAI_TX 43 > +#define SDMA_REQ_ASRC_TXB_2_ESAI_TX 44 > +#define SDMA_REQ_ASRC_TXC_2_ESAI_TX 45 > +#define SDMA_REQ_SSI1_RX1 46 > +#define SDMA_REQ_SSI1_TX1 47 > +#define SDMA_REQ_SSI1_RX0 48 > +#define SDMA_REQ_SSI1_TX0 49 > +#define SDMA_REQ_SSI2_RX1 50 > +#define SDMA_REQ_SSI2_TX1 51 > +#define SDMA_REQ_SSI2_RX0 52 > +#define SDMA_REQ_SSI2_TX0 53 > +#define SDMA_REQ_SSI3_RX1 54 > +#define SDMA_REQ_SSI3_TX1 55 > +#define SDMA_REQ_SSI3_RX0 56 > +#define SDMA_REQ_SSI3_TX0 57 > +#define SDMA_REQ_EXT1 58 > +#define SDMA_REQ_EXT2 59 > +#define SDMA_REQ_UART6_RX 60 > +#define SDMA_REQ_UART6_TX 61 > +#define SDMA_REQ_ADC1 62 > +#define SDMA_REQ_ADC2 63 > +#define SDMA_REQ_I2C4_RX 64 > +#define SDMA_REQ_I2C4_TX 65 > +#define SDMA_REQ_CSI1 66 > +#define SDMA_REQ_CSI2 67 > +#define SDMA_REQ_PXP 68 > +#define SDMA_REQ_LCDIF1 69 > +#define SDMA_REQ_LCDIF2 70 > +#define SDMA_REQ_QSPI1_RX 71 > +#define SDMA_REQ_QSPI1_TX 72 > +#define SDMA_REQ_QSPI2_RX 73 > +#define SDMA_REQ_QSPI2_TX 74 > +#define SDMA_REQ_SAI1_TX 75 > +#define SDMA_REQ_SAI1_RX 76 > +#define SDMA_REQ_SAI2_TX 77 > +#define SDMA_REQ_SAI2_RX 78 > diff --git a/Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Enet.asl b/Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Enet.asl > new file mode 100644 > index 000000000000..eded7cdae7d0 > --- /dev/null > +++ b/Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Enet.asl > @@ -0,0 +1,106 @@ > +/** @file > +* > +* Copyright (c) 2018 Microsoft Corporation. All rights reserved. > +* > +* This program and the accompanying materials > +* are licensed and made available under the terms and conditions of the BSD License > +* which accompanies this distribution. The full text of the license may be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +* > +**/ > + > +Device (ENET) > +{ > + Name (_HID, "NXP010D") > + Name (_UID, 0x0) > + > + Method (_STA) { > + Return (0xF) > + } > + > + Method (_CRS, 0x0, NotSerialized) { > + Name (RBUF, ResourceTemplate () { > + // ENET MAC Core Base address > + MEMORY32FIXED (ReadWrite, 0x02188000, 0x4000, ) > + > + // ENET MAC 0 Core IRQ > + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 150 } > + > + // ENET MAC 0 1588 Timer interrupt > + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 151 } > + > + // Errata ERR006687: workaround for GPIO interrupt to connect Enet interrupt > + // to the GPC > + GpioInt (Level, ActiveHigh, Shared, PullDefault, 0, "\\_SB.GPIO",) { 6 } > + }) > + Return (RBUF) > + } > + > + Name (MAC, Buffer (6) {}) > + CreateDWordField (MAC, 0x00, MACL) > + CreateWordField (MAC, 0x04, MACH) > + > + // Device Specific Method takes 4 args: > + // Arg0 : Buffer containing a UUID [16 bytes] > + // Arg1 : Integer containing the Revision ID > + // Arg2 : Integer containing the Function Index > + // Arg3 : Package that contains function-specific arguments > + Method (_DSM, 0x4, NotSerialized) { > + switch (ToBuffer (Arg0)) { > + // iMX Enet interface identifier > + case (ToUUID ("4EBBCB9D-4087-4791-80BD-8F8C08024206")) { > + // Function selector > + switch (Arg2) { > + // Function 0: Query support > + // Bit Description > + // --- ------------------------------- > + // 0 Get property (Function 0) > + // 1 Enet PHY address on MDIO bus (Function 1) > + // 2 Get Mac Address (Function 2) > + // 3 Get MDIO BAse Address (Function 3) > + case (0) { > + // Revision selector > + switch (Arg1) { > + case (0) { > + // Functions {0,1,2} supported > + Return (Buffer() { 0x07 }); > + } > + default { > + Return (Buffer() { 0x00 }); > + } > + } > + } > + > + // Function 1: Return Enet PHY address on MDIO bus. > + case (1) { > + Return (0x00); > + } > + > + // Function 2: Return Mac Address > + case (2) { > + if (LEqual (SIGN, 0x474C424C)) { > + if (LEqual (REVN, 1)) { > + if (Lequal (MC0V, 1)) { > + Store (MC0L, MACL); > + Store (MC0H, MACH); > + Return (MAC) > + } > + } > + } > + Return (Buffer() { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }); > + } > + > + default { > + Return (Buffer() { 0x00 }); > + } > + } > + } > + default { > + Return (Buffer() { 0x00 }); > + } > + } > + } > +} > diff --git a/Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Gfx.asl b/Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Gfx.asl > new file mode 100644 > index 000000000000..eec71864210e > --- /dev/null > +++ b/Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Gfx.asl > @@ -0,0 +1,74 @@ > +/** @file > +* > +* Copyright (c) 2018 Microsoft Corporation. All rights reserved. > +* > +* This program and the accompanying materials > +* are licensed and made available under the terms and conditions of the BSD License > +* which accompanies this distribution. The full text of the license may be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +* > +**/ > + > +Device (VPU0) > +{ > + Name (_HID, "NXP0109") > + Name (_UID, 0x0) > + > + Method (_STA) { > + Return (0x0) > + } > + > + Method (_CRS, 0x0, NotSerialized) { > + Name (RBUF, ResourceTemplate () { > + MEMORY32FIXED (ReadWrite, 0x02040000, 0x3C000, ) > + > + // JPEG codec interrupt request > + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 35 } > + > + // VPU interrupt request > + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 44 } > + }) > + Return (RBUF) > + } > +} > + > +// Description: Graphics Processing Unit (GPU) > +Device (GPU0) > +{ > + Name (_HID, "VERI2000") > + Name (_CID, "VERI2000") > + Name (_UID, 0) > + > + Method (_STA) { > + Return (0xf) > + } > + > + Method (_CRS, 0x0, NotSerialized) { > + Name (RBUF, ResourceTemplate () { > + // GPU 3D (GC2000) > + MEMORY32FIXED (ReadWrite, 0x00130000, 0x4000, ) > + > + // GPU 2D (GC320) > + MEMORY32FIXED (ReadWrite, 0x00134000, 0x4000, ) > + > + // IPU Base > + MEMORY32FIXED (ReadWrite, 0x02600000, 0x400000, ) > + > + // HDMI PHY > + MEMORY32FIXED (ReadWrite, 0x00120000, 0x9000, ) > + > + // GC2000 > + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 41 } > + > + // GC320 > + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 42 } > + > + // IPU1 sync interrupt request > + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 38 } > + }) > + Return (RBUF) > + } > +} > diff --git a/Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Gpio.asl b/Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Gpio.asl > new file mode 100644 > index 000000000000..d9a5d2f8500a > --- /dev/null > +++ b/Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Gpio.asl > @@ -0,0 +1,55 @@ > +/** @file > +* > +* Copyright (c) 2018 Microsoft Corporation. All rights reserved. > +* > +* This program and the accompanying materials > +* are licensed and made available under the terms and conditions of the BSD License > +* which accompanies this distribution. The full text of the license may be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +* > +**/ > + > +Device (GPIO) > +{ > + Name (_HID, "NXP0103") > + Name (_UID, 0x0) > + > + Method (_STA) { > + Return (0xf) > + } > + > + Method (_CRS, 0x0, NotSerialized) { > + Name (RBUF, ResourceTemplate () { > + // GPIO1-7 > + MEMORY32FIXED (ReadWrite, 0x0209C000, 0x1C000, ) > + > + // IOMUXC > + MEMORY32FIXED (ReadWrite, 0x020E0000, 0x4000, ) > + > + // GPIO1 0-15, 16-31 > + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 98, 99 } > + > + // GPIO2 0-15, 16-31 > + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 100, 101 } > + > + // GPIO3 0-15, 16-31 > + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 102, 103 } > + > + // GPIO4 0-15, 16-31 > + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 104, 105 } > + > + // GPIO5 0-15, 16-31 > + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 106, 107 } > + > + // GPIO6 0-15, 16-31 > + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 108, 109 } > + > + // GPIO7 0-15, 16-31 > + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 110, 111 } > + }) > + Return (RBUF) > + } > +} > diff --git a/Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-I2c.asl b/Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-I2c.asl > new file mode 100644 > index 000000000000..af9f17890b97 > --- /dev/null > +++ b/Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-I2c.asl > @@ -0,0 +1,67 @@ > +/** @file > +* > +* Copyright (c) 2018 Microsoft Corporation. All rights reserved. > +* > +* This program and the accompanying materials > +* are licensed and made available under the terms and conditions of the BSD License > +* which accompanies this distribution. The full text of the license may be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +* > +**/ > + > +Device (I2C1) > +{ > + Name (_HID, "NXP0104") > + Name (_UID, 0x1) > + > + Method (_STA) { > + Return (0xf) > + } > + > + Method (_CRS, 0x0, NotSerialized) { > + Name (RBUF, ResourceTemplate () { > + MEMORY32FIXED (ReadWrite, 0x021A0000, 0x14, ) > + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 68 } > + }) > + Return (RBUF) > + } > +} > + > +Device (I2C2) > +{ > + Name (_HID, "NXP0104") > + Name (_UID, 0x2) > + > + Method (_STA) { > + Return (0xf) > + } > + > + Method (_CRS, 0x0, NotSerialized) { > + Name (RBUF, ResourceTemplate () { > + MEMORY32FIXED (ReadWrite, 0x021A4000, 0x14, ) > + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 69 } > + }) > + Return (RBUF) > + } > +} > + > +Device (I2C3) > +{ > + Name (_HID, "NXP0104") > + Name (_UID, 0x3) > + > + Method (_STA) { > + Return (0xf) > + } > + > + Method (_CRS, 0x0, NotSerialized) { > + Name (RBUF, ResourceTemplate () { > + MEMORY32FIXED (ReadWrite, 0x021A8000, 0x14, ) > + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 70 } > + }) > + Return (RBUF) > + } > +} > diff --git a/Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-PCIe.asl b/Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-PCIe.asl > new file mode 100644 > index 000000000000..1e0627f93000 > --- /dev/null > +++ b/Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-PCIe.asl > @@ -0,0 +1,298 @@ > +/** @file > +* > +* Copyright (c) 2018 Microsoft Corporation. All rights reserved. > +* > +* This program and the accompanying materials > +* are licensed and made available under the terms and conditions of the BSD License > +* which accompanies this distribution. The full text of the license may be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +* > +**/ > + > +Device (PCI0) > +{ > + Name (_HID, "PNP0A08") > + Name (_UID, 0) > + Name (_STR, Unicode ("PCIe 0 Device")) > + Name (_BBN, 0) > + Name (_SEG, 0) > + > + // PCIE_PL memory map > + OperationRegion (PLGC, SystemMemory, 0x01FFC700, 0x220) > + Field (PLGC, DWordAcc, NoLock, Preserve) { > + Offset (0x2C), // Skip to register 0x01FFC72C > + DBG1, 32, // PCIE_PL_DEBUG1 > + } > + > + // IOMUXC memory map > + OperationRegion (IMXC, SystemMemory, 0x020E0000, 0x4000) > + Field (IMXC, DWordAcc, NoLock, Preserve) { > + Offset (0x04), // Skip to register 0x020E0004 > + GPR1, 32, // IOMUXC_GPR1 > + } > + > + // PCIe is only available if PCIe PHY reference clock is enabled and link is up > + Method (_STA) { > + Name (LNK, 0x0); > + Name (GPR, 0x0); > + Store (GPR1, GPR); // read IOMUXC_GPR1 register > + > + // Check if the PCIe PHY reference clock is enabled > + If (LNotEqual (And (GPR, 0x00010000), 0x00010000)) { > + Return (0x0) > + } > + > + Store (DBG1, LNK); // read PCIE_PL_DEBUG1 register > + > + // Check if link is already up and is not in training > + // Bit4 : [36]: xmlh_link_up LTSSM reports PHY link up > + // Bit29 : [61]: xmlh_link_in_training LTSSM performing link training > + If (LAnd (And (DBG1, 0x00000010), Lequal (And (DBG1, 0x20000000), 0x00))) { > + Return (0xF) > + } else { > + Return (0x0) > + } > + } > + > + // Declare the resources assigned to this root complex. > + Method (_CRS, 0, Serialized) { > + Name (RBUF, ResourceTemplate () { > + WordBusNumber ( > + ResourceProducer, // Specify bus ranged is passed to child devices > + MinFixed, // Specify min address is fixed > + MaxFixed, // Specify max address is fixed > + PosDecode, // Positive decode of bus number > + 0, // AddressGranularity 2 power of 0 > + 0, // AddressMinimum - Minimum Bus Number > + 1, // AddressMaximum - Maximum Bus Number > + 0, // AddressTranslation - Set to 0 > + 2) // RangeLength - Number of Busses > + > + // PCI memory space > + Memory32Fixed (ReadWrite, 0x01100000, 0x00E00000, ) > + }) > + Return (RBUF) > + } > + > + // Declare the PCI Routing Table. > + Name (_PRT, Package() { > + // Routing for device 0, all functions. > + // Note: ARM doesn't support LNK nodes, so the third param > + // is 0 and the fourth param is the SPI number of the interrupt > + // line. > + Package() {0x0000FFFF, 0, 0, 155}, // INTA > + Package() {0x0000FFFF, 1, 0, 154}, // INTB > + Package() {0x0000FFFF, 2, 0, 153}, // INTC > + Package() {0x0000FFFF, 3, 0, 152}, // INTD/MSI > + }) > + > + Name (SUPP, 0) // PCI _OSC Support Field value > + Name (CTRL, 0) // PCI _OSC Control Field value > + > + // Declare an _OSC (OS Control Hand-off) method which takes 4 arguments. > + // > + // Arguments: > + // Arg0 A Buffer containing a UUID > + // Arg1 An Integer containing a Revision ID of the buffer format > + // Arg2 An Integer containing a count of entries in Arg3 > + // Arg3 A Buffer containing a list of DWORD capabilities > + // Return Value: > + // A Buffer containing a list of capabilities > + Method (_OSC, 4) { > + > + // Create DWord-addressable fields from the Capabilities Buffer > + // Create CDW1 outside the test as it's used in the else clause. > + // The first DWORD in the _OSC Capabilities Buffer contains bits > + // that are generic to _OSC > + // PCI Firmware Specification - 4.5.1. > + // > + // ACPI - 6.2.10 > + // CDW return value information > + // Bit 0 - Reserved (not used) > + // Bit 1 - _OSC failure. Platform Firmware was unable to process the request or query > + // Bit 2 - Unrecognized UUID > + // Bit 3 - Unrecognized Revision > + // Bit 4 - Capabilities Masked > + // All others reserved > + > + CreateDWordField (Arg3, 0, CDW1) > + If (LEqual (Arg0, ToUUID ("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { > + CreateDWordField (Arg3, 4, CDW2) > + CreateDWordField (Arg3, 8, CDW3) > + > + // Save Capabilities DWord 2 & 3 > + // The second DWORD in the _OSC Capabilities Buffer is the Support Field > + // The third DWORD in the _OSC Capabilities Buffer is the Control Field > + // PCI Firmware Specification - 4.5.1. > + // Supported feature should be set in the control field > + // > + // Support field > + // Bit 0 - Extended PCI Config operation regions supported > + // Bit 1 - Active State Power Management supported > + // Bit 2 - Clock Power Management Capability supported > + // Bit 3 - PCI Segment Groups supported > + // Bit 4 - MSI supported > + // Bit 5 - Optimized Buffer Flush and Fill supported > + // Bit 6 - ASPM Optionality supported > + // > + // Control field > + // Bit 0 - PCI Express Native Hot Plug control > + // Bit 1 - SHPC Native Hot Plug control > + // Bit 2 - PCI Express Native Power Management Events control > + // Bit 3 - PCI Express Advanced Error Reporting control > + // Bit 4 - PCI Express Capability Structure control > + // Bit 5 - Latency Tolerance Reporting control > + > + Store (CDW2, SUPP) > + Store (CDW3, CTRL) > + > + // Only allow native hot plug control if OS supports: > + // ASPM > + // Clock PM > + // MSI/MSI-X > + If (LNotEqual (And (SUPP, 0x16), 0x16)) { > + And (CTRL, 0x1E, CTRL) > + } > + > + // Spec does not mention if standard hot plug is supported > + // so unmask the bit > + And (CTRL, 0x1D, CTRL) > + > + // Check for unknown revision. > + If (LNotEqual (Arg1, One)) { > + Or (CDW1, 0x08, CDW1) > + } > + > + // Check if capabilities bits were masked. > + If (LNotEqual (CDW3, CTRL)) { > + Or (CDW1, 0x10, CDW1) > + } > + > + // Update DWORD3 in the buffer. > + Store (CTRL, CDW3) > + Return (Arg3) > + } else { > + // Unrecognized UUID > + Or (CDW1, 4, CDW1) > + Return (Arg3) > + } > + } > + > + // Declare a _DSM method for various functions called by the OS. > + // See the APCI spec, Section 9.14.1, > + // and the PCI FW spec, Section 4.6. > + // See also: > + // http://download.microsoft.com/download/9/c/5/9c5b2167-8017-4bae-9fde-d599bac8184a/PCI-rsc.doc > + Method (_DSM, 0x4, Serialized) { > + // Match against the _DSM PCI UUID. PCI firmware spec - 4.6.1 > + // Arg0 - UUID > + // Arg1 - Revision ID > + // Arg2 - Function Index > + // Arg3 - Empty Package > + // > + // Revision 1 & 2 > + // Function 1 - PCI Express Slot Information > + // Function 2 - PCI Express Slot Number > + // Function 3 - Vendor-specific Token ID > + // Function 4 - PCI Bus Capabilities > + // Function 5 - Ignore PCI Boot Configuration > + // Revision 2 only > + // Function 6 - LTR Maximum Latency > + // Function 7 - Express device under OS > + If (LEqual (Arg0, ToUUID ("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) { > + > + switch (ToInteger (Arg2)) { > + // Function 0: Return supported functions as a bit-field > + // with one bit for each supported function. > + // Bit 0 must always be set, as that represents > + // function 0 (which is what is being called here). > + // Support for different functions may depend on > + // the revision ID of the interface, passed as Arg1. > + > + // Function 0: Get supported functions > + case (0) { > + // Functions 0,1,5 are supported. > + if (LEqual (Arg1, 1)) { > + return (Buffer() { 0x23 }) > + } > + > + // Functions 0,1,5,7 are supported. > + if (LEqual (Arg1, 2)) { > + return (Buffer() { 0xA3 }) > + } > + > + // Functions 0,1,5,7 are supported for > + // future revision. Expect backward compatibility > + return (Buffer() { 0xA3 }) > + } > + > + // Function 1: PCI Express Slot Information > + // PCI firmware spec - 4.6.1 > + case (1) { > + // Package item 1: > + // 0: Failure > + // 1: Success > + // Package item 2: > + // Integer 1:Bit Position > + // 0 Supports x1 > + // 1 Supports x2 > + // 2 Supports x4 > + // 3 Supports x8 > + // 4 Supports x12 > + // 5 Supports x16 > + // Integer 2: > + // 0h Unknown > + // 1h PCI Express Card Slot > + // 2h PCI Express Server I/O Module Slot > + // 3h PCI Express ExpressCard* Slot > + // 4h PCI Express Mini Card Slot > + // 5h PCI Express Wireless Form Factor Slot > + // Others Reserved > + // Integer 3: > + // 0 SMBus signal > + // 1 WAKE# signal > + return ( Package (2) { > + 0x01, // Status success (1) > + Package() { > + 0, // Supports x1 > + 4, // PCI Express Mini Card Slot > + 1 // Supported signals (no SMBus, WAKE#) > + } > + }) > + } > + > + // Function 5: Ignore PCI Boot Configurations > + // PCI firmware spec - 4.6.5 > + case (5) { > + // Always allow OS to rebalance > + return (0x01) > + } > + > + // Function 7: Naming a PCI or PCI Express Device Under > + // Operating Systems > + // PCI firmware spec - 4.6.7 > + case (7) { > + // Verify revision 2 > + if (LEqual (Arg1, 2)) { > + // PCI Express Slot Parsing > + Return ( Package (2) { > + 1, // Instance of the enumeration > + "PCIe Slot 1" // String name which matches the label on the chassis > + }) > + } > + } > + } > + } > + return (Buffer() { 0 }) > + } > + > + // Root Port 0 Device within the Root Complex. > + Device (RP0) { > + Name (_ADR, 0) // Device 0, Function 0 > + Name (_S0W, 4) // Supports wake > + } > + > +} > diff --git a/Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Platform.asl b/Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Platform.asl > new file mode 100644 > index 000000000000..0bdc78080d26 > --- /dev/null > +++ b/Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Platform.asl > @@ -0,0 +1,106 @@ > +/** @file > +* > +* Copyright (c) 2018 Microsoft Corporation. All rights reserved. > +* > +* This program and the accompanying materials > +* are licensed and made available under the terms and conditions of the BSD License > +* which accompanies this distribution. The full text of the license may be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +* > +**/ > + > +OperationRegion (GLBL, SystemMemory, 0x10817000, 0x10) > +Field (GLBL, AnyAcc, Nolock, Preserve) > +{ > + Offset (0), // Miscellaneous Dynamic Registers: > + SIGN, 32, // Global Page Signature 'GLBL' > + REVN, 8, // Revision > + , 8, // Reserved > + , 8, // Reserved > + , 8, // Reserved > + M0ID, 8, // MAC 0 ID > + MC0V, 8, // MAC 0 Valid > + MC0L, 32, // MAC Address 0 Low > + MC0H, 16, // MAC Address 0 High > +} > + > +Device (CPU0) > +{ > + Name (_HID, "ACPI0007") > + Name (_UID, 0x0) > + > + Method (_STA) { > + Return (0xf) > + } > +} > + > +Device (CPU1) > +{ > + Name (_HID, "ACPI0007") > + Name (_UID, 0x1) > + > + Method (_STA) { > + Return (0xf) > + } > +} > + > +Device (CPU2) > +{ > + Name (_HID, "ACPI0007") > + Name (_UID, 0x2) > + > + Method (_STA) { > + Return (0xf) > + } > +} > + > +Device (CPU3) > +{ > + Name (_HID, "ACPI0007") > + Name (_UID, 0x3) > + > + Method (_STA) { > + Return (0xf) > + } > +} > + > +// Timers HAL extension > +Device (EPIT) > +{ > + Name (_HID, "NXP0101") > + Name (_UID, 0x0) > + > + Method (_STA) { > + Return (0xf) > + } > +} > + > +// Platform Extension Plugin > +Device (PEP0) > +{ > + Name (_HID, "NXP0102") > + Name (_UID, 0x0) > + > + Method (_STA) { > + Return (0xf) > + } > + Method (_CRS, 0x0, NotSerialized) { > + Name (RBUF, ResourceTemplate () { > + // CCM request 1 > + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 119 } > + > + // CCM request 2 > + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 120 } > + > + // GPC request 1 > + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 121 } > + > + // UART1 > + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared) { 58 } > + }) > + Return (RBUF) > + } > +} > diff --git a/Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Pwm.asl b/Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Pwm.asl > new file mode 100644 > index 000000000000..22bab0cff575 > --- /dev/null > +++ b/Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Pwm.asl > @@ -0,0 +1,85 @@ > +/** @file > +* > +* Copyright (c) 2018 Microsoft Corporation. All rights reserved. > +* > +* This program and the accompanying materials > +* are licensed and made available under the terms and conditions of the BSD License > +* which accompanies this distribution. The full text of the license may be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +* > +**/ > + > +Device (PWM1) > +{ > + Name (_HID, "NXP010E") > + Name (_UID, 0x1) > + > + Method (_STA) { > + Return (0xf) > + } > + > + Method (_CRS, 0x0, NotSerialized) { > + Name (RBUF, ResourceTemplate () { > + MEMORY32FIXED (ReadWrite, 0x02080000, 0x4000, ) > + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 115 } > + }) > + Return (RBUF) > + } > +} > + > +Device (PWM2) > +{ > + Name (_HID, "NXP010E") > + Name (_UID, 0x2) > + > + Method (_STA) { > + Return (0xf) > + } > + > + Method (_CRS, 0x0, NotSerialized) { > + Name (RBUF, ResourceTemplate () { > + MEMORY32FIXED (ReadWrite, 0x02084000, 0x4000, ) > + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 116 } > + }) > + Return (RBUF) > + } > +} > + > +Device (PWM3) > +{ > + Name (_HID, "NXP010E") > + Name (_UID, 0x3) > + > + Method (_STA) { > + Return (0xf) > + } > + > + Method (_CRS, 0x0, NotSerialized) { > + Name (RBUF, ResourceTemplate () { > + MEMORY32FIXED (ReadWrite, 0x02088000, 0x4000, ) > + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 117 } > + }) > + Return (RBUF) > + } > +} > + > +Device (PWM4) > +{ > + Name (_HID, "NXP010E") > + Name (_UID, 0x4) > + > + Method (_STA) { > + Return (0xf) > + } > + > + Method (_CRS, 0x0, NotSerialized) { > + Name (RBUF, ResourceTemplate () { > + MEMORY32FIXED (ReadWrite, 0x0208C000, 0x4000, ) > + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 118 } > + }) > + Return (RBUF) > + } > +} > diff --git a/Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Sdhc.asl b/Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Sdhc.asl > new file mode 100644 > index 000000000000..fad33d2e9d6c > --- /dev/null > +++ b/Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Sdhc.asl > @@ -0,0 +1,133 @@ > +/** @file > +* > +* Copyright (c) 2018 Microsoft Corporation. All rights reserved. > +* > +* This program and the accompanying materials > +* are licensed and made available under the terms and conditions of the BSD License > +* which accompanies this distribution. The full text of the license may be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +* > +**/ > + > +// uSDHC1 > +Device (SDH1) > +{ > + Name (_HID, "NXP0108") > + Name (_UID, 0x1) > + > + Method (_STA) { > + Return (0xf) > + } > + > + Method (_CRS, 0x0, NotSerialized) { > + Name (RBUF, ResourceTemplate () { > + MEMORY32FIXED (ReadWrite, 0x02190000, 0x4000, ) > + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 54 } > + }) > + Return (RBUF) > + } > + > + // Child node to represent the only SD/MMC slot on this SD/MMC bus > + // In theory an SDHC can be connected to multiple SD/MMC slots at > + // the same time, but only 1 device will be selected and active at > + // a time > + Device (SD0) { > + Method (_ADR) { > + Return (0) > + } > + > + Method (_RMV) { > + Return (0) > + } > + } > +} > + > +// uSDHC2 > +Device (SDH2) > +{ > + Name (_HID, "NXP0108") > + Name (_UID, 0x2) > + > + Method (_STA) { > + Return (0xf) > + } > + > + Method (_CRS, 0x0, NotSerialized) { > + Name (RBUF, ResourceTemplate () { > + MEMORY32FIXED (ReadWrite, 0x02194000, 0x4000, ) > + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 55 } > + }) > + Return (RBUF) > + } > + > + Device (SD0) { > + Method (_ADR) { > + Return (0) > + } > + > + Method (_RMV) { > + Return (0) > + } > + } > +} > + > +// uSDHC3 > +Device (SDH3) > +{ > + Name (_HID, "NXP0108") > + Name (_UID, 0x3) > + > + Method (_STA) { > + Return (0xf) > + } > + > + Method (_CRS, 0x0, NotSerialized) { > + Name (RBUF, ResourceTemplate () { > + MEMORY32FIXED (ReadWrite, 0x02198000, 0x4000, ) > + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 56 } > + }) > + Return (RBUF) > + } > + > + Device (SD0) { > + Method (_ADR) { > + Return (0) > + } > + > + Method (_RMV) { > + Return (0) > + } > + } > +} > + > +// uSDHC4 > +Device (SDH4) > +{ > + Name (_HID, "NXP0108") > + Name (_UID, 0x4) > + > + Method (_STA) { > + Return (0xf) > + } > + > + Method (_CRS, 0x0, NotSerialized) { > + Name (RBUF, ResourceTemplate () { > + MEMORY32FIXED (ReadWrite, 0x0219C000, 0x4000, ) > + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 57 } > + }) > + Return (RBUF) > + } > + > + Device (SD0) { > + Method (_ADR) { > + Return (0) > + } > + > + Method (_RMV) { > + Return (0) > + } > + } > +} > diff --git a/Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Spi.asl b/Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Spi.asl > new file mode 100644 > index 000000000000..f68a7f306ecc > --- /dev/null > +++ b/Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-Spi.asl > @@ -0,0 +1,103 @@ > +/** @file > +* > +* Copyright (c) 2018 Microsoft Corporation. All rights reserved. > +* > +* This program and the accompanying materials > +* are licensed and made available under the terms and conditions of the BSD License > +* which accompanies this distribution. The full text of the license may be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +* > +**/ > + > +Device (SPI1) > +{ > + Name (_HID, "NXP0105") > + Name (_UID, 0x1) > + > + Method (_STA) { > + Return (0xf) > + } > + > + Method (_CRS, 0x0, NotSerialized) { > + Name (RBUF, ResourceTemplate () { > + MEMORY32FIXED (ReadWrite, 0x02008000, 0x4000, ) > + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 63 } > + }) > + Return (RBUF) > + } > +} > + > +Device (SPI2) > +{ > + Name (_HID, "NXP0105") > + Name (_UID, 0x2) > + > + Method (_STA) { > + Return (0xf) > + } > + > + Method (_CRS, 0x0, NotSerialized) { > + Name (RBUF, ResourceTemplate () { > + MEMORY32FIXED (ReadWrite, 0x0200C000, 0x4000, ) > + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 64 } > + }) > + Return (RBUF) > + } > +} > + > +Device (SPI3) > +{ > + Name (_HID, "NXP0105") > + Name (_UID, 0x3) > + > + Method (_STA) { > + Return (0xf) > + } > + > + Method (_CRS, 0x0, NotSerialized) { > + Name (RBUF, ResourceTemplate () { > + MEMORY32FIXED (ReadWrite, 0x02010000, 0x4000, ) > + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 65 } > + }) > + Return (RBUF) > + } > +} > + > +Device (SPI4) > +{ > + Name (_HID, "NXP0105") > + Name (_UID, 0x4) > + > + Method (_STA) { > + Return (0xf) > + } > + > + Method (_CRS, 0x0, NotSerialized) { > + Name (RBUF, ResourceTemplate () { > + MEMORY32FIXED (ReadWrite, 0x02014000, 0x4000, ) > + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 66 } > + }) > + Return (RBUF) > + } > +} > + > +Device (SPI5) > +{ > + Name (_HID, "NXP0105") > + Name (_UID, 0x5) > + > + Method (_STA) { > + Return (0xf) > + } > + > + Method (_CRS, 0x0, NotSerialized) { > + Name (RBUF, ResourceTemplate () { > + MEMORY32FIXED (ReadWrite, 0x02018000, 0x4000, ) > + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 67 } > + }) > + Return (RBUF) > + } > +} > diff --git a/Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-TrEE.asl b/Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-TrEE.asl > new file mode 100644 > index 000000000000..83975792bcaf > --- /dev/null > +++ b/Silicon/NXP/iMX6Pkg/AcpiTables/Dsdt-TrEE.asl > @@ -0,0 +1,33 @@ > +/** @file > +* > +* Copyright (c) 2018 Microsoft Corporation. All rights reserved. > +* > +* This program and the accompanying materials > +* are licensed and made available under the terms and conditions of the BSD License > +* which accompanies this distribution. The full text of the license may be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +* > +**/ > + > +Device (TREE) > +{ > + Name (_HID, "NXP010F") > + Name (_CID, "TrEECSMP") > + Name (_UID, 0) > + > + Method (_STA) { > + Return (0xf) > + } > + > + Method (_CRS, 0x0, NotSerialized) { > + Name (RBUF, ResourceTemplate () { > + // OP-TEE Shared memory area. > + // Needs to match: PcdTrustZoneSharedMemoryBase, PcdTrustZoneSharedMemorySize > + MEMORY32FIXED (ReadWrite, 0x12800000, 0x00200000, ) > + }) > + Return (RBUF) > + } > +} > diff --git a/Silicon/NXP/iMX6Pkg/AcpiTables/Fadt.aslc b/Silicon/NXP/iMX6Pkg/AcpiTables/Fadt.aslc > new file mode 100644 > index 000000000000..58181ee9eda7 > --- /dev/null > +++ b/Silicon/NXP/iMX6Pkg/AcpiTables/Fadt.aslc > @@ -0,0 +1,60 @@ > +/** @file > +* > +* Copyright (c) 2018 Microsoft Corporation. All rights reserved. > +* > +* This program and the accompanying materials > +* are licensed and made available under the terms and conditions of the BSD License > +* which accompanies this distribution. The full text of the license may be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +* > +**/ > + > +// Advertise support for PSCI > +#define FADT_ARM_BOOT_ARCH 0x01 > + > +char FACP[268] = { > + 0x46, 0x41, 0x43, 0x50, // Signature : 'FACP' > + 0x0C, 0x01, 0x00, 0x00, // Length > + 0x05, // Revision > + 0x00, // Checksum > + 0x4E, 0x58, 0x50, 0x4D, 0x58, 0x36, // OEMID : 'NXPMX6' > + 0x45, 0x44, 0x4B, 0x32, 0x20, 0x20, 0x20, 0x20, // OEMTABLE : 'EDK2' > + 0x01, 0x00, 0x00, 0x00, // OEM Revision > + 0x4D, 0x53, 0x46, 0x54, // CreatorID : 'MSFT' > + 0x01, 0x00, 0x00, 0x00, // Creator revision > + 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x04, 0x00, 0x00, 0x00, 0xE3, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, > + 0x00, 0x00, 0x21, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, FADT_ARM_BOOT_ARCH, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 > +}; > + > +VOID* > +ReferenceAcpiTable ( > + VOID > + ) > +{ > + return (void *) &FACP; > +} > diff --git a/Silicon/NXP/iMX6Pkg/AcpiTables/Madt.aslc b/Silicon/NXP/iMX6Pkg/AcpiTables/Madt.aslc > new file mode 100644 > index 000000000000..1c382306c780 > --- /dev/null > +++ b/Silicon/NXP/iMX6Pkg/AcpiTables/Madt.aslc > @@ -0,0 +1,120 @@ > +/** @file > +* > +* Copyright (c) 2018 Microsoft Corporation. All rights reserved. > +* > +* This program and the accompanying materials > +* are licensed and made available under the terms and conditions of the BSD License > +* which accompanies this distribution. The full text of the license may be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +* > +**/ > + > +#include > + > +#include > +#include > + > +#define GICC_BASE FixedPcdGet64 (PcdGicInterruptInterfaceBase) > +#define GICD_BASE FixedPcdGet64 (PcdGicDistributorBase) > + > +// Virtualization related fields. Not supported on IMX6 > +#define GICH_BASE 0 > +#define GICV_BASE 0 > +#define VGIC_MAINT_INT 0 > +#define PMU_INTERRUPT 0 > + > +#pragma pack(push, 1) > +typedef struct { > + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; > + EFI_ACPI_6_0_GIC_STRUCTURE GicC[FixedPcdGet32 (PcdCoreCount)]; > + EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE GicD; > +} ACPI_6_0_MADT_STRUCTURE; > +#pragma pack(pop) > + > +ACPI_6_0_MADT_STRUCTURE Madt = { > + { > + { > + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, // Signature > + sizeof (ACPI_6_0_MADT_STRUCTURE), // Length > + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION, // Revision > + 0, // Checksum > + EFI_ACPI_OEM_ID, // OemId[6] > + EFI_ACPI_OEM_TABLE_ID, // OemTableId > + EFI_ACPI_OEM_REVISION, // OemRevision > + EFI_ACPI_CREATOR_ID, // CreatorId > + EFI_ACPI_CREATOR_REVISION // CreatorRevision > + }, > + 0, // LocalApicAddress > + 0 // Flags > + }, > + { > + EFI_ACPI_6_0_GICC_STRUCTURE_INIT (0, // GicId > + 0x000, // AcpiCpuUid > + 0x000, // Mpidr > + EFI_ACPI_6_0_GIC_ENABLED, // Flags > + PMU_INTERRUPT, // PmuIrq > + GICC_BASE, // GicBase > + GICV_BASE, // GicVBase > + GICH_BASE, // GicHBase > + VGIC_MAINT_INT, // GsivId > + 0, // GicRBase > + 0 // Efficiency > + ), > +#if FixedPcdGet32(PcdCoreCount) > 1 > + EFI_ACPI_6_0_GICC_STRUCTURE_INIT (1, // GicId > + 0x001, // AcpiCpuUid > + 0x001, // Mpidr > + EFI_ACPI_6_0_GIC_ENABLED, // Flags > + PMU_INTERRUPT, // PmuIrq > + GICC_BASE, // GicBase > + GICV_BASE, // GicVBase > + GICH_BASE, // GicHBase > + VGIC_MAINT_INT, // GsivId > + 0, // GicRBase > + 0 // Efficiency > + ), > +#if FixedPcdGet32(PcdCoreCount) > 2 > + EFI_ACPI_6_0_GICC_STRUCTURE_INIT (2, // GicId > + 0x002, // AcpiCpuUid > + 0x002, // Mpidr > + EFI_ACPI_6_0_GIC_ENABLED, // Flags > + PMU_INTERRUPT, // PmuIrq > + GICC_BASE, // GicBase > + GICV_BASE, // GicVBase > + GICH_BASE, // GicHBase > + VGIC_MAINT_INT, // GsivId > + 0, // GicRBase > + 0 // Efficiency > + ), > + EFI_ACPI_6_0_GICC_STRUCTURE_INIT (3, // GicId > + 0x003, // AcpiCpuUid > + 0x003, // Mpidr > + EFI_ACPI_6_0_GIC_ENABLED, // Flags > + PMU_INTERRUPT, // PmuIrq > + GICC_BASE, // GicBase > + GICV_BASE, // GicVBase > + GICH_BASE, // GicHBase > + VGIC_MAINT_INT, // GsivId > + 0, // GicRBase > + 0 // Efficiency > + ), > +#endif > +#endif > + }, > + EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT (0x0, // GicDistHwId > + GICD_BASE, // GicDistBase > + IC_DIST_VECTOR_BASE, // GicDistVector > + EFI_ACPI_6_0_GIC_V1 // GicVersion > + ) > +}; > + > +VOID* > +ReferenceAcpiTable ( > + VOID > + ) > +{ > + return (VOID *)&Madt; > +} > diff --git a/Silicon/NXP/iMX6Pkg/AcpiTables/Mcfg.aslc b/Silicon/NXP/iMX6Pkg/AcpiTables/Mcfg.aslc > new file mode 100644 > index 000000000000..3e9d163cb52e > --- /dev/null > +++ b/Silicon/NXP/iMX6Pkg/AcpiTables/Mcfg.aslc > @@ -0,0 +1,92 @@ > +/** @file > +* > +* Copyright (c) 2018 Microsoft Corporation. All rights reserved. > +* > +* This program and the accompanying materials > +* are licensed and made available under the terms and conditions of the BSD License > +* which accompanies this distribution. The full text of the license may be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +* > +**/ > + > +#include > + > +#include > + > +#include "iMX6.h" #include > +#include "../Drivers/PciExpress/iMX6PciExpress.h" That include file should live in iMX6Pkg/Include/Drivers and be included as #include Apply these patterns throughout. > + > +#define EFI_ACPI_OEM_MCFG_REVISION 0x00000001 > + > +// Size in bytes a single bus consumes in ECAM space > +// Configuration size = 4K > +// Max device = 32 > +// Max function = 8 > +// Max bus size = 4K * 32 * 8 > +#define ECAM_BUS_ADDR_SIZE (1 << 20) > + > +// Provide 2 differenct base PCI space address. The first list would represent > +// the host config space and the second list would be the device config space. > +// Windows is expected to be able to parse the information. > +#define NUM_PCI 2 > + > +// MCFG structure > +// PCI Firmware specification Table 4-2 > +#pragma pack(push, 1) > + > +typedef struct { > + EFI_ACPI_DESCRIPTION_HEADER Header; > + UINT64 Reserved; > + EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE AllocationStructure[NUM_PCI]; > +} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE; > + > +#pragma pack(pop) > + > +// > +// Multiple APIC Description Table > +// > +EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE Mcfg = { > + { > + EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, > + sizeof (EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE), > + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION, > + 0x00, // Checksum will be updated at runtime > + EFI_ACPI_OEM_ID, // OEMID > + EFI_ACPI_OEM_TABLE_ID, // OEM Table ID > + EFI_ACPI_OEM_MCFG_REVISION, // OEM Revision > + EFI_ACPI_CREATOR_ID, // Creator ID > + EFI_ACPI_CREATOR_REVISION, // Creator revision > + }, > + 0x00, // Reserved > + > + { > + // PCIe Host > + { > + PCIE_HOST_CONFIG_BASE_REG, // PCIE Host Config Base Address > + 0x00, // PciSegmentGroupNumber (_SEG) > + 0x00, // StartBusNumber > + 0x00, // EndBusNumber > + 0x00000000 // Reserved > + }, > + > + // PCIe Device > + { > + PCIE_DEVICE_CONFIG_BASE_REG - ECAM_BUS_ADDR_SIZE, // BaseAddress > + 0x00, // PciSegmentGroupNumber (_SEG) > + 0x01, // StartBusNumber > + 0x01, // EndBusNumber > + 0x00000000 // Reserved > + } > + } > +}; > + > +VOID* > +ReferenceAcpiTable ( > + VOID > + ) > +{ > + return (VOID *)&Mcfg; > +} > diff --git a/Silicon/NXP/iMX6Pkg/AcpiTables/Spcr.aslc b/Silicon/NXP/iMX6Pkg/AcpiTables/Spcr.aslc > new file mode 100644 > index 000000000000..603422a737c4 > --- /dev/null > +++ b/Silicon/NXP/iMX6Pkg/AcpiTables/Spcr.aslc > @@ -0,0 +1,95 @@ > +/** @file > +* > +* Copyright (c) 2018 Microsoft Corporation. All rights reserved. > +* > +* This program and the accompanying materials > +* are licensed and made available under the terms and conditions of the BSD License > +* which accompanies this distribution. The full text of the license may be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +* > +**/ > + > +#include "Platform.h" Same thing, but here resolved via iMXPlatformPkg.dec. / Leif > +#include "iMX6.h" > + > +// Ensure proper structure formats > +#pragma pack (1) > + > +typedef struct { > + EFI_ACPI_DESCRIPTION_HEADER Header; > + UINT8 Interface_Type; > + UINT8 Reserved1[3]; > + EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister; > + UINT8 Interrupt_Type; > + UINT8 PCAT_compatible_IRQ; > + UINT32 Interrupt; > + UINT8 Baud_Rate; > + UINT8 Parity; > + UINT8 Stop_Bits; > + UINT8 Flow_Control; > + UINT8 Terminal_Type; > + UINT8 Reserved2; > + UINT16 PCI_Device_ID; > + UINT16 PCI_Vender_ID; > + UINT8 PCI_Bus; > + UINT8 PCI_Device; > + UINT8 PCI_Function; > + UINT32 PCI_Flags; > + UINT8 PCI_Segment; > + UINT32 Reserved3; > +} EFI_ACPI_5_0_SPCR_DESCRIPTION_TABLE; > + > +#pragma pack () > + > +EFI_ACPI_5_0_SPCR_DESCRIPTION_TABLE SPCR = { > + { > + EFI_ACPI_5_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE, > + sizeof (EFI_ACPI_5_0_SPCR_DESCRIPTION_TABLE), > + 0x02, > + 0x00, // Checksum will be updated at runtime > + EFI_ACPI_OEM_ID, > + EFI_ACPI_OEM_TABLE_ID, > + EFI_ACPI_OEM_REVISION, > + EFI_ACPI_CREATOR_ID, > + EFI_ACPI_CREATOR_REVISION, > + }, > + DBG_PORT_SUBTYPE_IMX6, // Serial Interface type = Serial Port Subtypes of the DBG2 > + {0x00, 0x00, 0x00}, // Reserved > + > + // ACPI Generic Address Structure. Set to all zeroes to disable console redirection > + { > + EFI_ACPI_5_0_SYSTEM_MEMORY, // AddressSpaceId: SystemMemory > + 0x20, // RegisterBitWidth > + 0, // RegisterBitOffset > + EFI_ACPI_5_0_DWORD, // AccessSize > + (UINT64)CSP_BASE_REG_PA_UART3 // Address UART3 > + }, > + 0x08, // Interrupt Type = Bit[3] ARMH GIC interrupt. 0 means not supported. > + 0x00, // IRQ. Not used since Bit[0] of the Interrupt Type field is not set > + 0x3c, // Global System Interrupt used by the UART (UART3 interrupt 60) > + 0x07, // Baud Rate > + 0x00, // No Parity > + 0x01, // One Stop Bit > + 0x00, // Flow Control: None > + 0x03, // Terminal Type: ANSI > + 0X00, // Reserved > + 0xffff, // 0xFFFF - not a PCI device > + 0xffff, // 0xFFFF - not a PCI device > + 0x00, // Bus Number. 0 - not a PCI device > + 0x00, // Device Number. 0 - not a PCI device > + 0x00, // Function. 0 - not a PCI device > + 0x00000000, // PCI Flags > + 0x00, // PCI Segment > + 0x00000000, //Reserved > +}; > + > +VOID* > +ReferenceAcpiTable ( > + VOID > + ) > +{ > + return (VOID *)&SPCR; > +} > diff --git a/Silicon/NXP/iMX6Pkg/AcpiTables/Tpm2.aslc b/Silicon/NXP/iMX6Pkg/AcpiTables/Tpm2.aslc > new file mode 100644 > index 000000000000..a5abb2bf15d1 > --- /dev/null > +++ b/Silicon/NXP/iMX6Pkg/AcpiTables/Tpm2.aslc > @@ -0,0 +1,53 @@ > +/** @file > +* > +* Copyright (c) 2018 Microsoft Corporation. All rights reserved. > +* > +* This program and the accompanying materials > +* are licensed and made available under the terms and conditions of the BSD License > +* which accompanies this distribution. The full text of the license may be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +* > +**/ > + > +#include > + > +#include > + > +#include > +#include "iMX6.h" > + > +// Definition is missing from MdePkg/Include/IndustryStandard/Tpm2Acpi.h > +#ifdef EFI_TPM2_ACPI_TABLE_START_METHOD_COMMAND_RESPONSE_BUFFER_INTERFACE_WITH_TREE > +#error "EFI_TPM2_ACPI_TABLE_START_METHOD_COMMAND_RESPONSE_BUFFER_INTERFACE_WITH_TREE is defined elsewhere." > +#else > +#define EFI_TPM2_ACPI_TABLE_START_METHOD_COMMAND_RESPONSE_BUFFER_INTERFACE_WITH_TREE 9 > +#endif > + > +EFI_TPM2_ACPI_TABLE Tpm2Table = { > + { > + EFI_ACPI_5_0_TRUSTED_COMPUTING_PLATFORM_2_TABLE_SIGNATURE, > + sizeof (EFI_TPM2_ACPI_TABLE), > + EFI_TPM2_ACPI_TABLE_REVISION, > + 0, // Checksum will be updated at runtime > + EFI_ACPI_OEM_ID, // OEMID is a 6 bytes long field > + EFI_ACPI_OEM_TABLE_ID, // OEM table identification(8 bytes long) > + EFI_ACPI_OEM_REVISION, // OEM revision number > + EFI_ACPI_CREATOR_ID, // Creator vendor ID > + EFI_ACPI_CREATOR_REVISION, // Creator revision number > + }, > + 0, // Flags > + FixedPcdGet64 (PcdTpm2AcpiBufferBase), // Control Area > + // StartMethod > + EFI_TPM2_ACPI_TABLE_START_METHOD_COMMAND_RESPONSE_BUFFER_INTERFACE_WITH_TREE, > +}; > + > +VOID* > +ReferenceAcpiTable ( > + VOID > + ) > +{ > + return (VOID *)&Tpm2Table; > +} > -- > 2.16.2.gvfs.1.33.gf5370f1 >