From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::442; helo=mail-wr1-x442.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 09B452119A84D for ; Tue, 18 Dec 2018 04:31:46 -0800 (PST) Received: by mail-wr1-x442.google.com with SMTP id t27so15732107wra.6 for ; Tue, 18 Dec 2018 04:31:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=yRIpUzQNmtjzg7dkz/fw0znqNuXjZNFI3KA1ri/Lqqc=; b=ND0A59bZc56denjOxWlQ+u3SFc7l08+TVG1h4GHMbWP7uG9DOidFU6WqVKsuX/7xkE K+ZlWAsYcQUJiqMnFbZ+V1TKeoeF+24ikQIjxBbDAlvZv0a58PQuGwSKTV04j2KLDQrm 2DS5cSHamYiqLWOBGbHrpID7i924XqaT1S4oE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=yRIpUzQNmtjzg7dkz/fw0znqNuXjZNFI3KA1ri/Lqqc=; b=LqiSqqVWDrwOY8rDDrSKpBgc22y2K3gfMlMxJvTdOzY4ZPsoYroAe6g1kqR/lZ5eeZ lC7eHr9n0S5hdJC3g7Eq3ZWW2nM+RfOOLK2cP0/AccGEdNWp4JpnrQgGZXY9KTM8u4Qy iHbXpSqTEJy/wt/300oEujFM0p7cQgNUxJdUW+0kW2m2GkAB35PYIyxE/fe84b54zutu KwEb5TbkqU6r6OfiqGfR57BOuxbGLp0HutD50skcC0iK3HTeHa1PE4bOzzR945okmFmg 1fddrNNyVK7ABSUmDIw1YkHsC9GWvzGPXTEFL11iRzRRgqpAJnNhZ9q5rWiDVoC3s8Ag ob4w== X-Gm-Message-State: AA+aEWZxQYrVT+KrBYf/KTNxxFEUli5GuNLE80f4r1derpBxKENltGjG +WMf0DRvuEvxvNsCurz4Wn9Ftg== X-Google-Smtp-Source: AFSGD/V5Ph9rn0Hvd5CT/ymEFui7xyKp7lR/pPdCQ5MafjAkY2fGQyPnA6fpVspiNwsRp87cqYSAzw== X-Received: by 2002:adf:b243:: with SMTP id y3mr15076181wra.184.1545136305025; Tue, 18 Dec 2018 04:31:45 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id o16sm2515080wrn.11.2018.12.18.04.31.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 18 Dec 2018 04:31:44 -0800 (PST) Date: Tue, 18 Dec 2018 12:31:42 +0000 From: Leif Lindholm To: Meenakshi Aggarwal Cc: ard.biesheuvel@linaro.org, michael.d.kinney@intel.com, edk2-devel@lists.01.org, udit.kumar@nxp.com, v.sethi@nxp.com Message-ID: <20181218123142.h3utnmgtkkpe73dw@bivouac.eciton.net> References: <1518771035-6733-1-git-send-email-meenakshi.aggarwal@nxp.com> <1543417315-5763-1-git-send-email-meenakshi.aggarwal@nxp.com> <1543417315-5763-4-git-send-email-meenakshi.aggarwal@nxp.com> MIME-Version: 1.0 In-Reply-To: <1543417315-5763-4-git-send-email-meenakshi.aggarwal@nxp.com> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms 03/41] SocLib : Add support for initialization of peripherals X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 18 Dec 2018 12:31:47 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Nov 28, 2018 at 08:31:17PM +0530, Meenakshi Aggarwal wrote: > Add SocInit function that initializes peripherals > and print board and soc information. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Meenakshi Aggarwal > --- > Silicon/NXP/Include/Chassis2/SerDes.h | 68 +++++ > Silicon/NXP/Include/Chassis2/Soc.h | 367 ++++++++++++++++++++++++++ > Silicon/NXP/LS1043A/Include/SocSerDes.h | 57 ++++ > Silicon/NXP/Library/SocLib/Chassis.c | 372 +++++++++++++++++++++++++++ > Silicon/NXP/Library/SocLib/Chassis.h | 144 +++++++++++ > Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 167 ++++++++++++ > Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 49 ++++ > Silicon/NXP/Library/SocLib/SerDes.c | 271 +++++++++++++++++++ > 8 files changed, 1495 insertions(+) > create mode 100644 Silicon/NXP/Include/Chassis2/SerDes.h > create mode 100644 Silicon/NXP/Include/Chassis2/Soc.h > create mode 100644 Silicon/NXP/LS1043A/Include/SocSerDes.h > create mode 100644 Silicon/NXP/Library/SocLib/Chassis.c > create mode 100644 Silicon/NXP/Library/SocLib/Chassis.h > create mode 100644 Silicon/NXP/Library/SocLib/Chassis2/Soc.c > create mode 100644 Silicon/NXP/Library/SocLib/LS1043aSocLib.inf > create mode 100644 Silicon/NXP/Library/SocLib/SerDes.c > > diff --git a/Silicon/NXP/Include/Chassis2/SerDes.h b/Silicon/NXP/Include/Chassis2/SerDes.h > new file mode 100644 > index 0000000..4c874aa > --- /dev/null > +++ b/Silicon/NXP/Include/Chassis2/SerDes.h > @@ -0,0 +1,68 @@ > +/** SerDes.h > + The Header file of SerDes Module for Chassis 2 > + > + Copyright 2017 NXP > + > + This program and the accompanying materials > + are licensed and made available under the terms and conditions of the BSD License > + which accompanies this distribution. The full text of the license may be found > + http://opensource.org/licenses/bsd-license.php > + > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > + > +**/ > + > +#ifndef __SERDES_H__ > +#define __SERDES_H__ SERDES is a bit too generic. Please add an NXP_ prefix, or more if you can come up with something that pins it down to the group of users of this header (QORIQ?). > + > +#include > + > +#define SRDS_MAX_LANES 4 > + > +typedef enum { > + NONE = 0, > + PCIE1, > + PCIE2, > + PCIE3, > + SATA, > + SGMII_FM1_DTSEC1, > + SGMII_FM1_DTSEC2, > + SGMII_FM1_DTSEC5, > + SGMII_FM1_DTSEC6, > + SGMII_FM1_DTSEC9, > + SGMII_FM1_DTSEC10, > + QSGMII_FM1_A, > + XFI_FM1_MAC9, > + XFI_FM1_MAC10, > + SGMII_2500_FM1_DTSEC2, > + SGMII_2500_FM1_DTSEC5, > + SGMII_2500_FM1_DTSEC9, > + SGMII_2500_FM1_DTSEC10, > + SERDES_PRTCL_COUNT As per https://edk2-docs.gitbooks.io/edk-ii-c-coding-standards-specification/content/5_source_files/56_declarations_and_types.html#5622-enumerated-types please rename enum members to CamelCase. (Please apply throughout set.) Yes, I missed this in my previous review - apologies for that. > +} SERDES_PROTOCOL; > + > +typedef enum { > + SRDS_1 = 0, > + SRDS_2, > + SRDS_MAX_NUM > +} SERDES_NUMBER; > + > +typedef struct { > + UINT16 Protocol; > + UINT8 SrdsLane[SRDS_MAX_LANES]; > +} SERDES_CONFIG; > + > +typedef VOID > +(*SERDES_PROBE_LANES_CALLBACK) ( > + IN SERDES_PROTOCOL LaneProtocol, > + IN VOID *Arg > + ); > + > +VOID > +SerDesProbeLanes( > + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback, > + IN VOID *Arg > + ); > + > +#endif /* __SERDES_H */ > diff --git a/Silicon/NXP/Include/Chassis2/Soc.h b/Silicon/NXP/Include/Chassis2/Soc.h > new file mode 100644 > index 0000000..10e99ab > --- /dev/null > +++ b/Silicon/NXP/Include/Chassis2/Soc.h > @@ -0,0 +1,367 @@ > +/** Soc.h > +* Header defining the Base addresses, sizes, flags etc for chassis 1 > +* > +* Copyright 2017 NXP > +* > +* This program and the accompanying materials > +* are licensed and made available under the terms and conditions of the BSD License > +* which accompanies this distribution. The full text of the license may be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +* > +**/ > + > +#ifndef __SOC_H__ > +#define __SOC_H__ NXP_PREFIX please. > + > +#define HWA_CGA_M1_CLK_SEL 0xe0000000 > +#define HWA_CGA_M1_CLK_SHIFT 29 > + > +#define TP_CLUSTER_EOC_MASK 0xc0000000 /* end of clusters mask */ > +#define NUM_CC_PLLS 2 > +#define CLK_FREQ 100000000 > +#define MAX_CPUS 4 > +#define NUM_FMAN 1 > +#define CHECK_CLUSTER(Cluster) ((Cluster & TP_CLUSTER_EOC_MASK) == 0x0) > + > +/* RCW SERDES MACRO */ > +#define RCWSR_INDEX 4 > +#define RCWSR_SRDS1_PRTCL_MASK 0xffff0000 > +#define RCWSR_SRDS1_PRTCL_SHIFT 16 > +#define RCWSR_SRDS2_PRTCL_MASK 0x0000ffff > +#define RCWSR_SRDS2_PRTCL_SHIFT 0 > + > +/* SMMU Defintions */ > +#define SMMU_BASE_ADDR 0x09000000 > +#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0) > +#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10) > +#define SMMU_REG_IDR1 (SMMU_BASE_ADDR + 0x24) > +#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400) > +#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410) > + > +#define SCR0_USFCFG_MASK 0x00000400 > +#define SCR0_CLIENTPD_MASK 0x00000001 > +#define SACR_PAGESIZE_MASK 0x00010000 > +#define IDR1_PAGESIZE_MASK 0x80000000 > + > +typedef struct { > + UINTN FreqProcessor[MAX_CPUS]; > + UINTN FreqSystemBus; > + UINTN FreqDdrBus; > + UINTN FreqLocalBus; > + UINTN FreqSdhc; > + UINTN FreqFman[NUM_FMAN]; > + UINTN FreqQman; > +} SYS_INFO; > + > +/* Device Configuration and Pin Control */ > +typedef struct { > + UINT32 PorSr1; /* POR status 1 */ > +#define CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000 > + UINT32 PorSr2; /* POR status 2 */ > + UINT8 Res008[0x20-0x8]; > + UINT32 GppOrCr1; /* General-purpose POR configuration */ > + UINT32 GppOrCr2; > + UINT32 DcfgFuseSr; /* Fuse status register */ > + UINT8 Res02c[0x70-0x2c]; > + UINT32 DevDisr; /* Device disable control */ > + UINT32 DevDisr2; /* Device disable control 2 */ > + UINT32 DevDisr3; /* Device disable control 3 */ > + UINT32 DevDisr4; /* Device disable control 4 */ > + UINT32 DevDisr5; /* Device disable control 5 */ > + UINT32 DevDisr6; /* Device disable control 6 */ > + UINT32 DevDisr7; /* Device disable control 7 */ > + UINT8 Res08c[0x94-0x8c]; > + UINT32 CoreDisrU; /* uppper portion for support of 64 cores */ > + UINT32 CoreDisrL; /* lower portion for support of 64 cores */ > + UINT8 Res09c[0xa0-0x9c]; > + UINT32 Pvr; /* Processor version */ > + UINT32 Svr; /* System version */ > + UINT32 Mvr; /* Manufacturing version */ > + UINT8 Res0ac[0xb0-0xac]; > + UINT32 RstCr; /* Reset control */ > + UINT32 RstRqPblSr; /* Reset request preboot loader status */ > + UINT8 Res0b8[0xc0-0xb8]; > + UINT32 RstRqMr1; /* Reset request mask */ > + UINT8 Res0c4[0xc8-0xc4]; > + UINT32 RstRqSr1; /* Reset request status */ > + UINT8 Res0cc[0xd4-0xcc]; > + UINT32 RstRqWdTmrL; /* Reset request WDT mask */ > + UINT8 Res0d8[0xdc-0xd8]; > + UINT32 RstRqWdtSrL; /* Reset request WDT status */ > + UINT8 Res0e0[0xe4-0xe0]; > + UINT32 BrrL; /* Boot release */ > + UINT8 Res0e8[0x100-0xe8]; > + UINT32 RcwSr[16]; /* Reset control word status */ > +#define CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25 > +#define CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f > +#define CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16 > +#define CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f > + UINT8 Res140[0x200-0x140]; > + UINT32 ScratchRw[4]; /* Scratch Read/Write */ > + UINT8 Res210[0x300-0x210]; > + UINT32 ScratcHw1R[4]; /* Scratch Read (Write once) */ > + UINT8 Res310[0x400-0x310]; > + UINT32 CrstSr[12]; > + UINT8 Res430[0x500-0x430]; > + /* PCI Express n Logical I/O Device Number register */ > + UINT32 DcfgCcsrPex1LiodNr; > + UINT32 DcfgCcsrPex2LiodNr; > + UINT32 DcfgCcsrPex3LiodNr; > + UINT32 DcfgCcsrPex4LiodNr; > + /* RIO n Logical I/O Device Number register */ > + UINT32 DcfgCcsrRio1LiodNr; > + UINT32 DcfgCcsrRio2LiodNr; > + UINT32 DcfgCcsrRio3LiodNr; > + UINT32 DcfgCcsrRio4LiodNr; > + /* USB Logical I/O Device Number register */ > + UINT32 DcfgCcsrUsb1LiodNr; > + UINT32 DcfgCcsrUsb2LiodNr; > + UINT32 DcfgCcsrUsb3LiodNr; > + UINT32 DcfgCcsrUsb4LiodNr; > + /* SD/MMC Logical I/O Device Number register */ > + UINT32 DcfgCcsrSdMmc1LiodNr; > + UINT32 DcfgCcsrSdMmc2LiodNr; > + UINT32 DcfgCcsrSdMmc3LiodNr; > + UINT32 DcfgCcsrSdMmc4LiodNr; > + /* RIO Message Unit Logical I/O Device Number register */ > + UINT32 DcfgCcsrRiomaintLiodNr; > + UINT8 Res544[0x550-0x544]; > + UINT32 SataLiodNr[4]; > + UINT8 Res560[0x570-0x560]; > + UINT32 DcfgCcsrMisc1LiodNr; > + UINT32 DcfgCcsrMisc2LiodNr; > + UINT32 DcfgCcsrMisc3LiodNr; > + UINT32 DcfgCcsrMisc4LiodNr; > + UINT32 DcfgCcsrDma1LiodNr; > + UINT32 DcfgCcsrDma2LiodNr; > + UINT32 DcfgCcsrDma3LiodNr; > + UINT32 DcfgCcsrDma4LiodNr; > + UINT32 DcfgCcsrSpare1LiodNr; > + UINT32 DcfgCcsrSpare2LiodNr; > + UINT32 DcfgCcsrSpare3LiodNr; > + UINT32 DcfgCcsrSpare4LiodNr; > + UINT8 Res5a0[0x600-0x5a0]; > + UINT32 DcfgCcsrPblSr; > + UINT32 PamuBypENr; > + UINT32 DmaCr1; > + UINT8 Res60c[0x610-0x60c]; > + UINT32 DcfgCcsrGenSr1; > + UINT32 DcfgCcsrGenSr2; > + UINT32 DcfgCcsrGenSr3; > + UINT32 DcfgCcsrGenSr4; > + UINT32 DcfgCcsrGenCr1; > + UINT32 DcfgCcsrGenCr2; > + UINT32 DcfgCcsrGenCr3; > + UINT32 DcfgCcsrGenCr4; > + UINT32 DcfgCcsrGenCr5; > + UINT32 DcfgCcsrGenCr6; > + UINT32 DcfgCcsrGenCr7; > + UINT8 Res63c[0x658-0x63c]; > + UINT32 DcfgCcsrcGenSr1; > + UINT32 DcfgCcsrcGenSr0; > + UINT8 Res660[0x678-0x660]; > + UINT32 DcfgCcsrcGenCr1; > + UINT32 DcfgCcsrcGenCr0; > + UINT8 Res680[0x700-0x680]; > + UINT32 DcfgCcsrSrIoPstecr; > + UINT32 DcfgCcsrDcsrCr; > + UINT8 Res708[0x740-0x708]; /* add more registers when needed */ > + UINT32 TpItyp[64]; /* Topology Initiator Type Register */ > + struct { > + UINT32 Upper; > + UINT32 Lower; > + } TpCluster[16]; > + UINT8 Res8c0[0xa00-0x8c0]; /* add more registers when needed */ > + UINT32 DcfgCcsrQmBmWarmRst; > + UINT8 Resa04[0xa20-0xa04]; /* add more registers when needed */ > + UINT32 DcfgCcsrReserved0; > + UINT32 DcfgCcsrReserved1; > +} CCSR_GUR; > + > +/* Supplemental Configuration Unit */ > +typedef struct { > + UINT8 Res000[0x070-0x000]; > + UINT32 Usb1Prm1Cr; > + UINT32 Usb1Prm2Cr; > + UINT32 Usb1Prm3Cr; > + UINT32 Usb2Prm1Cr; > + UINT32 Usb2Prm2Cr; > + UINT32 Usb2Prm3Cr; > + UINT32 Usb3Prm1Cr; > + UINT32 Usb3Prm2Cr; > + UINT32 Usb3Prm3Cr; > + UINT8 Res094[0x100-0x094]; > + UINT32 Usb2Icid; > + UINT32 Usb3Icid; > + UINT8 Res108[0x114-0x108]; > + UINT32 DmaIcid; > + UINT32 SataIcid; > + UINT32 Usb1Icid; > + UINT32 QeIcid; > + UINT32 SdhcIcid; > + UINT32 EdmaIcid; > + UINT32 EtrIcid; > + UINT32 Core0SftRst; > + UINT32 Core1SftRst; > + UINT32 Core2SftRst; > + UINT32 Core3SftRst; > + UINT8 Res140[0x158-0x140]; > + UINT32 AltCBar; > + UINT32 QspiCfg; > + UINT8 Res160[0x180-0x160]; > + UINT32 DmaMcr; > + UINT8 Res184[0x188-0x184]; > + UINT32 GicAlign; > + UINT32 DebugIcid; > + UINT8 Res190[0x1a4-0x190]; > + UINT32 SnpCnfGcr; > +#define CCSR_SCFG_SNPCNFGCR_SECRDSNP BIT31 > +#define CCSR_SCFG_SNPCNFGCR_SECWRSNP BIT30 > +#define CCSR_SCFG_SNPCNFGCR_SATARDSNP BIT23 > +#define CCSR_SCFG_SNPCNFGCR_SATAWRSNP BIT22 > +#define CCSR_SCFG_SNPCNFGCR_USB1RDSNP BIT21 > +#define CCSR_SCFG_SNPCNFGCR_USB1WRSNP BIT20 > +#define CCSR_SCFG_SNPCNFGCR_USB2RDSNP BIT15 > +#define CCSR_SCFG_SNPCNFGCR_USB2WRSNP BIT16 > +#define CCSR_SCFG_SNPCNFGCR_USB3RDSNP BIT13 > +#define CCSR_SCFG_SNPCNFGCR_USB3WRSNP BIT14 > + UINT8 Res1a8[0x1ac-0x1a8]; > + UINT32 IntpCr; > + UINT8 Res1b0[0x204-0x1b0]; > + UINT32 CoreSrEnCr; > + UINT8 Res208[0x220-0x208]; > + UINT32 RvBar00; > + UINT32 RvBar01; > + UINT32 RvBar10; > + UINT32 RvBar11; > + UINT32 RvBar20; > + UINT32 RvBar21; > + UINT32 RvBar30; > + UINT32 RvBar31; > + UINT32 LpmCsr; > + UINT8 Res244[0x400-0x244]; > + UINT32 QspIdQScr; > + UINT32 EcgTxcMcr; > + UINT32 SdhcIoVSelCr; > + UINT32 RcwPMuxCr0; > + /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS > + *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT > + *Setting RCW PinMux Register bits 25-27 to select USB3_DRVVBUS > + Setting RCW PinMux Register bits 29-31 to select USB3_DRVVBUS*/ > +#define CCSR_SCFG_RCWPMUXCRO_SELCR_USB 0x3333 > + /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS > + *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT > + *Setting RCW PinMux Register bits 25-27 to select IIC4_SCL > + Setting RCW PinMux Register bits 29-31 to select IIC4_SDA*/ > +#define CCSR_SCFG_RCWPMUXCRO_NOT_SELCR_USB 0x3300 > + UINT32 UsbDrvVBusSelCr; > +#define CCSR_SCFG_USBDRVVBUS_SELCR_USB1 0x00000000 > +#define CCSR_SCFG_USBDRVVBUS_SELCR_USB2 0x00000001 > +#define CCSR_SCFG_USBDRVVBUS_SELCR_USB3 0x00000003 > + UINT32 UsbPwrFaultSelCr; > +#define CCSR_SCFG_USBPWRFAULT_INACTIVE 0x00000000 > +#define CCSR_SCFG_USBPWRFAULT_SHARED 0x00000001 > +#define CCSR_SCFG_USBPWRFAULT_DEDICATED 0x00000002 > +#define CCSR_SCFG_USBPWRFAULT_USB3_SHIFT 4 > +#define CCSR_SCFG_USBPWRFAULT_USB2_SHIFT 2 > +#define CCSR_SCFG_USBPWRFAULT_USB1_SHIFT 0 > + UINT32 UsbRefclkSelcr1; > + UINT32 UsbRefclkSelcr2; > + UINT32 UsbRefclkSelcr3; > + UINT8 Res424[0x600-0x424]; > + UINT32 ScratchRw[4]; > + UINT8 Res610[0x680-0x610]; > + UINT32 CoreBCr; > + UINT8 Res684[0x1000-0x684]; > + UINT32 Pex1MsiIr; > + UINT32 Pex1MsiR; > + UINT8 Res1008[0x2000-0x1008]; > + UINT32 Pex2; > + UINT32 Pex2MsiR; > + UINT8 Res2008[0x3000-0x2008]; > + UINT32 Pex3MsiIr; > + UINT32 Pex3MsiR; > +} CCSR_SCFG; > + > +#define USB_TXVREFTUNE 0x9 > +#define USB_SQRXTUNE 0xFC7FFFFF > +#define USB_PCSTXSWINGFULL 0x47 > +#define USB_PHY_RX_EQ_VAL_1 0x0000 > +#define USB_PHY_RX_EQ_VAL_2 0x8000 > +#define USB_PHY_RX_EQ_VAL_3 0x8003 > +#define USB_PHY_RX_EQ_VAL_4 0x800b > + > +/*USB_PHY_SS memory map*/ > +typedef struct { > + UINT16 IpIdcodeLo; > + UINT16 SupIdcodeHi; > + UINT8 Res4[0x0006-0x0004]; > + UINT16 RtuneDebug; > + UINT16 RtuneStat; > + UINT16 SupSsPhase; > + UINT16 SsFreq; > + UINT8 ResE[0x0020-0x000e]; > + UINT16 Ateovrd; > + UINT16 MpllOvrdInLo; > + UINT8 Res24[0x0026-0x0024]; > + UINT16 SscOvrdIn; > + UINT8 Res28[0x002A-0x0028]; > + UINT16 LevelOvrdIn; > + UINT8 Res2C[0x0044-0x002C]; > + UINT16 ScopeCount; > + UINT8 Res46[0x0060-0x0046]; > + UINT16 MpllLoopCtl; > + UINT8 Res62[0x006C-0x0062]; > + UINT16 SscClkCntrl; > + UINT8 Res6E[0x2002-0x006E]; > + UINT16 Lane0TxOvrdInHi; > + UINT16 Lane0TxOvrdDrvLo; > + UINT8 Res2006[0x200C-0x2006]; > + UINT16 Lane0RxOvrdInHi; > + UINT8 Res200E[0x2022-0x200E]; > + UINT16 Lane0TxCmWaitTimeOvrd; > + UINT8 Res2024[0x202A-0x2024]; > + UINT16 Lane0TxLbertCtl; > + UINT16 Lane0RxLbertCtl; > + UINT16 Lane0RxLbertErr; > + UINT8 Res2030[0x205A-0x2030]; > + UINT16 Lane0TxAltBlock; > +} CCSR_USB_PHY; > + > +/* Clocking */ > +typedef struct { > + struct { > + UINT32 ClkCnCSr; /* core cluster n clock control status */ > + UINT8 Res004[0x0c]; > + UINT32 ClkcGHwAcSr; /* Clock generator n hardware accelerator */ > + UINT8 Res014[0x0c]; > + } ClkcSr[4]; > + UINT8 Res040[0x780]; /* 0x100 */ > + struct { > + UINT32 PllCnGSr; > + UINT8 Res804[0x1c]; > + } PllCgSr[NUM_CC_PLLS]; > + UINT8 Res840[0x1c0]; > + UINT32 ClkPCSr; /* 0xa00 Platform clock domain control/status */ > + UINT8 Resa04[0x1fc]; > + UINT32 PllPGSr; /* 0xc00 Platform PLL General Status */ > + UINT8 Resc04[0x1c]; > + UINT32 PllDGSr; /* 0xc20 DDR PLL General Status */ > + UINT8 Resc24[0x3dc]; > +} CCSR_CLOCK; > + > +VOID > +GetSysInfo ( > + OUT SYS_INFO * > + ); > + > +UINT32 > +EFIAPI > +GurRead ( > + IN UINTN Address > + ); > + > +#endif /* __SOC_H__ */ > diff --git a/Silicon/NXP/LS1043A/Include/SocSerDes.h b/Silicon/NXP/LS1043A/Include/SocSerDes.h > new file mode 100644 > index 0000000..7707e2a > --- /dev/null > +++ b/Silicon/NXP/LS1043A/Include/SocSerDes.h > @@ -0,0 +1,57 @@ > +/** @file > + The Header file of SerDes Module for LS1043A > + > + Copyright 2017 NXP > + > + This program and the accompanying materials > + are licensed and made available under the terms and conditions of the BSD License > + which accompanies this distribution. The full text of the license may be found > + http://opensource.org/licenses/bsd-license.php > + > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > + > +**/ > + > +#ifndef __SOC_SERDES_H__ > +#define __SOC_SERDES_H__ > + > +#ifdef CHASSIS2 > +#include > +#endif > + > +SERDES_CONFIG SerDes1ConfigTbl[] = { > + /* SerDes 1 */ > + {0x1555, {XFI_FM1_MAC9, PCIE1, PCIE2, PCIE3 } }, > + {0x2555, {SGMII_2500_FM1_DTSEC9, PCIE1, PCIE2, PCIE3 } }, > + {0x4555, {QSGMII_FM1_A, PCIE1, PCIE2, PCIE3 } }, > + {0x4558, {QSGMII_FM1_A, PCIE1, PCIE2, SATA } }, > + {0x1355, {XFI_FM1_MAC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } }, > + {0x2355, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } }, > + {0x3335, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, PCIE3 } }, > + {0x3355, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } }, > + {0x3358, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, SATA } }, > + {0x3555, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, PCIE3 } }, > + {0x3558, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, SATA } }, > + {0x7000, {PCIE1, PCIE1, PCIE1, PCIE1 } }, > + {0x9998, {PCIE1, PCIE2, PCIE3, SATA } }, > + {0x6058, {PCIE1, PCIE1, PCIE2, SATA } }, > + {0x1455, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE2, PCIE3 } }, > + {0x2455, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3 } }, > + {0x2255, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC2, PCIE2, PCIE3 } }, > + {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } }, > + {0x1460, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE3, PCIE3 } }, > + {0x2460, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE3, PCIE3 } }, > + {0x3460, {SGMII_FM1_DTSEC9, QSGMII_FM1_A, PCIE3, PCIE3 } }, > + {0x3455, {SGMII_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3 } }, > + {0x9960, {PCIE1, PCIE2, PCIE3, PCIE3 } }, > + {0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } }, > + {0x2533, {SGMII_2500_FM1_DTSEC9, PCIE1, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } }, > + {} > +}; > + > +SERDES_CONFIG *SerDesConfigTbl[] = { > + SerDes1ConfigTbl > +}; > + > +#endif /* __SOC_SERDES_H */ > diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c > new file mode 100644 > index 0000000..851174c > --- /dev/null > +++ b/Silicon/NXP/Library/SocLib/Chassis.c > @@ -0,0 +1,372 @@ > +/** @file > + SoC specific Library containg functions to initialize various SoC components > + > + Copyright 2017 NXP > + > + This program and the accompanying materials > + are licensed and made available under the terms and conditions of the BSD License > + which accompanies this distribution. The full text of the license may be found at > + http://opensource.org/licenses/bsd-license.php > + > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > + > +**/ > + > +#include > +#ifdef CHASSIS2 > +#include > +#endif > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "Chassis.h" > + > +UINT32 > +EFIAPI > +GurRead ( > + IN UINTN Address > + ) > +{ > + if (FixedPcdGetBool (PcdGurBigEndian)) { > + return SwapMmioRead32 (Address); > + } else { > + return MmioRead32 (Address); > + } > +} > + > +/* > + * Structure to list available SOCs. > + */ > +STATIC CPU_TYPE CpuTypeList[] = { STATIC global variables need an m-prefix: https://edk2-docs.gitbooks.io/edk-ii-c-coding-standards-specification/content/4_naming_conventions/43_identifiers.html#4332-any-variable-with-file-scope-or-better-shall-be-prefixed-by-an-m-or-g > + CPU_TYPE_ENTRY (LS1043A, LS1043A, 4), Please put a comment near here explaining at least the 4. > +}; > + > +/* > + * Return the type of initiator (core or hardware accelerator) > + */ > +UINT32 > +InitiatorType ( > + IN UINT32 Cluster, > + IN UINTN InitId > + ) > +{ > + CCSR_GUR *GurBase; > + UINT32 Idx; > + UINT32 Type; > + > + GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr); > + Idx = (Cluster >> (InitId * 8)) & TP_CLUSTER_INIT_MASK; > + Type = GurRead ((UINTN)&GurBase->TpItyp[Idx]); > + > + if (Type & TP_ITYP_AV_MASK) { > + return Type; > + } > + > + return 0; > +} > + > +/* > + * Return the mask for number of cores on this SOC. > + */ > +UINT32 > +CpuMask ( > + VOID > + ) > +{ > + CCSR_GUR *GurBase; > + UINTN ClusterIndex; > + UINTN Count; > + UINT32 Cluster; > + UINT32 Type; > + UINT32 Mask; > + UINTN InitiatorIndex; > + > + GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr); > + ClusterIndex = 0; > + Count = 0; > + Mask = 0; > + > + do { > + Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower); > + for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) { > + Type = InitiatorType (Cluster, InitiatorIndex); > + if (Type) { > + if (TP_ITYP_TYPE_MASK (Type) == TP_ITYP_TYPE_ARM) { > + Mask |= 1 << Count; > + } > + Count++; > + } > + } > + ClusterIndex++; > + } while (CHECK_CLUSTER (Cluster)); > + > + return Mask; > +} > + > +/* > + * Return the number of cores on this SOC. > + */ > +UINTN > +CpuNumCores ( > + VOID > + ) > +{ > + UINTN Count; > + UINTN Num; > + > + Count = 0; > + Num = CpuMask (); > + > + while (Num) { > + Count += Num & 1; > + Num >>= 1; > + } > + > + return Count; > +} > + > +/* > + * Return the type of core i.e. A53, A57 etc of inputted > + * core number. > + */ > +UINTN > +QoriqCoreToType ( > + IN UINTN Core > + ) > +{ > + CCSR_GUR *GurBase; > + UINTN ClusterIndex; > + UINTN Count; > + UINT32 Cluster; > + UINT32 Type; > + UINTN InitiatorIndex; > + > + GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr); > + ClusterIndex = 0; > + Count = 0; > + > + do { > + Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower); > + for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) { > + Type = InitiatorType (Cluster, InitiatorIndex); > + if (Type) { > + if (Count == Core) { > + return Type; > + } > + Count++; > + } > + } > + ClusterIndex++; > + } while (CHECK_CLUSTER (Cluster)); > + > + return EFI_NOT_FOUND; /* cannot identify the cluster */ > +} > + > +/* > + * Print CPU information > + */ > +VOID > +PrintCpuInfo ( > + VOID > + ) > +{ > + SYS_INFO SysInfo; > + UINTN CoreIndex; > + UINTN Core; > + UINT32 Type; > + CHAR8 Buffer[50]; Unless something non-obvious is going on here, you shouldn't need a buffer here (which helps get around the bit where I'm ask you to get rid of the statically sized array). If you do: CHAR8 *CoreName; > + > + GetSysInfo (&SysInfo); > + DEBUG ((DEBUG_INIT, "Clock Configuration:")); > + > + ForEachCpu (CoreIndex, Core, CpuNumCores (), CpuMask ()) { > + if (!(CoreIndex % 3)) { > + DEBUG ((DEBUG_INIT, "\n ")); > + } > + > + Type = TP_ITYP_VERSION (QoriqCoreToType (Core)); > + switch (Type) { > + case TY_ITYP_VERSION_A7: > + AsciiStrCpy (Buffer, "A7"); Then you can replace this copy with CoreName = "A7"; and so on (And if something non-obvious is going on, please add a comment describing it.) > + break; > + case TY_ITYP_VERSION_A53: > + AsciiStrCpy (Buffer, "A53"); > + break; > + case TY_ITYP_VERSION_A57: > + AsciiStrCpy (Buffer, "A57"); > + break; > + case TY_ITYP_VERSION_A72: > + AsciiStrCpy (Buffer, "A72"); > + break; > + default: > + AsciiStrCpy (Buffer, " Unknown Core "); > + } > + DEBUG ((DEBUG_INIT, "CPU%d(%a):%-4d MHz ", Core, Buffer, SysInfo.FreqProcessor[Core] / MHZ)); > + } > + > + DEBUG ((DEBUG_INIT, "\n Bus: %-4d MHz ", SysInfo.FreqSystemBus / MHZ)); > + DEBUG ((DEBUG_INIT, "DDR: %-4d MT/s", SysInfo.FreqDdrBus / MHZ)); > + > + if (SysInfo.FreqFman[0] != 0) { > + DEBUG ((DEBUG_INIT, "\n FMAN: %-4d MHz ", SysInfo.FreqFman[0] / MHZ)); > + } > + > + DEBUG ((DEBUG_INIT, "\n")); > +} > + > +/* > + * Return system bus frequency > + */ > +UINT64 > +GetBusFrequency ( > + VOID > + ) > +{ > + SYS_INFO SocSysInfo; > + > + GetSysInfo (&SocSysInfo); > + > + return SocSysInfo.FreqSystemBus; > +} > + > +/* > + * Return SDXC bus frequency > + */ > +UINT64 > +GetSdxcFrequency ( > + VOID > + ) > +{ > + SYS_INFO SocSysInfo; > + > + GetSysInfo (&SocSysInfo); > + > + return SocSysInfo.FreqSdhc; > +} > + > +/* > + * Print Soc information > + */ > +VOID > +PrintSoc ( > + VOID > + ) > +{ > + CHAR8 Buf[16]; > + CCSR_GUR *GurBase; > + UINTN Count; > + UINTN Svr; Can you expand this name to make it clear what it refers to? > + UINTN Ver; > + > + GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr); > + > + Buf[0] = L'\0'; This seems unneeded. StrCat is only ever called after > + Svr = GurRead ((UINTN)&GurBase->Svr); > + Ver = SVR_SOC_VER (Svr); > + > + for (Count = 0; Count < ARRAY_SIZE (CpuTypeList); Count++) Missing { > + if ((CpuTypeList[Count].SocVer & SVR_WO_E) == Ver) { > + AsciiStrCpy (Buf, (CONST CHAR8 *)CpuTypeList[Count].Name); I may be willing to overlook the statically sized buffer above, but if so, all of the String manipulation calls must use the sized versions: AsciiStrCpyS > + > + if (IS_E_PROCESSOR (Svr)) { > + AsciiStrCat (Buf, (CONST CHAR8 *)"E"); AsciiStrCatS > + } > + break; > + } Missing } > + > + if (Count == ARRAY_SIZE (CpuTypeList)) { > + AsciiStrCpy (Buf, (CONST CHAR8 *)"unknown"); AsciiStrCpyS > + } > + > + DEBUG ((DEBUG_INFO, "SoC: %a (0x%x); Rev %d.%d\n", > + Buf, Svr, SVR_MAJOR (Svr), SVR_MINOR (Svr))); > + > + return; > +} > + > +/* > + * Dump RCW (Reset Control Word) on console > + */ > +VOID > +PrintRCW ( > + VOID > + ) > +{ > + CCSR_GUR *Base; > + UINTN Count; > + > + Base = (VOID *)PcdGet64 (PcdGutsBaseAddr); > + > + /* > + * Display the RCW, so that no one gets confused as to what RCW > + * we're actually using for this boot. > + */ > + > + DEBUG ((DEBUG_INIT, "Reset Configuration Word (RCW):")); > + for (Count = 0; Count < ARRAY_SIZE(Base->RcwSr); Count++) { > + UINT32 Rcw = SwapMmioRead32((UINTN)&Base->RcwSr[Count]); > + > + if ((Count % 4) == 0) { > + DEBUG ((DEBUG_INIT, "\n %08x:", Count * 4)); > + } > + > + DEBUG ((DEBUG_INIT, " %08x", Rcw)); > + } > + > + DEBUG ((DEBUG_INIT, "\n")); > +} > + > +/* > + * Setup SMMU in bypass mode > + * and also set its pagesize > + */ > +VOID > +SmmuInit ( > + VOID > + ) > +{ > + UINT32 Value; > + > + /* set pagesize as 64K and ssmu-500 in bypass mode */ > + Value = (MmioRead32 ((UINTN)SMMU_REG_SACR) | SACR_PAGESIZE_MASK); > + MmioWrite32 ((UINTN)SMMU_REG_SACR, Value); > + > + Value = (MmioRead32 ((UINTN)SMMU_REG_SCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK; > + MmioWrite32 ((UINTN)SMMU_REG_SCR0, Value); > + > + Value = (MmioRead32 ((UINTN)SMMU_REG_NSCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK; > + MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value); > +} > + > +/* > + * Return current Soc Name form CpuTypeList > + */ > +CHAR8 * > +GetSocName ( > + VOID > + ) > +{ > + UINT8 Count; > + UINTN Svr; > + UINTN Ver; > + CCSR_GUR *GurBase; > + > + GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr); > + > + Svr = GurRead ((UINTN)&GurBase->Svr); > + Ver = SVR_SOC_VER (Svr); > + > + for (Count = 0; Count < ARRAY_SIZE (CpuTypeList); Count++) { > + if ((CpuTypeList[Count].SocVer & SVR_WO_E) == Ver) { > + return (CHAR8 *)CpuTypeList[Count].Name; > + } > + } > + > + return NULL; > +} > diff --git a/Silicon/NXP/Library/SocLib/Chassis.h b/Silicon/NXP/Library/SocLib/Chassis.h > new file mode 100644 > index 0000000..5aa1209 > --- /dev/null > +++ b/Silicon/NXP/Library/SocLib/Chassis.h > @@ -0,0 +1,144 @@ > +/** @file > +* Header defining the Base addresses, sizes, flags etc for chassis 1 > +* > +* Copyright 2017 NXP > +* > +* This program and the accompanying materials > +* are licensed and made available under the terms and conditions of the BSD License > +* which accompanies this distribution. The full text of the license may be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +* > +**/ > + > +#ifndef __CHASSIS_H__ > +#define __CHASSIS_H__ NXP_ and/or QUORIQ_ prefix? Oh, and please drop leading _ from include guards: https://edk2-docs.gitbooks.io/edk-ii-c-coding-standards-specification/content/5_source_files/53_include_files.html#535-all-include-file-contents-must-be-protected-by-a-include-guard > + > +#define TP_ITYP_AV_MASK 0x00000001 /* Initiator available */ > +#define TP_ITYP_TYPE_MASK(x) (((x) & 0x6) >> 1) /* Initiator Type */ > +#define TP_ITYP_TYPE_ARM 0x0 > +#define TP_ITYP_TYPE_PPC 0x1 > +#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */ > +#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */ > +#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */ > +#define TP_ITYP_VERSION(x) (((x) & 0xe0) >> 5) /* Initiator Version */ > +#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ > +#define TP_INIT_PER_CLUSTER 4 > + > +#define TY_ITYP_VERSION_A7 0x1 > +#define TY_ITYP_VERSION_A53 0x2 > +#define TY_ITYP_VERSION_A57 0x3 > +#define TY_ITYP_VERSION_A72 0x4 > + > +STATIC > +inline > +UINTN > +CpuMaskNext ( https://edk2-docs.gitbooks.io/edk-ii-c-coding-standards-specification/content/5_source_files/53_include_files.html#537-include-files-shall-not-generate-code-or-define-data-variables > + IN UINTN Cpu, > + IN UINTN Mask > + ) > +{ > + for (Cpu++; !((1 << Cpu) & Mask); Cpu++) > + ; > + > + return Cpu; > +} > + > +#define ForEachCpu(Iter, Cpu, NumCpus, Mask) \ > + for (Iter = 0, Cpu = CpuMaskNext(-1, Mask); \ > + Iter < NumCpus; \ > + Iter++, Cpu = CpuMaskNext(Cpu, Mask)) \ Macros are fine, but please drop that trailing \ > + > +#define CPU_TYPE_ENTRY(N, V, NC) \ > + { .Name = #N, .SocVer = SVR_##V, .NumCores = (NC)} > + > +#define SVR_WO_E 0xFFFFFE > +#define SVR_LS1043A 0x879200 > + > +#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf) > +#define SVR_MINOR(svr) (((svr) >> 0) & 0xf) > +#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) > +#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) > + > +#define MHZ 1000000 > + > +typedef struct { > + CHAR8 Name[16]; Shouldn't need a static size, just make it a pointer. > + UINT32 SocVer; > + UINT32 NumCores; > +} CPU_TYPE; No further comments beyond this point. Regards, Leif