From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::444; helo=mail-wr1-x444.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 19698211963C0 for ; Wed, 19 Dec 2018 10:41:20 -0800 (PST) Received: by mail-wr1-x444.google.com with SMTP id r10so20546187wrs.10 for ; Wed, 19 Dec 2018 10:41:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=0aTiwJ7/b2VBZ4pK2MowU8TnrZB+x4EJ4jTpNl1LkbU=; b=DTQFdPxJ+gk3fBpvRFfhTdd74+FQ4aTqU27MMUs8h0epMERdCJbKCNyJmU0rrtzL1x l4/LyydzleSblTdRK/i+Cjp0ZODetuEZqtp1z1zrtKzj93/TNxkjbD+Zp3X+GYOZy5/I VDIp2Dob0kgXaX7MmYkBHNIcm/D57lRMp44/g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=0aTiwJ7/b2VBZ4pK2MowU8TnrZB+x4EJ4jTpNl1LkbU=; b=n1DWznBD+arwIKo1kiHlZfN14i019xQud0zy82ATDXCAxPeZLG2ePys2LbmUkWunS1 gABJ9/ZBS/OfxU2ZF3wsnhiyUB4Uc6BVq0BM1IAuenNM7bGlMqthp4h32y0sAEUBxJlQ g7Eyi8KOvEXTF67vnJiULDQvLIYGSGaugXDg7yyhrENZh4VKJ9s1rREzI8sNIIYgPzyo fpuwZmYMSBjZSogInN9zb5j6ZmbzS+xetnT38aUMzsn5I98FffPe6kUpoiIwFkd6ot2/ Vk5fEuKKkWgrAUgzgJ09hozm2r13KspFD1NRZ5to60hTtEr+i8F5EMICDZVteTSs1eWr WYTg== X-Gm-Message-State: AA+aEWZnyGIICRED7JSvQtju5b2Mv4jZrhJd9anIW6gdWSPVAQNYoMwF 2yAfZfjpDHKgncR0o+bDPUowsg== X-Google-Smtp-Source: AFSGD/VVuUErapjVrO7Ty4geIaLnk/WaJO6IoHMTyF4VLJUJoZ8Nuhzc1VIJX+maKWDZ6MTJu4P6iw== X-Received: by 2002:a5d:4652:: with SMTP id j18mr20210864wrs.279.1545244879364; Wed, 19 Dec 2018 10:41:19 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id 200sm5695403wmw.31.2018.12.19.10.41.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 19 Dec 2018 10:41:18 -0800 (PST) Date: Wed, 19 Dec 2018 18:41:16 +0000 From: Leif Lindholm To: Meenakshi Aggarwal Cc: ard.biesheuvel@linaro.org, michael.d.kinney@intel.com, edk2-devel@lists.01.org, udit.kumar@nxp.com, v.sethi@nxp.com, Vabhav Message-ID: <20181219184116.dx4vk7gr4aibcnqi@bivouac.eciton.net> References: <1518771035-6733-1-git-send-email-meenakshi.aggarwal@nxp.com> <1543417315-5763-1-git-send-email-meenakshi.aggarwal@nxp.com> <1543417315-5763-20-git-send-email-meenakshi.aggarwal@nxp.com> MIME-Version: 1.0 In-Reply-To: <1543417315-5763-20-git-send-email-meenakshi.aggarwal@nxp.com> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms 19/41] Silicon/NXP:Add LS1046ARDB SoCLib Support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 19 Dec 2018 18:41:21 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Nov 28, 2018 at 08:31:33PM +0530, Meenakshi Aggarwal wrote: > Provide Functions to initialize peripherals, > print board and soc information. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Vabhav > Signed-off-by: Meenakshi Aggarwal > --- > Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 1 + > Silicon/NXP/LS1046A/Include/SocSerDes.h | 55 ++++++++++++++++++++++ > Silicon/NXP/LS1046A/LS1046A.dec | 22 +++++++++ > Silicon/NXP/LS1046A/LS1046A.dsc.inc | 68 ++++++++++++++++++++++++++++ > Silicon/NXP/Library/SocLib/Chassis.c | 1 + > Silicon/NXP/Library/SocLib/Chassis.h | 1 + > Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 48 ++++++++++++++++++++ > Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 2 + > Silicon/NXP/Library/SocLib/LS1046aSocLib.inf | 53 ++++++++++++++++++++++ > Silicon/NXP/NxpQoriqLs.dec | 1 + > 10 files changed, 252 insertions(+) > create mode 100644 Silicon/NXP/LS1046A/Include/SocSerDes.h > create mode 100644 Silicon/NXP/LS1046A/LS1046A.dec > create mode 100644 Silicon/NXP/LS1046A/LS1046A.dsc.inc > create mode 100644 Silicon/NXP/Library/SocLib/LS1046aSocLib.inf > > diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc > index 9a68cfd..b69ffa2 100644 > --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc > +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc > @@ -59,6 +59,7 @@ > gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500 > gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE > gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1 > + gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3|TRUE > > # > # RTC Pcds > diff --git a/Silicon/NXP/LS1046A/Include/SocSerDes.h b/Silicon/NXP/LS1046A/Include/SocSerDes.h > new file mode 100644 > index 0000000..957db0f > --- /dev/null > +++ b/Silicon/NXP/LS1046A/Include/SocSerDes.h > @@ -0,0 +1,55 @@ > +/** @file > + The Header file of SerDes Module > + > + Copyright 2017 NXP > + > + This program and the accompanying materials > + are licensed and made available under the terms and conditions of the BSD License > + which accompanies this distribution. The full text of the license may be found > + http://opensource.org/licenses/bsd-license.php > + > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > + > +**/ > + > +#ifndef __LS1046A_SERDES_H__ > +#define __LS1046A_SERDES_H__ > + > +#include > + > +SERDES_CONFIG SerDes1ConfigTbl[] = { Whoops. I didn't pick up on this last time: https://edk2-docs.gitbooks.io/edk-ii-c-coding-standards-specification/content/5_source_files/53_include_files.html#537-include-files-shall-not-generate-code-or-define-data-variables Can you move this to a .c file? I guess this and SerDes2ConfigTbl could both be marked STATIC? > + /* SerDes 1 */ > + {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } }, > + {0x1133, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } }, > + {0x1333, {XFI_FM1_MAC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } }, > + {0x2333, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } }, > + {0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } }, > + {0x1040, {XFI_FM1_MAC9, NONE, QSGMII_FM1_A, NONE } }, > + {0x2040, {SGMII_2500_FM1_DTSEC9, NONE, QSGMII_FM1_A, NONE } }, > + {0x1163, {XFI_FM1_MAC9, XFI_FM1_MAC10, PCIE1, SGMII_FM1_DTSEC6 } }, > + {0x2263, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, PCIE1, SGMII_FM1_DTSEC6 } }, > + {0x3363, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, PCIE1, SGMII_FM1_DTSEC6 } }, > + {0x2223, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, SGMII_2500_FM1_DTSEC5, SGMII_FM1_DTSEC6 } }, > + {} > +}; > + > +SERDES_CONFIG SerDes2ConfigTbl[] = { > + /* SerDes 2 */ > + {0x8888, {PCIE1, PCIE1, PCIE1, PCIE1 } }, > + {0x5559, {PCIE1, PCIE2, PCIE3, SATA } }, > + {0x5577, {PCIE1, PCIE2, PCIE3, PCIE3 } }, > + {0x5506, {PCIE1, PCIE2, NONE, PCIE3 } }, > + {0x0506, {NONE, PCIE2, NONE, PCIE3 } }, > + {0x0559, {NONE, PCIE2, PCIE3, SATA } }, > + {0x5A59, {PCIE1, SGMII_FM1_DTSEC2, PCIE3, SATA } }, > + {0x5A06, {PCIE1, SGMII_FM1_DTSEC2, NONE, PCIE3 } }, > + {} > +}; > + > +SERDES_CONFIG *SerDesConfigTbl[] = { > + SerDes1ConfigTbl, > + SerDes2ConfigTbl > +}; > + > +#endif /* __LS1046A_SERDES_H */ > diff --git a/Silicon/NXP/LS1046A/LS1046A.dec b/Silicon/NXP/LS1046A/LS1046A.dec > new file mode 100644 > index 0000000..93fc80d > --- /dev/null > +++ b/Silicon/NXP/LS1046A/LS1046A.dec > @@ -0,0 +1,22 @@ > +# LS1046A.dec > +# > +# Copyright 2017 NXP > +# > +# This program and the accompanying materials are licensed and made available under > +# the terms and conditions of the BSD License which accompanies this distribution. > +# The full text of the license may be found at > +# http://opensource.org/licenses/bsd-license.php > +# > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +# > +# > + > +[Defines] > + DEC_SPECIFICATION = 0x0001000A 1A? (If that makes sense after changes.) / Leif > + > +[Guids.common] > + gNxpLs1046ATokenSpaceGuid = {0x8d7ffac8, 0xb4d5, 0x43c3, {0xaa, 0x27, 0x84, 0xbc, 0x12, 0x01, 0x28, 0x10}} > + > +[Includes] > + Include > diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc b/Silicon/NXP/LS1046A/LS1046A.dsc.inc > new file mode 100644 > index 0000000..9f87028 > --- /dev/null > +++ b/Silicon/NXP/LS1046A/LS1046A.dsc.inc > @@ -0,0 +1,68 @@ > +# LS1046A.dsc > +# LS1046A Soc package. > +# > +# Copyright 2017 NXP > +# > +# This program and the accompanying materials > +# are licensed and made available under the terms and conditions of the BSD License > +# which accompanies this distribution. The full text of the license may be found at > +# http://opensource.org/licenses/bsd-license.php > +# > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +# > +# > + > +################################################################################ > +# > +# Pcd Section - list of all EDK II PCD Entries defined by this Platform > +# > +################################################################################ > +[PcdsDynamicDefault.common] > + > + # > + # ARM General Interrupt Controller > + gArmTokenSpaceGuid.PcdGicDistributorBase|0x01410000 > + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x01420000 > + > +[PcdsFixedAtBuild.common] > + > + # > + # CCSR Address Space and other attached Memories > + # > + gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000 > + gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000 > + gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x01EE1000 > + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x60000000 > + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x20000000 > + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0620000000 > + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x00E0000000 > + gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x2EA > + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000 > + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000 > + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000 > + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0080000000 > + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x4000000000 > + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x800000000 > + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x4800000000 > + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x800000000 > + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x5000000000 > + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x800000000 > + gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr|0x0080000000 > + gNxpQoriqLsTokenSpaceGuid.PcdDram1Size|0x0080000000 > + gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr|0x0880000000 > + gNxpQoriqLsTokenSpaceGuid.PcdDram2Size|0x0780000000 > + gNxpQoriqLsTokenSpaceGuid.PcdDram3BaseAddr|0x8800000000 > + gNxpQoriqLsTokenSpaceGuid.PcdDram3Size|0x7800000000 > + gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x1570000 > + gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x01EE0000 > + gNxpQoriqLsTokenSpaceGuid.PcdWdog1BaseAddr|0x02AD0000 > + gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x01560000 > + gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02180000 > + gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000 > + gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4 > + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000 > + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000 > + gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x1530000 > + > +## > diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c > index 851174c..e8e69a6 100644 > --- a/Silicon/NXP/Library/SocLib/Chassis.c > +++ b/Silicon/NXP/Library/SocLib/Chassis.c > @@ -45,6 +45,7 @@ GurRead ( > */ > STATIC CPU_TYPE CpuTypeList[] = { > CPU_TYPE_ENTRY (LS1043A, LS1043A, 4), > + CPU_TYPE_ENTRY (LS1046A, LS1046A, 4), > }; > > /* > diff --git a/Silicon/NXP/Library/SocLib/Chassis.h b/Silicon/NXP/Library/SocLib/Chassis.h > index 5aa1209..5b7e5c4 100644 > --- a/Silicon/NXP/Library/SocLib/Chassis.h > +++ b/Silicon/NXP/Library/SocLib/Chassis.h > @@ -56,6 +56,7 @@ CpuMaskNext ( > > #define SVR_WO_E 0xFFFFFE > #define SVR_LS1043A 0x879200 > +#define SVR_LS1046A 0x870700 > > #define SVR_MAJOR(svr) (((svr) >> 4) & 0xf) > #define SVR_MINOR(svr) (((svr) >> 0) & 0xf) > diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c > index e79728e..62d761e 100644 > --- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c > +++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c > @@ -20,6 +20,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -138,6 +139,43 @@ GetSysInfo ( > } > > /** > + Function to select pins depending upon pcd using supplemental > + configuration unit(SCFG) extended RCW controlled pinmux control > + register which contains the bits to provide pin multiplexing control. > + This register is reset on HRESET. > + **/ > +VOID > +ConfigScfgMux (VOID) > +{ > + CCSR_SCFG *Scfg; > + UINT32 UsbPwrFault; > + > + Scfg = (VOID *)PcdGet64 (PcdScfgBaseAddr); > + // Configures functionality of the IIC3_SCL to USB2_DRVVBUS > + // Configures functionality of the IIC3_SDA to USB2_PWRFAULT > + > + // LS1043A > + // Configures functionality of the IIC4_SCL to USB3_DRVVBUS > + // Configures functionality of the IIC4_SDA to USB3_PWRFAULT > + > + // LS1046A > + // USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA > + if (PcdGetBool (PcdMuxToUsb3)) { > + SwapMmioWrite32 ((UINTN)&Scfg->RcwPMuxCr0, CCSR_SCFG_RCWPMUXCRO_SELCR_USB); > + } else { > + SwapMmioWrite32 ((UINTN)&Scfg->RcwPMuxCr0, CCSR_SCFG_RCWPMUXCRO_NOT_SELCR_USB); > + } > + > + SwapMmioWrite32 ((UINTN)&Scfg->UsbDrvVBusSelCr, CCSR_SCFG_USBDRVVBUS_SELCR_USB1); > + UsbPwrFault = > + (CCSR_SCFG_USBPWRFAULT_DEDICATED << CCSR_SCFG_USBPWRFAULT_USB3_SHIFT) | > + (CCSR_SCFG_USBPWRFAULT_DEDICATED << CCSR_SCFG_USBPWRFAULT_USB2_SHIFT) | > + (CCSR_SCFG_USBPWRFAULT_SHARED << CCSR_SCFG_USBPWRFAULT_USB1_SHIFT); > + > + SwapMmioWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault); > +} > + > +/** > Function to initialize SoC specific constructs > CPU Info > SoC Personality > @@ -167,6 +205,16 @@ SocInit ( > PrintSoc (); > IfcInit (); > PrintBoardPersonality (); > + // > + // Due to the extensive functionality present on the chip and the limited number of external > + // signals available, several functional blocks share signal resources through multiplexing. > + // In this case when there is alternate functionality between multiple functional blocks, > + // the signal's function is determined at the chip level (rather than at the block level) > + // typically by a reset configuration word (RCW) option. Some of the signals' function are > + // determined externel to RCW at Power-on Reset Sequence. > + // > + ConfigScfgMux (); > + > > return; > } > diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf > index af0790f..d93d66a 100644 > --- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf > +++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf > @@ -47,5 +47,7 @@ > gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr > gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian > gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr > + gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3 > gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv > + gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr > gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled > diff --git a/Silicon/NXP/Library/SocLib/LS1046aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1046aSocLib.inf > new file mode 100644 > index 0000000..7eb0180 > --- /dev/null > +++ b/Silicon/NXP/Library/SocLib/LS1046aSocLib.inf > @@ -0,0 +1,53 @@ > +# @file > +# > +# Copyright 2017 NXP > +# > +# This program and the accompanying materials > +# are licensed and made available under the terms and conditions of the BSD License > +# which accompanies this distribution. The full text of the license may be found at > +# http://opensource.org/licenses/bsd-license.php > +# > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +# > +# > + > +[Defines] > + INF_VERSION = 0x0001001A > + BASE_NAME = SocLib > + FILE_GUID = ddd5f950-8816-4d38-8f98-f42b07333f78 > + MODULE_TYPE = BASE > + VERSION_STRING = 1.0 > + LIBRARY_CLASS = SocLib > + > +[Packages] > + MdeModulePkg/MdeModulePkg.dec > + MdePkg/MdePkg.dec > + Silicon/NXP/NxpQoriqLs.dec > + Silicon/NXP/LS1046A/LS1046A.dec > + > +[LibraryClasses] > + BaseLib > + DebugLib > + FpgaLib > + IfcLib > + IoAccessLib > + SerialPortLib > + > +[Sources.common] > + Chassis.c > + Chassis2/Soc.c > + SerDes.c > + > +[BuildOptions] > + GCC:*_*_*_CC_FLAGS = -DCHASSIS2 > + > +[FixedPcd] > + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString > + gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr > + gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian > + gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr > + gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3 > + gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv > + gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr > + gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled > diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec > index bd89da4..159ea65 100644 > --- a/Silicon/NXP/NxpQoriqLs.dec > +++ b/Silicon/NXP/NxpQoriqLs.dec > @@ -101,6 +101,7 @@ > # > gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x0|UINT32|0x00000250 > gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE|BOOLEAN|0x00000251 > + gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3|FALSE|BOOLEAN|0x00000252 > > # > # Clock PCDs > -- > 1.9.1 >