From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::444; helo=mail-wr1-x444.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6A56C21197378 for ; Wed, 19 Dec 2018 11:08:57 -0800 (PST) Received: by mail-wr1-x444.google.com with SMTP id z5so20614819wrt.11 for ; Wed, 19 Dec 2018 11:08:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=/RTBbB1Tn46FScjAfaUmVi/kxC2e54XXLAyzRjo/kjE=; b=IYJIbzj4la5OWqbkDPrphuN1t9RllNk0yUil4Y6kYe8qM1uGmM/N9zv5oXyIq5509V Ps+wMaxsVUobX818GelzGverNqoLlx8CFGPEkGonrAf4JWvpAUqpqC/XA6T5TfrFDXiL 3L90odcF4GajXmmV714U/kc2dP3s7GsGmnumY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=/RTBbB1Tn46FScjAfaUmVi/kxC2e54XXLAyzRjo/kjE=; b=RLP1exwMvA/WBYXEv2/QrZMkjAqpmQTTNg1kNQjyPzjhtafHmn4swaq6wXHgEma+/8 NGDfHCh+rtPjyyVyJL4Kz/G9RqFc3EkOO0hpYoim6818uyDHsD0sFKyGDaUxFKCNeoW6 UEM06t9VGhFXfZ3qGQuDQHx8knP3zxT0Mlyrgw8Cb5RRENMb+talvstY9fU+CMdbmBjY H2ADbSQKkyLyeEYs1I+nbgErJvoyOD8lYIso44Q20oUyMfAABjoPnTk/9QUqoF432YZs 2D8GNfHR96APsVJtZN7Mvl8/m1Y9nK8sw1EYZ/YRAFw6GNNw4CrIPTTsaJsfELX0iKDG UKfg== X-Gm-Message-State: AA+aEWY2pmy5zVrmjebByk2eKGFhNEo0g0rj3cdpXGC2gfZnFmMDJSvV grlH7Ahglqxv5zXA4W4RGDUQZg== X-Google-Smtp-Source: AFSGD/Ve2H+VZU7LbN5Gk7+mLKQ6WHnfP4qFl16n+yjcz+Owjj6BLJUZO+nSrjZM1bHpAXoTxnM6tw== X-Received: by 2002:adf:9ec8:: with SMTP id b8mr8214888wrf.164.1545246536267; Wed, 19 Dec 2018 11:08:56 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id z14sm4918497wrm.48.2018.12.19.11.08.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 19 Dec 2018 11:08:55 -0800 (PST) Date: Wed, 19 Dec 2018 19:08:54 +0000 From: Leif Lindholm To: Meenakshi Aggarwal Cc: ard.biesheuvel@linaro.org, michael.d.kinney@intel.com, edk2-devel@lists.01.org, udit.kumar@nxp.com, v.sethi@nxp.com, Vabhav Message-ID: <20181219190854.lsgis554n4pplwoo@bivouac.eciton.net> References: <1518771035-6733-1-git-send-email-meenakshi.aggarwal@nxp.com> <1543417315-5763-1-git-send-email-meenakshi.aggarwal@nxp.com> <1543417315-5763-23-git-send-email-meenakshi.aggarwal@nxp.com> MIME-Version: 1.0 In-Reply-To: <1543417315-5763-23-git-send-email-meenakshi.aggarwal@nxp.com> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms 22/41] Platform/NXP: Add ArmPlatformLib for LS1046A X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 19 Dec 2018 19:08:59 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Nov 28, 2018 at 08:31:36PM +0530, Meenakshi Aggarwal wrote: > From: Vabhav > > Adding support of ArmPlatformLib for NXP LS1046ARDB board > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Vabhav > Reviewed-by: Leif Lindholm > --- > .../Library/PlatformLib/ArmPlatformLib.c | 105 ++++++++++++++ > .../Library/PlatformLib/ArmPlatformLib.inf | 66 +++++++++ > .../Library/PlatformLib/NxpQoriqLsHelper.S | 35 +++++ > .../Library/PlatformLib/NxpQoriqLsMem.c | 152 +++++++++++++++++++++ > 4 files changed, 358 insertions(+) > create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c > create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf > create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S > create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c > > diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c > new file mode 100644 > index 0000000..c59a06a > --- /dev/null > +++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c > @@ -0,0 +1,105 @@ > +/** ArmPlatformLib.c > +* > +* Contains board initialization functions. > +* > +* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoard.c > +* > +* Copyright (c) 2011-2012, ARM Limited. All rights reserved. > +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. > +* Copyright 2017 NXP > +* > +* This program and the accompanying materials > +* are licensed and made available under the terms and conditions of the BSD License > +* which accompanies this distribution. The full text of the license may be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +* > +**/ > + > +#include > +#include > + > +extern VOID SocInit (VOID); Please import this through an include file. > + > +/** > + Return the current Boot Mode > + > + This function returns the boot reason on the platform > + > +**/ > +EFI_BOOT_MODE > +ArmPlatformGetBootMode ( > + VOID > + ) > +{ > + return BOOT_WITH_FULL_CONFIGURATION; > +} > + > +/** > + Placeholder for Platform Initialization > +**/ > +EFI_STATUS > +ArmPlatformInitialize ( > + IN UINTN MpId > + ) > +{ > + SocInit (); > + > + return EFI_SUCCESS; > +} > + > +ARM_CORE_INFO LS1046aMpCoreInfoCTA72x4[] = { STATIC? m-prefix. > + { > + // Cluster 0, Core 0 > + 0x0, 0x0, > + > + // MP Core MailBox Set/Get/Clear Addresses and Clear Value > + (EFI_PHYSICAL_ADDRESS)0, > + (EFI_PHYSICAL_ADDRESS)0, > + (EFI_PHYSICAL_ADDRESS)0, > + (UINT64)0xFFFFFFFF > + }, > +}; Move global variables before function definitions start: https://edk2-docs.gitbooks.io/edk-ii-c-coding-standards-specification/content/5_source_files/54_code_file_structure.html > + > +EFI_STATUS > +PrePeiCoreGetMpCoreInfo ( > + OUT UINTN *CoreCount, > + OUT ARM_CORE_INFO **ArmCoreTable > + ) > +{ > + *CoreCount = sizeof (LS1046aMpCoreInfoCTA72x4) / sizeof (ARM_CORE_INFO); > + *ArmCoreTable = LS1046aMpCoreInfoCTA72x4; > + > + return EFI_SUCCESS; > +} > + > +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo }; STATIC? Before function definitions. > + > +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = { STATIC? m-prefix? Before function definitions? / Leif > + { > + EFI_PEI_PPI_DESCRIPTOR_PPI, > + &gArmMpCoreInfoPpiGuid, > + &mMpCoreInfoPpi > + } > +}; > + > +VOID > +ArmPlatformGetPlatformPpiList ( > + OUT UINTN *PpiListSize, > + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList > + ) > +{ > + *PpiListSize = sizeof (gPlatformPpiTable); > + *PpiList = gPlatformPpiTable; > +} > + > + > +UINTN > +ArmPlatformGetCorePosition ( > + IN UINTN MpId > + ) > +{ > + return 1; > +} > diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf > new file mode 100644 > index 0000000..49b57fc > --- /dev/null > +++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf > @@ -0,0 +1,66 @@ > +# @file > +# > +# Copyright 2017 NXP > +# > +# This program and the accompanying materials > +# are licensed and made available under the terms and conditions of the BSD License > +# which accompanies this distribution. The full text of the license may be found at > +# http://opensource.org/licenses/bsd-license.php > +# > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +# > + > +[Defines] > + INF_VERSION = 0x0001001A > + BASE_NAME = PlatformLib > + FILE_GUID = 05a9029b-266f-421d-bb46-0e8385c64aa0 > + MODULE_TYPE = BASE > + VERSION_STRING = 1.0 > + LIBRARY_CLASS = ArmPlatformLib > + > +[Packages] > + ArmPkg/ArmPkg.dec > + ArmPlatformPkg/ArmPlatformPkg.dec > + EmbeddedPkg/EmbeddedPkg.dec > + MdePkg/MdePkg.dec > + Silicon/NXP/NxpQoriqLs.dec > + > +[LibraryClasses] > + ArmLib > + SocLib > + > +[Sources.common] > + NxpQoriqLsHelper.S | GCC > + NxpQoriqLsMem.c > + ArmPlatformLib.c > + > +[Ppis] > + gArmMpCoreInfoPpiGuid > + > +[FixedPcd] > + gArmTokenSpaceGuid.PcdArmPrimaryCore > + gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr > + gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize > + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr > + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size > + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr > + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size > + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr > + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize > + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr > + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize > + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr > + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize > + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr > + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize > + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr > + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize > + gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr > + gNxpQoriqLsTokenSpaceGuid.PcdDram1Size > + gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr > + gNxpQoriqLsTokenSpaceGuid.PcdDram2Size > + gNxpQoriqLsTokenSpaceGuid.PcdDram3BaseAddr > + gNxpQoriqLsTokenSpaceGuid.PcdDram3Size > + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr > + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize > diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S > new file mode 100644 > index 0000000..6d54091 > --- /dev/null > +++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S > @@ -0,0 +1,35 @@ > +# @file > +# > +# Copyright (c) 2012-2013, ARM Limited. All rights reserved. > +# Copyright 2017 NXP > +# > +# This program and the accompanying materials > +# are licensed and made available under the terms and conditions of the BSD License > +# which accompanies this distribution. The full text of the license may be found at > +# http://opensource.org/licenses/bsd-license.php > +# > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +# > +# > + > +#include > +#include > + > +.text > +.align 2 > + > +GCC_ASM_IMPORT(ArmReadMpidr) > + > +ASM_FUNC(ArmPlatformIsPrimaryCore) > + tst x0, #3 > + cset x0, eq > + ret > + > +ASM_FUNC(ArmPlatformPeiBootAction) > + ret > + > +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId) > + MOV32 (x0, FixedPcdGet32(PcdArmPrimaryCore)) > + ldrh w0, [x0] > + ret > diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c > new file mode 100644 > index 0000000..64c5612 > --- /dev/null > +++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c > @@ -0,0 +1,152 @@ > +/** NxpQoriqLsMem.c > +* > +* Board memory specific Library. > +* > +* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c > +* > +* Copyright (c) 2011, ARM Limited. All rights reserved. > +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. > +* Copyright 2017 NXP > +* > +* This program and the accompanying materials > +* are licensed and made available under the terms and conditions of the BSD License > +* which accompanies this distribution. The full text of the license may be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +* > +**/ > + > +#include > +#include > +#include > +#include > + > +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25 > + > +/** > + Return the Virtual Memory Map of your platform > + > + This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform. > + > + @param VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to- > + Virtual Memory mapping. This array must be ended by a zero-filled > + entry > + > +**/ > + > +VOID > +ArmPlatformGetVirtualMemoryMap ( > + IN ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap > + ) > +{ > + UINTN Index; > + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; > + > + Index = 0; > + > + ASSERT (VirtualMemoryMap != NULL); > + > + VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages ( > + EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS)); > + > + if (VirtualMemoryTable == NULL) { > + return; > + } > + > + // DRAM1 (Must be 1st entry) > + VirtualMemoryTable[Index].PhysicalBase = FixedPcdGet64 (PcdDram1BaseAddr); > + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDram1BaseAddr); > + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDram1Size); > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK; > + > + // CCSR Space > + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdCcsrBaseAddr); > + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdCcsrBaseAddr); > + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize); > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > + > + // IFC region 1 > + // > + // A-009241 : Unaligned write transactions to IFC may result in corruption of data > + // Affects : IFC > + // Description: 16 byte unaligned write from system bus to IFC may result in extra unintended > + // writes on external IFC interface that can corrupt data on external flash. > + // Impact : Data corruption on external flash may happen in case of unaligned writes to > + // IFC memory space. > + // Workaround: Following are the workarounds: > + // For write transactions from core, IFC interface memories (including IFC SRAM) > + // should be configured as device type memory in MMU. > + // For write transactions from non-core masters (like system DMA), the address > + // should be 16 byte aligned and the data size should be multiple of 16 bytes. > + // > + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr); > + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr); > + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion1Size); > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > + > + // QMAN SWP > + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQmanSwpBaseAddr); > + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQmanSwpBaseAddr); > + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQmanSwpSize); > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED; > + > + // BMAN SWP > + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdBmanSwpBaseAddr); > + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdBmanSwpBaseAddr); > + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdBmanSwpSize); > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED; > + > + // IFC region 2 > + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr); > + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr); > + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion2Size); > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > + > + // DRAM2 > + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDram2BaseAddr); > + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDram2BaseAddr); > + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDram2Size); > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK; > + > + // PCIe1 > + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp1BaseAddr); > + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp1BaseAddr); > + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp1BaseSize); > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > + > + // PCIe2 > + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp2BaseAddr); > + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp2BaseAddr); > + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp2BaseSize); > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > + > + // PCIe3 > + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp3BaseAddr); > + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp3BaseAddr); > + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp3BaseSize); > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > + > + // DRAM3 > + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDram3BaseAddr); > + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDram3BaseAddr); > + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDram3Size); > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK; > + > + // QSPI region > + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQspiRegionBaseAddr); > + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQspiRegionBaseAddr); > + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQspiRegionSize); > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED; > + > + // End of Table > + VirtualMemoryTable[++Index].PhysicalBase = 0; > + VirtualMemoryTable[Index].VirtualBase = 0; > + VirtualMemoryTable[Index].Length = 0; > + VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0; > + > + ASSERT ((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); > + > + *VirtualMemoryMap = VirtualMemoryTable; > +} > -- > 1.9.1 >