From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.151; helo=mga17.intel.com; envelope-from=hao.a.wu@intel.com; receiver=edk2-devel@lists.01.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8E444211A2DAC for ; Thu, 20 Dec 2018 19:11:13 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Dec 2018 19:11:13 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,379,1539673200"; d="scan'208";a="102333232" Received: from shwdeopenpsi014.ccr.corp.intel.com ([10.239.9.9]) by orsmga006.jf.intel.com with ESMTP; 20 Dec 2018 19:11:11 -0800 From: Hao Wu To: edk2-devel@lists.01.org Cc: Hao Wu , Ard Biesheuvel , Leif Lindholm , Liming Gao , Michael D Kinney , Jiewen Yao , Laszlo Ersek Date: Fri, 21 Dec 2018 11:11:02 +0800 Message-Id: <20181221031106.12960-2-hao.a.wu@intel.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20181221031106.12960-1-hao.a.wu@intel.com> References: <20181221031106.12960-1-hao.a.wu@intel.com> Subject: [PATCH v1 1/5] MdePkg/BaseLib: Introduce new SpeculationBarrier API X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 21 Dec 2018 03:11:13 -0000 REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1417 X86 specific BaseLib API AsmLfence() was introduced to address the Spectre Variant 1 (CVE-2017-5753) issue. The purpose of this API is to insert barriers to stop speculative execution. However, the API is highly architecture (X86) specific, and thus should be avoided using across generic code. To address this issue, this patch will add a new BaseLib API called SpeculationBarrier(). Different architectures will have different implementations for this API. For IA32 and x64, the implementation of SpeculationBarrier() will directly call AsmLfence(). For ARM and AARCH64, this patch will add a temporary empty implementation as a placeholder. We hope experts in ARM can help to contribute the actual implementation. For EBC, similar to the ARM and AARCH64 cases, a temporary empty implementation is added. Cc: Ard Biesheuvel Cc: Leif Lindholm Cc: Liming Gao Cc: Michael D Kinney Cc: Jiewen Yao Cc: Laszlo Ersek Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu --- MdePkg/Library/BaseLib/BaseLib.inf | 5 +++ MdePkg/Include/Library/BaseLib.h | 15 +++++++++ MdePkg/Library/BaseLib/Arm/SpeculationBarrier.c | 30 ++++++++++++++++++ MdePkg/Library/BaseLib/Ebc/SpeculationBarrier.c | 30 ++++++++++++++++++ MdePkg/Library/BaseLib/X86SpeculationBarrier.c | 32 ++++++++++++++++++++ 5 files changed, 112 insertions(+) diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf index b84e58324c..d195c5417b 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -336,6 +336,7 @@ X86DisablePaging32.c X86RdRand.c X86PatchInstruction.c + X86SpeculationBarrier.c [Sources.X64] X64/Thunk16.nasm @@ -515,6 +516,7 @@ X86DisablePaging32.c X86RdRand.c X86PatchInstruction.c + X86SpeculationBarrier.c X64/GccInline.c | GCC X64/Thunk16.S | XCODE X64/SwitchStack.nasm| GCC @@ -543,12 +545,14 @@ Ebc/CpuBreakpoint.c Ebc/SetJumpLongJump.c Ebc/SwitchStack.c + Ebc/SpeculationBarrier.c Unaligned.c Math64.c [Sources.ARM] Arm/InternalSwitchStack.c Arm/Unaligned.c + Arm/SpeculationBarrier.c Math64.c | RVCT Math64.c | MSFT @@ -582,6 +586,7 @@ [Sources.AARCH64] Arm/InternalSwitchStack.c Arm/Unaligned.c + Arm/SpeculationBarrier.c Math64.c AArch64/MemoryFence.S | GCC diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h index 8cc086983d..1eb842384e 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -5111,6 +5111,21 @@ CpuDeadLoop ( VOID ); + +/** + Uses as a barrier to stop speculative execution. + + Ensures that no later instruction will execute speculatively, until all prior + instructions have completed. + +**/ +VOID +EFIAPI +SpeculationBarrier ( + VOID + ); + + #if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64) /// /// IA32 and x64 Specific Functions. diff --git a/MdePkg/Library/BaseLib/Arm/SpeculationBarrier.c b/MdePkg/Library/BaseLib/Arm/SpeculationBarrier.c new file mode 100644 index 0000000000..8a6165a102 --- /dev/null +++ b/MdePkg/Library/BaseLib/Arm/SpeculationBarrier.c @@ -0,0 +1,30 @@ +/** @file + SpeculationBarrier() function for ARM. + + Copyright (C) 2018, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + +/** + Uses as a barrier to stop speculative execution. + + Ensures that no later instruction will execute speculatively, until all prior + instructions have completed. + +**/ +VOID +EFIAPI +SpeculationBarrier ( + VOID + ) +{ +} diff --git a/MdePkg/Library/BaseLib/Ebc/SpeculationBarrier.c b/MdePkg/Library/BaseLib/Ebc/SpeculationBarrier.c new file mode 100644 index 0000000000..8fa4c204f8 --- /dev/null +++ b/MdePkg/Library/BaseLib/Ebc/SpeculationBarrier.c @@ -0,0 +1,30 @@ +/** @file + SpeculationBarrier() function for EBC. + + Copyright (C) 2018, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + +/** + Uses as a barrier to stop speculative execution. + + Ensures that no later instruction will execute speculatively, until all prior + instructions have completed. + +**/ +VOID +EFIAPI +SpeculationBarrier ( + VOID + ) +{ +} diff --git a/MdePkg/Library/BaseLib/X86SpeculationBarrier.c b/MdePkg/Library/BaseLib/X86SpeculationBarrier.c new file mode 100644 index 0000000000..03deca8489 --- /dev/null +++ b/MdePkg/Library/BaseLib/X86SpeculationBarrier.c @@ -0,0 +1,32 @@ +/** @file + SpeculationBarrier() function for IA32 and x64. + + Copyright (C) 2018, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include + +/** + Uses as a barrier to stop speculative execution. + + Ensures that no later instruction will execute speculatively, until all prior + instructions have completed. + +**/ +VOID +EFIAPI +SpeculationBarrier ( + VOID + ) +{ + AsmLfence (); +} -- 2.12.0.windows.1