From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::444; helo=mail-wr1-x444.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E9743211A2084 for ; Fri, 21 Dec 2018 07:08:54 -0800 (PST) Received: by mail-wr1-x444.google.com with SMTP id t6so5592550wrr.12 for ; Fri, 21 Dec 2018 07:08:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=b6ToDA7QaChxwK5SXSo2WghytjzYZEc4RNMHTEswGWg=; b=Y/REFfc+lnidaSCHo8tnDH+ZvvkHwSZMG39zLSRNKTmhYh7MN7ZC7+EsY8qmOJqOYu unY8tueP7V33IyOBDuX2u++o0/XM//IkpH2HgnfU5bG48Pz4WrzBFdPWMz5zPYuUykmF Kv+DzLzS+ZHVblbCvhSt+UKYGciUuMkFN7DBo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=b6ToDA7QaChxwK5SXSo2WghytjzYZEc4RNMHTEswGWg=; b=KSoRnpzT/n+fmXqKY3unJJzlFN/tZwNKe3NEdYNe1CXAMfIuNq8UR8xNplkrJnjeXx B7Iuetqqeq4jbE+UgpB9vn1qZeplgGYh/WJaYHU6Ui4D/sXYB1o3SICE9iRUyUyV+Hpu e9vYO3zNsCMhChH+h+estLKevG6uCPVwzKmAMD5ltCrsQsosGNTbktBpYDPT/M6k6iD0 ta0EH+aiGITRzznrv213e4a36b/iTxqMKHzemsZ/5qv1R/MjfNNl9iq4K2Ickw6KiXnh cRRW/LGVYmdtgrtSR75qwB1Renq3u3zGIiL2okmqf1ZXuoY++1ru+f3nxv2E3XBq2mZS du1Q== X-Gm-Message-State: AJcUukdsfIa3/aY6jTwH++tNYlnCs4HTILFtGrtEWUx0vpXXc3rRzng6 tLqV/MOxi+uqxy/AmwgIC3IVKKHsEC+gtQ== X-Google-Smtp-Source: ALg8bN4A2wft4X8tJ4ZXQSS7RV7+qMzCph8zXNwljQFavabSfB1B81HTmqFo2lDPbGemaPH4Q7NGxg== X-Received: by 2002:adf:80a9:: with SMTP id 38mr2841727wrl.137.1545404932777; Fri, 21 Dec 2018 07:08:52 -0800 (PST) Received: from localhost.localdomain (laubervilliers-657-1-83-120.w92-154.abo.wanadoo.fr. [92.154.90.120]) by smtp.gmail.com with ESMTPSA id c7sm20315823wre.64.2018.12.21.07.08.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 21 Dec 2018 07:08:51 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Fri, 21 Dec 2018 16:08:48 +0100 Message-Id: <20181221150848.4783-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.19.2 MIME-Version: 1.0 Subject: [PATCH] ArmPkg/ArmGicV3Dxe: use correct value for ARM_GICD_IROUTER X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 21 Dec 2018 15:08:55 -0000 Content-Transfer-Encoding: 8bit Use the correct value for ARM_GICD_IROUTER as per the GIC spec, and fix the code that relies on the value being skewed by 32 x 8 bytes. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- ArmPkg/Include/Library/ArmGicLib.h | 2 +- ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/ArmPkg/Include/Library/ArmGicLib.h b/ArmPkg/Include/Library/ArmGicLib.h index 5775905ca91b..b52b77628ae1 100644 --- a/ArmPkg/Include/Library/ArmGicLib.h +++ b/ArmPkg/Include/Library/ArmGicLib.h @@ -43,7 +43,7 @@ #define ARM_GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register // GICv3 specific registers -#define ARM_GICD_IROUTER 0x6100 // Interrupt Routing Registers +#define ARM_GICD_IROUTER 0x6000 // Interrupt Routing Registers // GICD_CTLR bits #define ARM_GIC_ICDDCR_ARE (1 << 4) // Affinity Routing Enable (ARE) diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c index 1558db31713a..7d891873ba82 100644 --- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c +++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c @@ -466,7 +466,7 @@ GicV3DxeInitialize ( } // Route the SPIs to the primary CPU. SPIs start at the INTID 32 - for (Index = 0; Index < (mGicNumInterrupts - 32); Index++) { + for (Index = 32; Index < mGicNumInterrupts; Index++) { MmioWrite32 ( mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8), CpuTarget -- 2.19.2