From: Leif Lindholm <leif.lindholm@linaro.org>
To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Cc: ard.biesheuvel@linaro.org, michael.d.kinney@intel.com,
edk2-devel@lists.01.org, udit.kumar@nxp.com, v.sethi@nxp.com,
Vabhav <vabhav.sharma@nxp.com>
Subject: Re: [PATCH edk2-platforms 35/41] Silicon/NXP: Implement PciHostBridgeLib support
Date: Fri, 21 Dec 2018 18:30:57 +0000 [thread overview]
Message-ID: <20181221183057.owxl2hvu6zd6ecch@bivouac.eciton.net> (raw)
In-Reply-To: <1543417315-5763-36-git-send-email-meenakshi.aggarwal@nxp.com>
On Wed, Nov 28, 2018 at 08:31:49PM +0530, Meenakshi Aggarwal wrote:
> From: Vabhav <vabhav.sharma@nxp.com>
>
> Implement the library that exposes the PCIe root complexes to the
> generic PCI host bridge driver,Putting SoC Specific low level init
> code for the RCs.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
> ---
> .../Library/PciHostBridgeLib/PciHostBridgeLib.c | 639 +++++++++++++++++++++
> .../Library/PciHostBridgeLib/PciHostBridgeLib.inf | 51 ++
> 2 files changed, 690 insertions(+)
> create mode 100644 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
> create mode 100644 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
>
> diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
> new file mode 100644
> index 0000000..a543d7d
> --- /dev/null
> +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
> @@ -0,0 +1,639 @@
> +/** @file
> + PCI Host Bridge Library instance for NXP SoCs
> +
> + Copyright 2018 NXP
> +
> + This program and the accompanying materials are licensed and made available
> + under the terms and conditions of the BSD License which accompanies this
> + distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php.
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
> + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <PiDxe.h>
> +#include <IndustryStandard/Pci22.h>
> +#include <Library/DebugLib.h>
> +#include <Library/DevicePathLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/IoAccessLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/PciHostBridgeLib.h>
> +#include <NxpPcie.h>
> +#include <Protocol/PciHostBridgeResourceAllocation.h>
> +#include <Protocol/PciRootBridgeIo.h>
> +
> +#pragma pack(1)
> +typedef struct {
> + ACPI_HID_DEVICE_PATH AcpiDevicePath;
> + EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
> +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
> +#pragma pack ()
> +
> +STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = {
> + {
> + {
> + {
> + ACPI_DEVICE_PATH,
> + ACPI_DP,
> + {
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
> + }
> + },
> + EISA_PNP_ID (0x0A08), // PCI Express
> + PCI_SEG0_NUM
> + },
> +
> + {
> + END_DEVICE_PATH_TYPE,
> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
> + {
> + END_DEVICE_PATH_LENGTH,
> + 0
> + }
> + }
> + },
> + {
> + {
> + {
> + ACPI_DEVICE_PATH,
> + ACPI_DP,
> + {
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
> + }
> + },
> + EISA_PNP_ID (0x0A08), // PCI Express
> + PCI_SEG1_NUM
> + },
> +
> + {
> + END_DEVICE_PATH_TYPE,
> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
> + {
> + END_DEVICE_PATH_LENGTH,
> + 0
> + }
> + }
> + },
> + {
> + {
> + {
> + ACPI_DEVICE_PATH,
> + ACPI_DP,
> + {
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
> + }
> + },
> + EISA_PNP_ID (0x0A08), // PCI Express
> + PCI_SEG2_NUM
> + },
> +
> + {
> + END_DEVICE_PATH_TYPE,
> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
> + {
> + END_DEVICE_PATH_LENGTH,
> + 0
> + }
> + }
> + },
> + {
> + {
> + {
> + ACPI_DEVICE_PATH,
> + ACPI_DP,
> + {
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
> + }
> + },
> + EISA_PNP_ID (0x0A08), // PCI Express
> + PCI_SEG3_NUM
> + },
> +
> + {
> + END_DEVICE_PATH_TYPE,
> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
> + {
> + END_DEVICE_PATH_LENGTH,
> + 0
> + }
> + }
> + }
> +};
> +
> +STATIC
> +GLOBAL_REMOVE_IF_UNREFERENCED
> +CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
> + L"Mem", L"I/O", L"Bus"
> +};
> +
> +#define PCI_ALLOCATION_ATTRIBUTES EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | \
> + EFI_PCI_HOST_BRIDGE_MEM64_DECODE
> +
> +#define PCI_SUPPORT_ATTRIBUTES EFI_PCI_ATTRIBUTE_ISA_IO_16 | \
> + EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | \
> + EFI_PCI_ATTRIBUTE_VGA_MEMORY | \
> + EFI_PCI_ATTRIBUTE_VGA_IO_16 | \
> + EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16
> +
> +PCI_ROOT_BRIDGE mPciRootBridges[NUM_PCIE_CONTROLLER];
> +
> +/**
> + Function to set-up iATU outbound window for PCIe controller
> +
> + @param Dbi Address of PCIe host controller.
> + @param Idx Index of iATU outbound window.
> + @param Type Type(Cfg0/Cfg1/Mem/IO) of iATU outbound window.
> + @param Phys PCIe controller phy address for outbound window.
> + @param BusAdr PCIe controller bus address for outbound window.
> + @param Pcie Size of PCIe controller space(Cfg0/Cfg1/Mem/IO).
> +
> +**/
> +STATIC
> +VOID
> +PcieIatuOutboundSet (
> + IN EFI_PHYSICAL_ADDRESS Dbi,
> + IN UINT32 Idx,
> + IN UINT32 Type,
> + IN UINT64 Phys,
> + IN UINT64 BusAddr,
> + IN UINT64 Size
> + )
> +{
> + MmioWrite32 (Dbi + IATU_VIEWPORT_OFF,
> + (UINT32)(IATU_VIEWPORT_OUTBOUND | Idx));
Indentation in continuation should be one step further.
Please address below as well.
> + MmioWrite32 (Dbi + IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0,
> + (UINT32)Phys);
> + MmioWrite32 (Dbi + IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0,
> + (UINT32)(Phys >> 32));
> + MmioWrite32 (Dbi + IATU_LIMIT_ADDR_OFF_OUTBOUND_0,
> + (UINT32)(Phys + Size - BIT0));
What's with the BIT0 arithmetic?
> + MmioWrite32 (Dbi + IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0,
> + (UINT32)BusAddr);
> + MmioWrite32 (Dbi + IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0,
> + (UINT32)(BusAddr >> 32));
> + MmioWrite32 (Dbi + IATU_REGION_CTRL_1_OFF_OUTBOUND_0,
> + (UINT32)Type);
> + MmioWrite32 (Dbi + IATU_REGION_CTRL_2_OFF_OUTBOUND_0,
> + IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN);
> +}
> +
> +/**
> + Function to check PCIe controller LTSSM state
> +
> + @param Pcie Address of PCIe host controller.
> +
> +**/
> +STATIC
> +INTN
> +PcieLinkState (
> + IN EFI_PHYSICAL_ADDRESS Pcie
> + )
> +{
> + UINT32 State;
> +
> + //
> + // Reading PCIe controller LTSSM state
> + //
> + if (FeaturePcdGet (PcdPciLutBigEndian)) {
> + State = SwapMmioRead32 ((UINTN)Pcie + PCI_LUT_BASE + PCI_LUT_DBG) &
> + LTSSM_STATE_MASK;
> + } else {
> + State = MmioRead32 ((UINTN)Pcie + PCI_LUT_BASE + PCI_LUT_DBG) &
> + LTSSM_STATE_MASK;
> + }
> +
> + if (State < LTSSM_PCIE_L0) {
> + DEBUG ((DEBUG_INFO," Pcie Link error. LTSSM=0x%2x\n", State));
> + return EFI_SUCCESS;
> + }
> +
> + return EFI_UNSUPPORTED;
> +}
> +
> +/**
> + Helper function to check PCIe link state
> +
> + @param Pcie Address of PCIe host controller.
> +
> +**/
> +STATIC
> +INTN
> +PcieLinkUp (
> + IN EFI_PHYSICAL_ADDRESS Pcie
> + )
> +{
> + INTN State;
> + UINT32 Cap;
> +
> + State = PcieLinkState (Pcie);
> + if (State) {
> + return State;
> + }
> +
> + //
> + // Try to download speed to gen1
> + //
> + Cap = MmioRead32 ((UINTN)Pcie + PCI_LINK_CAP);
> + MmioWrite32 ((UINTN)Pcie + PCI_LINK_CAP, (UINT32)(Cap & (~PCI_LINK_SPEED_MASK)) | BIT0);
What does BIT0 signify here?
> + State = PcieLinkState (Pcie);
> + if (State) {
> + return State;
> + }
> +
> + MmioWrite32 ((UINTN)Pcie + PCI_LINK_CAP, Cap);
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + This function checks whether PCIe is enabled or not
> + depending upon SoC serdes protocol map
> +
> + @param PcieNum PCIe number.
> +
> + @return The PCIe number enabled in map.
> + @return FALSE PCIe number is disabled in map.
> +
> +**/
> +STATIC
> +BOOLEAN
> +IsPcieNumEnabled(
> + IN UINTN PcieNum
> + )
> +{
> + UINT64 SerDes1ProtocolMap;
> +
> + SerDes1ProtocolMap = 0x0;
> +
> + //
> + // Reading serdes map
> + //
> + GetSerdesProtocolMaps (&SerDes1ProtocolMap);
> +
> + //
> + // Verify serdes line is configured in the map
> + //
> + if (PcieNum < NUM_PCIE_CONTROLLER) {
> + return IsSerDesLaneProtocolConfigured (SerDes1ProtocolMap, (PcieNum + BIT0));
So, I'm getting the feeling a global search-and-replace on BIT0 may
have happened in this file/patch. Please have a look and see where the
numeral 1 is what was intended, where a #define with a descriptive
alias for BIT0 was intended, and where actually BIT0 was intended.
> + } else {
> + DEBUG ((DEBUG_ERROR, "Device not supported\n"));
> + }
> +
> + return FALSE;
> +}
> +
> +/**
> + Function to set-up iATU outbound window for PCIe controller
> +
> + @param Pcie Address of PCIe host controller
> + @param Cfg0Base PCIe controller phy address Type0 Configuration Space.
> + @param Cfg1Base PCIe controller phy address Type1 Configuration Space.
> + @param MemBase PCIe controller phy address in MMIO32 Memory Space.
> + @param Mem64Base PCIe controller phy address in MMIO64 Memory Space.
> + @param IoBase PCIe controller phy address IO Space.
> +**/
> +STATIC
> +VOID
> +PcieSetupAtu (
> + IN EFI_PHYSICAL_ADDRESS Pcie,
> + IN EFI_PHYSICAL_ADDRESS Cfg0Base,
> + IN EFI_PHYSICAL_ADDRESS Cfg1Base,
> + IN EFI_PHYSICAL_ADDRESS MemBase,
> + IN EFI_PHYSICAL_ADDRESS Mem64Base,
> + IN EFI_PHYSICAL_ADDRESS IoBase
> + )
> +{
> +
> + //
> + // iATU : OUTBOUND WINDOW 0 : CFG0
> + //
> + PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX0,
> + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0,
> + Cfg0Base,
> + SEG_CFG_BUS,
> + SEG_CFG_SIZE);
I'll just point out here that I'm nearly certain this indentation
pattern violates the coding style. But I kind of like it :)
> +
> + //
> + // iATU : OUTBOUND WINDOW 1 : CFG1
> + PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX1,
> + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1,
> + Cfg1Base,
> + SEG_CFG_BUS,
> + SEG_CFG_SIZE);
> + //
> + // iATU 2 : OUTBOUND WINDOW 2 : MMIO32
> + //
> + PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX2,
> + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM | BIT12,
> + MemBase,
> + SEG_MEM_BUS,
> + SEG_MEM_SIZE);
> +
> + //
> + // iATU 3 : OUTBOUND WINDOW 3: IO
> + //
> + PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX3,
> + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO,
> + IoBase,
> + SEG_IO_BUS,
> + SEG_IO_SIZE);
> + //
> + // iATU 4 : OUTBOUND WINDOW 4 : MMIO64
> + //
> + PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX4,
> + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM,
> + Mem64Base,
> + SEG_MEM64_BASE,
> + MEM64_LIMIT);
> +
> + if (FeaturePcdGet (PcdPciDebug) == TRUE) {
> + INTN Cnt;
Cnt -> Count;
> + UINTN AddrTemp;
> +
> + for (Cnt = 0; Cnt <= IATU_REGION_INDEX4; Cnt++) {
> + MmioWrite32 ((UINTN)Pcie + IATU_VIEWPORT_OFF,
> + (UINT32)(IATU_VIEWPORT_OUTBOUND | Cnt));
> + DEBUG ((DEBUG_INFO,"iATU%d:\n", Cnt));
> + AddrTemp = (UINTN)((UINTN)Pcie + IATU_VIEWPORT_OFF);
> + DEBUG ((DEBUG_INFO,"iATU%d VIEWPORT REG Addr:%08lx Val:%08lx\n",
> + Cnt, AddrTemp, MmioRead32 (AddrTemp)));
> + DEBUG ((DEBUG_INFO,"iATU%d VIEWPORT REG:%08lx\n",
> + Cnt, MmioRead32 ((UINTN)Pcie + IATU_VIEWPORT_OFF)));
> + DEBUG ((DEBUG_INFO,"\tLOWER PHYS 0x%08x\n",
> + MmioRead32 ((UINTN)Pcie + IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0)));
> + DEBUG ((DEBUG_INFO,"\tUPPER PHYS 0x%08x\n",
> + MmioRead32 ((UINTN)Pcie + IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0)));
> + DEBUG ((DEBUG_INFO,"\tLOWER BUS 0x%08x\n",
> + MmioRead32 ((UINTN)Pcie + IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0)));
> + DEBUG ((DEBUG_INFO,"\tUPPER BUS 0x%08x\n",
> + MmioRead32 ((UINTN)Pcie + IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0)));
> + DEBUG ((DEBUG_INFO,"\tLIMIT 0x%08x\n",
> + MmioRead32 ((UINTN)Pcie + IATU_LIMIT_ADDR_OFF_OUTBOUND_0)));
> + DEBUG ((DEBUG_INFO,"\tCR1 0x%08x\n",
> + MmioRead32 ((UINTN)Pcie + IATU_REGION_CTRL_1_OFF_OUTBOUND_0)));
> + DEBUG ((DEBUG_INFO,"\tCR2 0x%08x\n",
> + MmioRead32 ((UINTN)Pcie + IATU_REGION_CTRL_2_OFF_OUTBOUND_0)));
> + }
> + }
> +}
> +
> +/**
> + Helper function to set-up PCIe controller
> +
> + @param Pcie Address of PCIe host controller
> + @param Cfg0Base PCIe controller phy address Type0 Configuration Space.
> + @param Cfg1Base PCIe controller phy address Type1 Configuration Space.
> + @param MemBase PCIe controller phy address MMIO32 Memory Space.
> + @param Mem64Base PCIe controller phy address MMIO64 Memory Space.
> + @param IoBase PCIe controller phy address IO Space.
> +
> +**/
> +STATIC
> +VOID
> +PcieSetupCntrl (
> + IN EFI_PHYSICAL_ADDRESS Pcie,
> + IN EFI_PHYSICAL_ADDRESS Cfg0Base,
> + IN EFI_PHYSICAL_ADDRESS Cfg1Base,
> + IN EFI_PHYSICAL_ADDRESS MemBase,
> + IN EFI_PHYSICAL_ADDRESS Mem64Base,
> + IN EFI_PHYSICAL_ADDRESS IoBase
> + )
> +{
> + //
> + // iATU outbound set-up
> + //
> + PcieSetupAtu (Pcie, Cfg0Base, Cfg1Base, MemBase, Mem64Base, IoBase);
> +
> + //
> + // program correct class for RC
> + //
> + MmioWrite32 ((UINTN)Pcie + PCI_BASE_ADDRESS_0, (BIT0 - BIT0));
> + MmioWrite32 ((UINTN)Pcie + PCI_DBI_RO_WR_EN, (UINT32)BIT0);
> + MmioWrite32 ((UINTN)Pcie + PCI_CLASS_DEVICE, (UINT32)PCI_CLASS_BRIDGE_PCI);
> + MmioWrite32 ((UINTN)Pcie + PCI_DBI_RO_WR_EN, (UINT32)(BIT0 - BIT0));
> +}
> +
> +/**
> + Return all the root bridge instances in an array.
> +
> + @param Count Return the count of root bridge instances.
> +
> + @return All the root bridge instances in an array.
> +
> +**/
> +PCI_ROOT_BRIDGE *
> +EFIAPI
> +PciHostBridgeGetRootBridges (
> + OUT UINTN *Count
> + )
> +{
> + UINTN Idx;
Idx -> Index.
> + UINTN Loop;
> + INTN LinkUp;
> + UINT64 PciPhyMemAddr[NUM_PCIE_CONTROLLER];
> + UINT64 PciPhyMem64Addr[NUM_PCIE_CONTROLLER];
> + UINT64 PciPhyCfg0Addr[NUM_PCIE_CONTROLLER];
> + UINT64 PciPhyCfg1Addr[NUM_PCIE_CONTROLLER];
> + UINT64 PciPhyIoAddr[NUM_PCIE_CONTROLLER];
> + UINT64 Regs[NUM_PCIE_CONTROLLER];
> + UINT8 PciEnabled[NUM_PCIE_CONTROLLER];
> +
> + *Count = 0;
> +
> + //
> + // Filling local array for
> + // PCIe controller Physical address space for Cfg0,Cfg1,Mem,IO
> + // Host Contoller address
> + //
> + for (Idx = 0; Idx < NUM_PCIE_CONTROLLER; Idx++) {
> + PciPhyMemAddr[Idx] = PCI_SEG0_PHY_MEM_BASE + (PCI_BASE_DIFF * Idx);
> + PciPhyCfg0Addr[Idx] = PCI_SEG0_PHY_CFG0_BASE + (PCI_BASE_DIFF * Idx);
> + PciPhyCfg1Addr[Idx] = PCI_SEG0_PHY_CFG1_BASE + (PCI_BASE_DIFF * Idx);
> + PciPhyIoAddr [Idx] = PCI_SEG0_PHY_IO_BASE + (PCI_BASE_DIFF * Idx);
> + PciPhyMem64Addr[Idx] = PCI_SEG0_PHY_MEM64_BASE + (PCI_BASE_DIFF * Idx);
> + Regs[Idx] = PCI_SEG0_DBI_BASE + (PCI_DBI_SIZE_DIFF * Idx);
> + }
> +
> + if (FeaturePcdGet (PcdPciDebug) == TRUE) {
> + DEBUG ((DEBUG_INFO, "In PCIE_INFO: %d\n", Idx));
> + DEBUG ((DEBUG_INFO, "PciNum:%d Info PCIe Controller Address: %016llx\n",
> + Idx,
> + Regs[Idx]));
> + DEBUG ((DEBUG_INFO, "Info CFG Values: %016llx:%016llx\n",
> + (UINT64)PciPhyCfg0Addr[Idx],
> + (UINT64)PciPhyCfg1Addr[Idx]));
> + DEBUG ((DEBUG_INFO, "Info Mem Values: %016llx\n",
> + (UINT64)PciPhyMemAddr[Idx]));
> + DEBUG ((DEBUG_INFO, "Info IO Values: %016llx\n",
> + (UINT64)PciPhyIoAddr[Idx]));
> + DEBUG ((DEBUG_INFO, "Info Mem64 Values: %016llx\n",
> + (UINT64)PciPhyMem64Addr[Idx]));
> + }
> +
> + for (Idx = 0; Idx < NUM_PCIE_CONTROLLER; Idx++) {
> + //
> + // Verify PCIe controller is enabled in Soc Serdes Map
> + //
> + if (!IsPcieNumEnabled (Idx)) {
> + DEBUG ((DEBUG_ERROR, "PCIE%d is disabled\n", (Idx + BIT0)));
> + //
> + // Continue with other PCIe controller
> + //
> + continue;
> + }
> + DEBUG ((DEBUG_INFO, "PCIE%d is Enabled\n", Idx + BIT0));
> +
> + //
> + // Verify PCIe controller LTSSM state
> + //
> + LinkUp = PcieLinkUp(Regs[Idx]);
Space after (.
> + if (!LinkUp) {
> + //
> + // Let the user know there's no PCIe link
> + //
> + DEBUG ((DEBUG_INFO,"no link, regs @ 0x%lx\n", Regs[Idx]));
> + //
> + // Continue with other PCIe controller
> + //
> + continue;
> + }
> + DEBUG ((DEBUG_INFO, "PCIE%d Passed Linkup Phase\n", Idx + BIT0));
> +
> + //
> + // Function to set up address translation unit outbound window for
> + // PCIe Controller
> + //
> + PcieSetupCntrl (Regs[Idx],
> + PciPhyCfg0Addr[Idx],
> + PciPhyCfg1Addr[Idx],
> + PciPhyMemAddr[Idx],
> + PciPhyMem64Addr[Idx],
> + PciPhyIoAddr[Idx]);
> + //
> + // Local array to index all enable PCIe controllers
> + //
> + PciEnabled[*Count] = Idx;
> +
> + *Count += BIT0;
> + }
> +
> + if (*Count == 0) {
> + return NULL;
> + } else {
No need for the else, anything after the NULL return is just the rest
of the function, and can lose a level of indentation.
> + for (Loop = 0; Loop < *Count; Loop++) {
> + mPciRootBridges[Loop].Segment = PciEnabled[Loop];
> + mPciRootBridges[Loop].Supports = PCI_SUPPORT_ATTRIBUTES;
> + mPciRootBridges[Loop].Attributes = PCI_SUPPORT_ATTRIBUTES;
> + mPciRootBridges[Loop].DmaAbove4G = TRUE;
> + mPciRootBridges[Loop].NoExtendedConfigSpace = FALSE;
> + mPciRootBridges[Loop].ResourceAssigned = FALSE;
> + mPciRootBridges[Loop].AllocationAttributes = PCI_ALLOCATION_ATTRIBUTES;
> + mPciRootBridges[Loop].Bus.Base = PCI_SEG_BUSNUM_MIN;
> + mPciRootBridges[Loop].Bus.Limit = PCI_SEG_BUSNUM_MAX;
> + mPciRootBridges[Loop].Io.Base = PCI_SEG_PORTIO_MIN;
> + mPciRootBridges[Loop].Io.Limit = PCI_SEG_PORTIO_MAX;
> + mPciRootBridges[Loop].Io.Translation = MAX_UINT64 -
> + (PciEnabled[Loop] *
> + SEG_IO_SIZE) + 1;
> + mPciRootBridges[Loop].Mem.Base = PCI_SEG_MMIO32_MIN;
> + mPciRootBridges[Loop].Mem.Limit = PCI_SEG_MMIO32_MAX;
> + mPciRootBridges[Loop].Mem.Translation = MAX_UINT64 -
> + (PciEnabled[Loop] *
> + PCI_SEG_MMIO32_DIFF) + 1;
> + mPciRootBridges[Loop].MemAbove4G.Base = PciPhyMemAddr[PciEnabled[Loop]];
> + mPciRootBridges[Loop].MemAbove4G.Limit = PciPhyMemAddr[PciEnabled[Loop]] +
> + PCI_SEG_MMIO64_MAX_DIFF;
> + //
> + // No separate ranges for prefetchable and non-prefetchable BARs
> + //
> + mPciRootBridges[Loop].PMem.Base = MAX_UINT64;
> + mPciRootBridges[Loop].PMem.Limit = 0;
> + mPciRootBridges[Loop].PMemAbove4G.Base = MAX_UINT64;
> + mPciRootBridges[Loop].PMemAbove4G.Limit = 0;
> + mPciRootBridges[Loop].DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[PciEnabled[Loop]];
> + }
> +
> + return mPciRootBridges;
> + }
> +}
> +
> +/**
> + Free the root bridge instances array returned from PciHostBridgeGetRootBridges().
> +
> + @param Bridges The root bridge instances array.
> + @param Count The count of the array.
> +**/
> +VOID
> +EFIAPI
> +PciHostBridgeFreeRootBridges (
> + PCI_ROOT_BRIDGE *Bridges,
> + UINTN Count
> + )
> +{
A comment that/why nothing is needed here wouldn't go amiss.
/
Leif
> +}
> +
> +/**
> + Inform the platform that the resource conflict happens.
> +
> + @param HostBridgeHandle Handle of the Host Bridge.
> + @param Configuration Pointer to PCI I/O and PCI memory resource
> + descriptors. The Configuration contains the resources
> + for all the root bridges. The resource for each root
> + bridge is terminated with END descriptor and an
> + additional END is appended indicating the end of the
> + entire resources. The resource descriptor field
> + values follow the description in
> + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
> + .SubmitResources().
> +
> +**/
> +VOID
> +EFIAPI
> +PciHostBridgeResourceConflict (
> + EFI_HANDLE HostBridgeHandle,
> + VOID *Configuration
> + )
> +{
> + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
> + UINTN RootBridgeIndex;
> + DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n"));
> +
> + RootBridgeIndex = 0;
> + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
> + while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
> + DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));
> + for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
> + ASSERT (Descriptor->ResType <
> + ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr));
> + DEBUG ((DEBUG_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n",
> + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
> + Descriptor->AddrLen, Descriptor->AddrRangeMax
> + ));
> + if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
> + DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n",
> + Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,
> + ((Descriptor->SpecificFlag &
> + EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
> + ) != 0) ? L" (Prefetchable)" : L""
> + ));
> + }
> + }
> + //
> + // Skip the END descriptor for root bridge
> + //
> + ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
> + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(
> + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1
> + );
> + }
> +
> + return;
> +}
> diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> new file mode 100644
> index 0000000..4f1c4d2
> --- /dev/null
> +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> @@ -0,0 +1,51 @@
> +## @file
> +# PCI Host Bridge Library instance for NXP ARM SOC
> +#
> +# Copyright 2018 NXP
> +#
> +# This program and the accompanying materials are licensed and made available
> +# under the terms and conditions of the BSD License which accompanies this
> +# distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
> +# IMPLIED.
> +#
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = PciHostBridgeLib
> + FILE_GUID = f4c99bcc-5c95-49ad-b0f3-fc5b611dc9c1
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = PciHostBridgeLib
> +
> +[Sources]
> + PciHostBridgeLib.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[LibraryClasses]
> + DebugLib
> + DevicePathLib
> + IoAccessLib
> + MemoryAllocationLib
> + PcdLib
> + SocLib
> + UefiBootServicesTableLib
> +
> +[Pcd]
> + gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian
> + gNxpQoriqLsTokenSpaceGuid.PcdNumPciController
> + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase
> + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciDebug
> --
> 1.9.1
>
next prev parent reply other threads:[~2018-12-21 18:31 UTC|newest]
Thread overview: 254+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
2018-02-16 8:49 ` [PATCH edk2-platforms 01/39] Silicon/NXP: Add support for Big Endian Mmio APIs Meenakshi
2018-02-21 15:46 ` Leif Lindholm
2018-02-21 16:06 ` Laszlo Ersek
2018-02-21 18:58 ` Leif Lindholm
2018-02-22 4:45 ` Meenakshi Aggarwal
2018-02-22 8:34 ` Laszlo Ersek
2018-02-22 11:52 ` Leif Lindholm
2018-02-22 13:56 ` Laszlo Ersek
2018-02-23 8:40 ` Pankaj Bansal
2018-02-23 9:21 ` Laszlo Ersek
2018-02-23 9:47 ` Meenakshi Aggarwal
2018-02-23 10:17 ` Laszlo Ersek
2018-02-23 10:39 ` Udit Kumar
2018-02-23 10:59 ` Laszlo Ersek
2018-02-23 11:04 ` Pankaj Bansal
2018-02-23 11:22 ` Laszlo Ersek
2018-02-23 11:48 ` Pankaj Bansal
2018-02-23 15:17 ` Laszlo Ersek
2018-02-23 11:21 ` Udit Kumar
2018-02-23 10:25 ` Udit Kumar
2018-02-23 10:47 ` Laszlo Ersek
2018-02-23 11:48 ` Udit Kumar
2018-02-23 15:15 ` Laszlo Ersek
2018-02-28 13:19 ` Leif Lindholm
2018-02-22 4:49 ` Udit Kumar
2018-02-16 8:49 ` [PATCH edk2-platforms 02/39] Silicon/NXP : Add support for Watchdog driver Meenakshi
2018-02-16 8:49 ` [PATCH edk2-platforms 03/39] SocLib : Add support for initialization of peripherals Meenakshi
2018-04-18 15:12 ` Leif Lindholm
2018-04-18 16:38 ` Meenakshi Aggarwal
2018-04-18 18:15 ` Leif Lindholm
2018-04-19 4:59 ` Meenakshi Aggarwal
2018-02-16 8:50 ` [PATCH edk2-platforms 04/39] Silicon/NXP : Add support for DUART library Meenakshi
2018-04-18 15:15 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 05/39] Silicon/NXP: Add support for I2c driver Meenakshi
2018-04-17 16:36 ` Leif Lindholm
2018-04-23 8:21 ` Meenakshi Aggarwal
2018-04-23 8:38 ` Leif Lindholm
2018-04-23 10:34 ` Meenakshi Aggarwal
2018-04-23 13:39 ` Ard Biesheuvel
2018-04-23 15:50 ` Meenakshi Aggarwal
2018-04-23 15:53 ` Ard Biesheuvel
2018-02-16 8:50 ` [PATCH edk2-platforms 06/39] Silicon/Maxim : Add support for DS1307 RTC library Meenakshi
2018-04-18 15:27 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 07/39] Platform/NXP: Add support for ArmPlatformLib Meenakshi
2018-04-18 15:32 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 08/39] Compilation : Add the fdf, dsc and dec files Meenakshi
2018-04-18 15:38 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 09/39] Build : Add build script and environment script Meenakshi
2018-02-21 16:02 ` Leif Lindholm
2018-02-22 4:58 ` Meenakshi Aggarwal
2018-02-16 8:50 ` [PATCH edk2-platforms 10/39] IFC : Add Header file for IFC controller Meenakshi
2018-04-18 18:31 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 11/39] LS1043/BoardLib : Add support for LS1043 BoardLib Meenakshi
2018-04-18 18:34 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 12/39] Silicon/NXP : Add support of IfcLib Meenakshi
2018-04-18 18:39 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 13/39] LS1043/FpgaLib : Add support for FpgaLib Meenakshi
2018-04-18 18:43 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 14/39] LS1043 : Enable support of FpgaLib Meenakshi
2018-04-18 18:43 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 15/39] Silicon/NXP : Add support of NorFlashLib Meenakshi
2018-04-18 19:26 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 16/39] Silicon/NXP : Add NOR driver Meenakshi
2018-04-17 16:23 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 17/39] LS1043 : Enable NOR driver for LS1043aRDB package Meenakshi
2018-04-19 9:54 ` Leif Lindholm
2018-04-19 10:14 ` Meenakshi Aggarwal
2018-02-16 8:50 ` [PATCH edk2-platforms 18/39] Silicon/NXP:Add LS1046ARDB SoCLib Support Meenakshi
2018-04-19 10:00 ` Leif Lindholm
2018-04-19 10:05 ` Meenakshi Aggarwal
2018-04-19 10:20 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 19/39] Silicon/NXP:Add support for PCF2129 Real Time Clock Library Meenakshi
2018-04-19 10:11 ` Leif Lindholm
2018-04-19 12:33 ` Meenakshi Aggarwal
2018-04-19 13:47 ` Leif Lindholm
2018-04-20 3:20 ` Meenakshi Aggarwal
2018-02-16 8:50 ` [PATCH edk2-platforms 20/39] Platform/NXP: LS1046A RDB Board Library Meenakshi
2018-04-19 13:49 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 21/39] Platform/NXP: Add ArmPlatformLib for LS1046A Meenakshi
2018-04-19 13:53 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 22/39] Platform/NXP: LS1046 RDB Board FPGA library Meenakshi
2018-04-19 14:44 ` Leif Lindholm
2018-06-04 4:10 ` Meenakshi Aggarwal
2018-06-04 9:25 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 23/39] Platform/NXP: Compilation for LS1046A RDB Board Meenakshi
2018-04-19 14:54 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 24/39] Silicon/NXP:SocLib support for initialization of peripherals Meenakshi
2018-04-19 15:20 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 25/39] Platform/NXP/LS2088aRdbPkg: ArmPlatformLib Support for LS2088ARDB Meenakshi
2018-04-19 15:59 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 26/39] Silicon/Maxim: DS3232 RTC Library Support Meenakshi
2018-04-19 16:02 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 27/39] Compilation : Add the fdf, dsc and dec files Meenakshi
2018-04-19 16:28 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 28/39] Platform/NXP: LS2088A RDB Board Library Meenakshi
2018-04-19 16:28 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 29/39] Platform/NXP: LS2088 RDB Board FPGA library Meenakshi
2018-04-19 16:30 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 30/39] LS2088 : Enable support of FpgaLib Meenakshi
2018-04-19 16:31 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 31/39] LS2088ARDB: Enable NOR driver and Runtime Services Meenakshi
2018-04-19 16:32 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 32/39] Silicon/NXP: Implement PciSegmentLib to support multiple RCs Meenakshi
2018-04-19 19:27 ` Leif Lindholm
2018-04-20 6:40 ` Vabhav Sharma
2018-04-20 12:41 ` Leif Lindholm
2018-04-24 12:30 ` Vabhav Sharma
2018-02-16 8:50 ` [PATCH edk2-platforms 33/39] Silicon/NXP: Implement PciHostBridgeLib support Meenakshi
2018-04-20 8:34 ` Ard Biesheuvel
2018-04-24 12:17 ` Vabhav Sharma
2018-04-20 14:54 ` Leif Lindholm
2018-04-24 12:32 ` Vabhav Sharma
2018-02-16 8:50 ` [PATCH edk2-platforms 34/39] Silicon/NXP: Implement EFI_CPU_IO2_PROTOCOL Meenakshi
2018-04-20 8:40 ` Ard Biesheuvel
2018-04-24 12:26 ` Vabhav Sharma
2018-04-24 12:33 ` Ard Biesheuvel
2018-04-24 13:36 ` Vabhav Sharma
2018-04-24 14:02 ` Ard Biesheuvel
2018-04-20 15:15 ` Leif Lindholm
2018-04-24 12:40 ` Vabhav Sharma
2018-02-16 8:50 ` [PATCH edk2-platforms 35/39] Compilation: Update the fdf, dsc and dec files Meenakshi
2018-04-20 15:22 ` Leif Lindholm
2018-04-24 12:47 ` Vabhav Sharma
2018-02-16 8:50 ` [PATCH edk2-platforms 36/39] DWC3 : Add DWC3 USB controller initialization driver Meenakshi
2018-04-20 15:30 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 37/39] LS2088 : Enable support of USB controller Meenakshi
2018-04-20 15:30 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 38/39] Platform/NXP:PCIe enablement for LS1046A RDB Meenakshi
2018-04-20 15:33 ` Leif Lindholm
2018-04-24 12:48 ` Vabhav Sharma
2018-02-16 8:50 ` [PATCH edk2-platforms 39/39] Platform/NXP:PCIe enablement for LS2088A RDB Meenakshi
2018-04-20 15:36 ` Leif Lindholm
2018-04-24 12:50 ` Vabhav Sharma
2018-04-17 16:44 ` [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Leif Lindholm
2018-04-20 16:15 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
2018-11-28 15:01 ` [PATCH edk2-platforms 01/41] Silicon/NXP: Add Library to return Mmio APIs pointer Meenakshi Aggarwal
2018-12-21 19:17 ` Leif Lindholm
2018-12-26 5:00 ` Meenakshi Aggarwal
2018-11-28 15:01 ` [PATCH edk2-platforms 02/41] Silicon/NXP : Add support for Watchdog driver Meenakshi Aggarwal
2018-12-17 17:36 ` Leif Lindholm
2019-01-29 5:32 ` Meenakshi Aggarwal
2018-11-28 15:01 ` [PATCH edk2-platforms 03/41] SocLib : Add support for initialization of peripherals Meenakshi Aggarwal
2018-12-18 12:31 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 04/41] Silicon/NXP : Add support for DUART library Meenakshi Aggarwal
2018-11-28 15:01 ` [PATCH edk2-platforms 05/41] Silicon/NXP: Add support for I2c driver Meenakshi Aggarwal
2018-12-18 17:25 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 06/41] Silicon/Maxim : Add support for DS1307 RTC library Meenakshi Aggarwal
2018-11-28 15:01 ` [PATCH edk2-platforms 07/41] Platform/NXP: Add support for ArmPlatformLib Meenakshi Aggarwal
2018-11-28 15:01 ` [PATCH edk2-platforms 08/41] Platform/NXP: Add Platform driver for LS1043 RDB board Meenakshi Aggarwal
2018-12-18 17:47 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 09/41] Compilation : Add the fdf, dsc and dec files Meenakshi Aggarwal
2018-12-18 18:35 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 10/41] Readme : Add Readme.md file Meenakshi Aggarwal
2018-12-18 18:41 ` Leif Lindholm
2019-02-01 5:43 ` Meenakshi Aggarwal
2018-11-28 15:01 ` [PATCH edk2-platforms 11/41] IFC : Add Header file for IFC controller Meenakshi Aggarwal
2018-12-18 18:45 ` Leif Lindholm
2019-02-01 5:55 ` Meenakshi Aggarwal
2018-11-28 15:01 ` [PATCH edk2-platforms 12/41] LS1043/BoardLib : Add support for LS1043 BoardLib Meenakshi Aggarwal
2018-12-18 18:50 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 13/41] Silicon/NXP : Add support of IfcLib Meenakshi Aggarwal
2018-12-19 13:25 ` Leif Lindholm
2019-02-01 6:53 ` Meenakshi Aggarwal
2018-11-28 15:01 ` [PATCH edk2-platforms 14/41] Silicon/NXP : Add support for FpgaLib Meenakshi Aggarwal
2018-12-19 17:37 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 15/41] LS1043 : Enable support of FpgaLib Meenakshi Aggarwal
2018-11-28 15:01 ` [PATCH edk2-platforms 16/41] Silicon/NXP : Add support of NorFlashLib Meenakshi Aggarwal
2018-12-19 18:13 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 17/41] Silicon/NXP : Add NOR driver Meenakshi Aggarwal
2018-12-19 18:32 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 18/41] LS1043 : Enable NOR driver for LS1043aRDB package Meenakshi Aggarwal
2018-12-19 18:33 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 19/41] Silicon/NXP:Add LS1046ARDB SoCLib Support Meenakshi Aggarwal
2018-12-19 18:41 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 20/41] Silicon/NXP:Add support for PCF2129 Real Time Clock Library Meenakshi Aggarwal
2018-12-19 18:52 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 21/41] Platform/NXP: LS1046A RDB Board Library Meenakshi Aggarwal
2018-12-19 18:54 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 22/41] Platform/NXP: Add ArmPlatformLib for LS1046A Meenakshi Aggarwal
2018-12-19 19:08 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 23/41] Platform/NXP: Add Platform driver for LS1046 RDB board Meenakshi Aggarwal
2018-12-19 22:05 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 24/41] Platform/NXP: Compilation for LS1046A RDB Board Meenakshi Aggarwal
2018-12-20 17:39 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 25/41] Silicon/NXP:SocLib support for initialization of peripherals Meenakshi Aggarwal
2018-12-21 9:22 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 26/41] Platform/NXP/LS2088aRdbPkg: ArmPlatformLib Support for LS2088ARDB Meenakshi Aggarwal
2018-12-21 9:30 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 27/41] Platform/NXP: Add Platform driver for LS2088 RDB board Meenakshi Aggarwal
2018-12-21 9:35 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 28/41] Silicon/Maxim: DS3232 RTC Library Support Meenakshi Aggarwal
2018-12-21 9:56 ` Leif Lindholm
2018-12-21 10:01 ` Ard Biesheuvel
2018-11-28 15:01 ` [PATCH edk2-platforms 29/41] Compilation : Add the fdf, dsc and dec files Meenakshi Aggarwal
2018-12-21 10:17 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 30/41] Platform/NXP: LS2088A RDB Board Library Meenakshi Aggarwal
2018-12-21 10:20 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 31/41] Platform/NXP: LS2088 RDB Board FPGA library Meenakshi Aggarwal
2018-12-21 10:22 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 32/41] LS2088 : Enable support of FpgaLib Meenakshi Aggarwal
2018-12-21 10:23 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 33/41] LS2088ARDB: Enable NOR driver and Runtime Services Meenakshi Aggarwal
2018-12-21 10:24 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 34/41] Silicon/NXP: Implement PciSegmentLib to support multiple RCs Meenakshi Aggarwal
2018-12-21 10:44 ` Ard Biesheuvel
2018-12-21 14:01 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 35/41] Silicon/NXP: Implement PciHostBridgeLib support Meenakshi Aggarwal
2018-12-21 10:51 ` Ard Biesheuvel
2018-12-21 18:30 ` Leif Lindholm [this message]
2018-11-28 15:01 ` [PATCH edk2-platforms 36/41] Silicon/NXP: Implement EFI_CPU_IO2_PROTOCOL Meenakshi Aggarwal
2018-12-21 11:09 ` Ard Biesheuvel
2018-12-21 18:49 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 37/41] Compilation: Update the fdf, dsc and dec files Meenakshi Aggarwal
2018-12-21 18:51 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 38/41] DWC3 : Add DWC3 USB controller initialization driver Meenakshi Aggarwal
2018-12-21 19:03 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 39/41] LS2088 : Enable support of USB controller Meenakshi Aggarwal
2018-11-28 15:01 ` [PATCH edk2-platforms 40/41] Platform/NXP:PCIe enablement for LS1046A RDB Meenakshi Aggarwal
2018-12-21 19:05 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 41/41] Platform/NXP:PCIe enablement for LS2088A RDB Meenakshi Aggarwal
2018-12-21 19:05 ` Leif Lindholm
2018-12-17 9:50 ` [PATCH edk2-platforms 00/41] NXP : Add support of LS1043, LS1046 and LS2088 SoCs Leif Lindholm
[not found] ` <1570639758-30355-1-git-send-email-meenakshi.aggarwal@nxp.com>
[not found] ` <1570639758-30355-2-git-send-email-meenakshi.aggarwal@nxp.com>
2019-10-10 10:17 ` [PATCH edk2-platforms 01/12] Silicon/NXP: Add Library to provide Mmio APIs with swapped data Leif Lindholm
[not found] ` <1570639758-30355-3-git-send-email-meenakshi.aggarwal@nxp.com>
2019-10-10 10:23 ` [PATCH edk2-platforms 02/12] Silicon/NXP: Add function to return swapped Mmio APIs pointer Leif Lindholm
[not found] ` <1570639758-30355-4-git-send-email-meenakshi.aggarwal@nxp.com>
2019-10-10 10:39 ` [PATCH edk2-platforms 03/12] Silicon/NXP : Add support for Watchdog driver Leif Lindholm
[not found] ` <1570639758-30355-5-git-send-email-meenakshi.aggarwal@nxp.com>
2019-10-10 11:17 ` [PATCH edk2-platforms 04/12] SocLib : Add support for initialization of peripherals Leif Lindholm
[not found] ` <1570639758-30355-7-git-send-email-meenakshi.aggarwal@nxp.com>
2019-10-10 14:51 ` [PATCH edk2-platforms 06/12] Silicon/NXP: Add support for I2c driver Leif Lindholm
[not found] ` <1570639758-30355-9-git-send-email-meenakshi.aggarwal@nxp.com>
2019-10-10 15:07 ` [PATCH edk2-platforms 08/12] Silicon/NXP : Add MemoryInitPei Library Leif Lindholm
[not found] ` <1570639758-30355-11-git-send-email-meenakshi.aggarwal@nxp.com>
2019-10-10 15:12 ` [PATCH edk2-platforms 10/12] Platform/NXP: Add Platform driver for LS1043 RDB board Leif Lindholm
[not found] ` <1570639758-30355-12-git-send-email-meenakshi.aggarwal@nxp.com>
2019-10-10 15:17 ` [PATCH edk2-platforms 11/12] Compilation : Add the fdf, dsc and dec files Leif Lindholm
[not found] ` <1570639758-30355-13-git-send-email-meenakshi.aggarwal@nxp.com>
2019-10-10 15:19 ` [PATCH edk2-platforms 12/12] Readme : Add Readme.md file Leif Lindholm
2019-10-10 15:27 ` [PATCH edk2-platforms 00/12] NXP : Add support of LS1043 SoC Leif Lindholm
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 00/11] " Meenakshi Aggarwal
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 01/11] Silicon/NXP: Add Library to provide Mmio APIs with swapped data Meenakshi Aggarwal
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 02/11] Silicon/NXP: Add function to return swapped Mmio APIs pointer Meenakshi Aggarwal
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 03/11] SocLib : Add support for initialization of peripherals Meenakshi Aggarwal
2019-11-26 16:43 ` Leif Lindholm
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 04/11] Silicon/NXP : Add support for DUART library Meenakshi Aggarwal
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 05/11] Silicon/NXP: Add support for I2c driver Meenakshi Aggarwal
2019-11-26 17:00 ` Leif Lindholm
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 06/11] Silicon/Maxim : Add support for DS1307 RTC library Meenakshi Aggarwal
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 07/11] Silicon/NXP : Add MemoryInitPei Library Meenakshi Aggarwal
2019-11-26 16:55 ` [edk2-devel] " Leif Lindholm
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 08/11] Platform/NXP: Add support for ArmPlatformLib Meenakshi Aggarwal
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 09/11] Platform/NXP: Add Platform driver for LS1043 RDB board Meenakshi Aggarwal
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 10/11] Compilation : Add the fdf, dsc and dec files Meenakshi Aggarwal
2019-11-26 16:56 ` [edk2-devel] " Leif Lindholm
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 11/11] Readme : Add Readme.md file Meenakshi Aggarwal
2019-11-26 16:58 ` Leif Lindholm
2020-01-24 22:25 ` [edk2-platforms] [PATCH v3 00/11] Add support of LS1043 SoC Meenakshi Aggarwal
2020-01-24 22:25 ` [edk2-platforms] [PATCH v3 03/11] SocLib : Add support for initialization of peripherals Meenakshi Aggarwal
2020-01-24 22:25 ` [edk2-platforms] [PATCH v3 08/11] Silicon/NXP : Add MemoryInitPei Library Meenakshi Aggarwal
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