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[92.154.90.120]) by smtp.gmail.com with ESMTPSA id z17sm22268820wrv.2.2018.12.26.05.25.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Dec 2018 05:25:37 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Wed, 26 Dec 2018 14:25:28 +0100 Message-Id: <20181226132530.8445-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181226132530.8445-1-ard.biesheuvel@linaro.org> References: <20181226132530.8445-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Subject: [PATCH edk2-platforms 1/3] Silicon/SynQuacer/AcpiTables: don't use PCD for PL011 base X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 26 Dec 2018 13:25:41 -0000 Content-Transfer-Encoding: 8bit Instead of using the generic PcdSerialRegisterBase PCD for generating the DSDT object for the PL011 UART, add PL011 base and size #defines to the memory map header file, and use those instead. This will allow us to switch to a different UART for DEBUG and/or serial console output in a future patch. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf | 1 - Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h | 4 ++++ Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl | 2 +- Silicon/Socionext/SynQuacer/AcpiTables/Spcr.aslc | 3 ++- 4 files changed, 7 insertions(+), 3 deletions(-) diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf index afee50df5c63..6fbdf4d67a88 100644 --- a/Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf +++ b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf @@ -59,7 +59,6 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase gSynQuacerTokenSpaceGuid.PcdNetsecEepromBase gSynQuacerTokenSpaceGuid.PcdNetsecPhyAddress diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h index fff760477488..28d4afabd2c8 100644 --- a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h +++ b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h @@ -72,4 +72,8 @@ #define SYNQUACER_MMIO_TIMER_CTL_BASE 0x2A810000 #define SYNQUACER_MMIO_TIMER_CNT_BASE0 0x2A830000 +// PL011 UART +#define SYNQUACER_UART0_BASE 0x2A400000 +#define SYNQUACER_UART0_SIZE SIZE_4KB + #endif diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl index 7c7677f1fea0..ddb456d1dc70 100644 --- a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl @@ -137,7 +137,7 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "SNI", "SYNQUACR", Name (_HID, "ARMH0011") Name (_UID, Zero) Name (_CRS, ResourceTemplate () { - Memory32Fixed (ReadWrite, FixedPcdGet32 (PcdSerialRegisterBase), 0x1000) + Memory32Fixed (ReadWrite, SYNQUACER_UART0_BASE, SYNQUACER_UART0_SIZE) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 95 } }) } diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Spcr.aslc b/Silicon/Socionext/SynQuacer/AcpiTables/Spcr.aslc index 699e79e1bf59..c549a9781c8c 100644 --- a/Silicon/Socionext/SynQuacer/AcpiTables/Spcr.aslc +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Spcr.aslc @@ -19,6 +19,7 @@ #include #include +#include #include "AcpiTables.h" @@ -47,7 +48,7 @@ STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = { 32, 0, EFI_ACPI_5_1_DWORD, - FixedPcdGet32 (PcdSerialRegisterBase) + SYNQUACER_UART0_BASE }, // // InterruptType -- 2.19.2